1 |
2 |
dimamali |
-----------------------------------------------------------------------------
|
2 |
|
|
-- LEON3 Demonstration design test bench
|
3 |
|
|
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
|
4 |
|
|
--
|
5 |
|
|
-- This program is free software; you can redistribute it and/or modify
|
6 |
|
|
-- it under the terms of the GNU General Public License as published by
|
7 |
|
|
-- the Free Software Foundation; either version 2 of the License, or
|
8 |
|
|
-- (at your option) any later version.
|
9 |
|
|
--
|
10 |
|
|
-- This program is distributed in the hope that it will be useful,
|
11 |
|
|
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
12 |
|
|
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
13 |
|
|
-- GNU General Public License for more details.
|
14 |
|
|
------------------------------------------------------------------------------
|
15 |
|
|
|
16 |
|
|
library ieee;
|
17 |
|
|
use ieee.std_logic_1164.all;
|
18 |
|
|
library gaisler;
|
19 |
|
|
use gaisler.libdcom.all;
|
20 |
|
|
use gaisler.sim.all;
|
21 |
|
|
library techmap;
|
22 |
|
|
use techmap.gencomp.all;
|
23 |
|
|
library micron;
|
24 |
|
|
use micron.components.all;
|
25 |
|
|
use work.debug.all;
|
26 |
|
|
|
27 |
|
|
use work.config.all; -- configuration
|
28 |
|
|
|
29 |
|
|
entity testbench is
|
30 |
|
|
generic (
|
31 |
|
|
fabtech : integer := CFG_FABTECH;
|
32 |
|
|
memtech : integer := CFG_MEMTECH;
|
33 |
|
|
padtech : integer := CFG_PADTECH;
|
34 |
|
|
clktech : integer := CFG_CLKTECH;
|
35 |
|
|
ncpu : integer := CFG_NCPU;
|
36 |
|
|
disas : integer := CFG_DISAS; -- Enable disassembly to console
|
37 |
|
|
dbguart : integer := CFG_DUART; -- Print UART on console
|
38 |
|
|
pclow : integer := CFG_PCLOW;
|
39 |
|
|
|
40 |
|
|
clkperiod : integer := 25; -- system clock period
|
41 |
|
|
romwidth : integer := 32; -- rom data width (8/32)
|
42 |
|
|
romdepth : integer := 16; -- rom address depth
|
43 |
|
|
sramwidth : integer := 32; -- ram data width (8/16/32)
|
44 |
|
|
sramdepth : integer := 18; -- ram address depth
|
45 |
|
|
srambanks : integer := 2 -- number of ram banks
|
46 |
|
|
);
|
47 |
|
|
port (
|
48 |
|
|
pci_rst : inout std_logic; -- PCI bus
|
49 |
|
|
pci_clk : in std_logic;
|
50 |
|
|
pci_gnt : in std_logic;
|
51 |
|
|
pci_idsel : in std_logic;
|
52 |
|
|
pci_lock : inout std_logic;
|
53 |
|
|
pci_ad : inout std_logic_vector(31 downto 0);
|
54 |
|
|
pci_cbe : inout std_logic_vector(3 downto 0);
|
55 |
|
|
pci_frame : inout std_logic;
|
56 |
|
|
pci_irdy : inout std_logic;
|
57 |
|
|
pci_trdy : inout std_logic;
|
58 |
|
|
pci_devsel : inout std_logic;
|
59 |
|
|
pci_stop : inout std_logic;
|
60 |
|
|
pci_perr : inout std_logic;
|
61 |
|
|
pci_par : inout std_logic;
|
62 |
|
|
pci_req : inout std_logic;
|
63 |
|
|
pci_serr : inout std_logic;
|
64 |
|
|
pci_host : in std_logic;
|
65 |
|
|
pci_66 : in std_logic
|
66 |
|
|
);
|
67 |
|
|
|
68 |
|
|
end;
|
69 |
|
|
|
70 |
|
|
architecture behav of testbench is
|
71 |
|
|
|
72 |
|
|
constant promfile : string := "prom.srec"; -- rom contents
|
73 |
|
|
constant sramfile : string := "sram.srec"; -- ram contents
|
74 |
|
|
constant sdramfile : string := "sdram.srec"; -- sdram contents
|
75 |
|
|
|
76 |
|
|
signal sys_clk : std_logic := '0';
|
77 |
|
|
signal sys_rst_in : std_logic := '0'; -- Reset
|
78 |
|
|
constant ct : integer := clkperiod/2;
|
79 |
|
|
|
80 |
|
|
signal errorn : std_logic;
|
81 |
|
|
signal address : std_logic_vector(27 downto 0);
|
82 |
|
|
signal data : std_logic_vector(15 downto 0);
|
83 |
|
|
signal xdata : std_logic_vector(31 downto 0);
|
84 |
|
|
signal romsn : std_logic;
|
85 |
|
|
signal iosn : std_logic;
|
86 |
|
|
signal writen, read : std_logic;
|
87 |
|
|
signal oen : std_logic;
|
88 |
|
|
signal flash_rstn : std_logic;
|
89 |
|
|
signal ddr_clk : std_logic_vector(1 downto 0);
|
90 |
|
|
signal ddr_clkb : std_logic_vector(1 downto 0);
|
91 |
|
|
signal ddr_clk_fb : std_logic;
|
92 |
|
|
signal ddr_clk_fb_out : std_logic;
|
93 |
|
|
signal ddr_cke : std_logic_vector(1 downto 0);
|
94 |
|
|
signal ddr_csb : std_logic_vector(1 downto 0);
|
95 |
|
|
signal ddr_web : std_logic; -- ddr write enable
|
96 |
|
|
signal ddr_rasb : std_logic; -- ddr ras
|
97 |
|
|
signal ddr_casb : std_logic; -- ddr cas
|
98 |
|
|
signal ddr_dm : std_logic_vector (7 downto 0); -- ddr dm
|
99 |
|
|
signal ddr_dqs : std_logic_vector (7 downto 0); -- ddr dqs
|
100 |
|
|
signal ddr_ad : std_logic_vector (12 downto 0); -- ddr address
|
101 |
|
|
signal ddr_ba : std_logic_vector (1 downto 0); -- ddr bank address
|
102 |
|
|
signal ddr_dq : std_logic_vector (63 downto 0); -- ddr data
|
103 |
|
|
signal txd1 : std_logic; -- UART1 tx data
|
104 |
|
|
signal rxd1 : std_logic; -- UART1 rx data
|
105 |
|
|
signal gpio : std_logic_vector(31 downto 0); -- I/O port
|
106 |
|
|
signal flash_cex : std_logic;
|
107 |
|
|
|
108 |
|
|
signal clk125 : std_logic := '0';
|
109 |
|
|
signal GND : std_logic := '0';
|
110 |
|
|
signal VCC : std_logic := '1';
|
111 |
|
|
signal NC : std_logic := 'Z';
|
112 |
|
|
constant lresp : boolean := false;
|
113 |
|
|
|
114 |
|
|
signal dsuen : std_logic;
|
115 |
|
|
signal dsubre : std_logic;
|
116 |
|
|
signal dsuact : std_logic;
|
117 |
|
|
begin
|
118 |
|
|
|
119 |
|
|
-- clock and reset
|
120 |
|
|
|
121 |
|
|
sys_clk <= not sys_clk after ct * 1 ns;
|
122 |
|
|
sys_rst_in <= '0', '1' after 200 ns;
|
123 |
|
|
rxd1 <= 'H'; errorn <= 'H';
|
124 |
|
|
ddr_clk_fb <= ddr_clk_fb_out;
|
125 |
|
|
|
126 |
|
|
clk125 <= not clk125 after 6.75 ns;
|
127 |
|
|
|
128 |
|
|
cpu : entity work.leon3mp
|
129 |
|
|
generic map ( fabtech, memtech, padtech, ncpu, disas, dbguart, pclow )
|
130 |
|
|
port map ( sys_rst_in, sys_clk, clk125, errorn, flash_rstn, address,
|
131 |
|
|
data, dsuen, dsubre, dsuact, oen, writen, read, iosn, romsn,
|
132 |
|
|
ddr_clk, ddr_clkb, ddr_clk_fb, ddr_clk_fb_out, ddr_cke, ddr_csb,
|
133 |
|
|
ddr_web, ddr_rasb, ddr_casb, ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq,
|
134 |
|
|
txd1, rxd1,
|
135 |
|
|
-- gpio,
|
136 |
|
|
pci_rst, pci_clk, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe,
|
137 |
|
|
pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr, pci_par,
|
138 |
|
|
pci_req, pci_serr, pci_host, pci_66
|
139 |
|
|
);
|
140 |
|
|
|
141 |
|
|
ddrmem : for i in 0 to 1 generate
|
142 |
|
|
u3 : mt46v16m16
|
143 |
|
|
generic map (index => 3, fname => sdramfile, bbits => 64)
|
144 |
|
|
PORT MAP(
|
145 |
|
|
Dq => ddr_dq(15 downto 0), Dqs => ddr_dqs(1 downto 0), Addr => ddr_ad,
|
146 |
|
|
Ba => ddr_ba, Clk => ddr_clk(i), Clk_n => ddr_clkb(i), Cke => ddr_cke(i),
|
147 |
|
|
Cs_n => ddr_csb(i), Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web,
|
148 |
|
|
Dm => ddr_dm(1 downto 0));
|
149 |
|
|
|
150 |
|
|
u2 : mt46v16m16
|
151 |
|
|
generic map (index => 2, fname => sdramfile, bbits => 64)
|
152 |
|
|
PORT MAP(
|
153 |
|
|
Dq => ddr_dq(31 downto 16), Dqs => ddr_dqs(3 downto 2), Addr => ddr_ad,
|
154 |
|
|
Ba => ddr_ba, Clk => ddr_clk(i), Clk_n => ddr_clkb(i), Cke => ddr_cke(i),
|
155 |
|
|
Cs_n => ddr_csb(i), Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web,
|
156 |
|
|
Dm => ddr_dm(3 downto 2));
|
157 |
|
|
u1 : mt46v16m16
|
158 |
|
|
generic map (index => 1, fname => sdramfile, bbits => 64)
|
159 |
|
|
PORT MAP(
|
160 |
|
|
Dq => ddr_dq(47 downto 32), Dqs => ddr_dqs(5 downto 4), Addr => ddr_ad,
|
161 |
|
|
Ba => ddr_ba, Clk => ddr_clk(i), Clk_n => ddr_clkb(i), Cke => ddr_cke(i),
|
162 |
|
|
Cs_n => ddr_csb(i), Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web,
|
163 |
|
|
Dm => ddr_dm(5 downto 4));
|
164 |
|
|
|
165 |
|
|
u0 : mt46v16m16
|
166 |
|
|
generic map (index => 0, fname => sdramfile, bbits => 64)
|
167 |
|
|
PORT MAP(
|
168 |
|
|
Dq => ddr_dq(63 downto 48), Dqs => ddr_dqs(7 downto 6), Addr => ddr_ad,
|
169 |
|
|
Ba => ddr_ba, Clk => ddr_clk(i), Clk_n => ddr_clkb(i), Cke => ddr_cke(i),
|
170 |
|
|
Cs_n => ddr_csb(i), Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web,
|
171 |
|
|
Dm => ddr_dm(7 downto 6));
|
172 |
|
|
end generate;
|
173 |
|
|
|
174 |
|
|
prom0 : sram16 generic map (index => 4, abits => romdepth, fname => promfile)
|
175 |
|
|
port map (address(romdepth-1 downto 0), data,
|
176 |
|
|
gnd, gnd, romsn, writen, oen);
|
177 |
|
|
|
178 |
|
|
iuerr : process
|
179 |
|
|
begin
|
180 |
|
|
wait for 5000 ns;
|
181 |
|
|
if to_x01(errorn) = '1' then wait on errorn; end if;
|
182 |
|
|
assert (to_x01(errorn) = '1')
|
183 |
|
|
report "*** IU in error mode, simulation halted ***"
|
184 |
|
|
severity failure ;
|
185 |
|
|
end process;
|
186 |
|
|
|
187 |
|
|
xdata <= "0000000000000000" & data;
|
188 |
|
|
test0 : grtestmod
|
189 |
|
|
port map ( sys_rst_in, sys_clk, errorn, address(20 downto 1), xdata,
|
190 |
|
|
iosn, oen, writen, open);
|
191 |
|
|
|
192 |
|
|
|
193 |
|
|
data <= buskeep(data), (others => 'H') after 250 ns;
|
194 |
|
|
ddr_dq <= buskeep(ddr_dq), (others => 'H') after 250 ns;
|
195 |
|
|
|
196 |
|
|
end ;
|
197 |
|
|
|