URL https://opencores.org/ocsvn/mips_enhanced/mips_enhanced/trunk

Subversion Repositories mips_enhanced

[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [designs/] [leon3-digilent-xc3s1000/] [testbench.vhd] - Blame information for rev 2

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-----------------------------------------------------------------------------
--  LEON3 Demonstration design test bench
--  Copyright (C) 2004 Jiri Gaisler, Gaisler Research
--
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License as published by
--  the Free Software Foundation; either version 2 of the License, or
--  (at your option) any later version.
--
--  This program is distributed in the hope that it will be useful,
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--  GNU General Public License for more details.
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
use work.debug.all;
 
use work.config.all;    -- configuration
 
entity testbench is
  generic (
    fabtech   : integer := CFG_FABTECH;
    memtech   : integer := CFG_MEMTECH;
    padtech   : integer := CFG_PADTECH;
    clktech   : integer := CFG_CLKTECH;
    disas     : integer := CFG_DISAS;   -- Enable disassembly to console
    dbguart   : integer := CFG_DUART;   -- Print UART on console
    pclow     : integer := CFG_PCLOW;
 
    clkperiod : integer := 20;          -- system clock period
    romwidth  : integer := 32;          -- rom data width (8/32)
    romdepth  : integer := 16;          -- rom address depth
    sramwidth  : integer := 32;         -- ram data width (8/16/32)
    sramdepth  : integer := 18;         -- ram address depth
    srambanks  : integer := 2           -- number of ram banks
  );
end;
 
architecture behav of testbench is
 
constant promfile  : string := "prom.srec";  -- rom contents
constant sramfile  : string := "sram.srec";  -- ram contents
constant sdramfile : string := "sdram.srec"; -- sdram contents
 
signal clk : std_logic := '0';
signal Rst : std_logic := '0';                   -- Reset
constant ct : integer := clkperiod/2;
 
signal address  : std_logic_vector(19 downto 0);
signal data     : std_logic_vector(31 downto 0);
signal mben     : std_logic_vector(3 downto 0);
signal pio      : std_logic_vector(17 downto 0);
signal ramsn    : std_logic_vector(1 downto 0);
signal oen      : std_ulogic;
signal writen   : std_ulogic;
signal dsuen, dsutx, dsurx, dsubre, dsuact : std_ulogic;
signal dsurst   : std_ulogic;
signal GND      : std_ulogic := '0';
signal VCC      : std_ulogic := '1';
signal NC       : std_ulogic := 'Z';
signal clk2     : std_ulogic := '1';
 
signal txd1, rxd1 : std_logic;
signal txd2, rxd2 : std_logic;
signal errorn   : std_logic;
 
signal ps2clk      : std_logic;
signal ps2data     : std_logic;
 
signal vid_hsync   : std_ulogic;
signal vid_vsync   : std_ulogic;
signal vid_r       : std_logic;
signal vid_g       : std_logic;
signal vid_b       : std_logic;
signal switch      : std_logic_vector(7 downto 0);       -- switches
signal button      : std_logic_vector(2 downto 0);
constant lresp : boolean := false;
 
begin
 
-- clock and reset
 
  clk  <= not clk after ct * 1 ns;
  rst <= dsurst; dsuen <= '1'; dsubre <= '0';
  rxd1 <= 'H';
  ps2clk <= 'H'; ps2data <= 'H';
  pio(4) <= pio(5); pio(1) <= pio(2); pio <= (others => 'H');
  address(1 downto 0) <= "00";
 
  cpu : entity work.leon3mp
      generic map ( fabtech, memtech, padtech, clktech, disas, dbguart, pclow)
      port map (rst, clk, errorn, address(19 downto 2), data,
        ramsn, mben, oen, writen,
        dsubre, dsuact, txd1, rxd1, pio, --switch, button,
        ps2clk, ps2data,
        vid_hsync, vid_vsync, vid_r, vid_g, vid_b
      );
 
  sram0 : for i in 0 to 1 generate
      sr0 : sram16 generic map (index => i*2, abits => 18, fname => sdramfile)
        port map (address(19 downto 2), data(31-i*16 downto 16-i*16),
                mben(i*2), mben(i*2+1), ramsn(i), writen, oen);
  end generate;
 
 
   iuerr : process
   begin
     wait for 5000 ns;
     if to_x01(errorn) = '0' then wait on errorn; end if;
     assert (to_x01(errorn) = '0')
       report "*** IU in error mode, simulation halted ***"
         severity failure ;
   end process;
 
  data <= buskeep(data), (others => 'H') after 250 ns;
 
  dsucom : process
    procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
    variable w32 : std_logic_vector(31 downto 0);
    variable c8  : std_logic_vector(7 downto 0);
    constant txp : time := 320 * 1 ns;
    begin
    dsutx <= '1';
    dsurst <= '1';
    wait for 2500 ns;
    dsurst <= '0';
    wait;
    wait for 5000 ns;
    txc(dsutx, 16#55#, txp);            -- sync uart
 
    txc(dsutx, 16#c0#, txp);
    txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
    txa(dsutx, 16#00#, 16#00#, 16#20#, 16#2e#, txp);
 
    wait for 25000 ns;
    txc(dsutx, 16#c0#, txp);
    txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
    txa(dsutx, 16#00#, 16#00#, 16#00#, 16#01#, txp);
 
    txc(dsutx, 16#c0#, txp);
    txa(dsutx, 16#90#, 16#40#, 16#00#, 16#24#, txp);
    txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0D#, txp);
 
    txc(dsutx, 16#c0#, txp);
    txa(dsutx, 16#90#, 16#70#, 16#11#, 16#78#, txp);
    txa(dsutx, 16#91#, 16#00#, 16#00#, 16#0D#, txp);
 
    txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
    txa(dsutx, 16#00#, 16#00#, 16#20#, 16#00#, txp);
 
    txc(dsutx, 16#80#, txp);
    txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
 
    wait;
    txc(dsutx, 16#c0#, txp);
    txa(dsutx, 16#00#, 16#00#, 16#0a#, 16#aa#, txp);
    txa(dsutx, 16#00#, 16#55#, 16#00#, 16#55#, txp);
    txc(dsutx, 16#c0#, txp);
    txa(dsutx, 16#00#, 16#00#, 16#0a#, 16#a0#, txp);
    txa(dsutx, 16#01#, 16#02#, 16#09#, 16#33#, txp);
 
    txc(dsutx, 16#c0#, txp);
    txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
    txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2e#, txp);
    txc(dsutx, 16#c0#, txp);
    txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
    txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2e#, txp);
    txc(dsutx, 16#c0#, txp);
    txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
    txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
    txc(dsutx, 16#c0#, txp);
    txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
    txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
    txc(dsutx, 16#c0#, txp);
    txa(dsutx, 16#80#, 16#00#, 16#02#, 16#10#, txp);
    txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
 
    txc(dsutx, 16#c0#, txp);
    txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
    txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
    txc(dsutx, 16#c0#, txp);
    txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
    txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
 
 
 
 
 
    txc(dsutx, 16#c0#, txp);
    txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
    txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
 
    txc(dsutx, 16#c0#, txp);
    txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
    txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
 
    txc(dsutx, 16#c0#, txp);
    txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
    txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
 
    txc(dsutx, 16#80#, txp);
    txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
    rxi(dsurx, w32, txp, lresp);
 
    txc(dsutx, 16#a0#, txp);
    txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
    rxi(dsurx, w32, txp, lresp);
 
    end;
 
  begin
 
    dsucfg(txd2, rxd2);
 
    wait;
  end process;
end ;
 

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Subversion Repositories mips_enhanced

[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [designs/] [leon3-digilent-xc3s1000/] [testbench.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	dimamali	`-----------------------------------------------------------------------------`
2			`-- LEON3 Demonstration design test bench`
3			`-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research`
4			`--`
5			`-- This program is free software; you can redistribute it and/or modify`
6			`-- it under the terms of the GNU General Public License as published by`
7			`-- the Free Software Foundation; either version 2 of the License, or`
8			`-- (at your option) any later version.`
9			`--`
10			`-- This program is distributed in the hope that it will be useful,`
11			`-- but WITHOUT ANY WARRANTY; without even the implied warranty of`
12			`-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
13			`-- GNU General Public License for more details.`
14			`------------------------------------------------------------------------------`
15
16			`library ieee;`
17			`use ieee.std_logic_1164.all;`
18			`library gaisler;`
19			`use gaisler.libdcom.all;`
20			`use gaisler.sim.all;`
21			`library techmap;`
22			`use techmap.gencomp.all;`
23			`use work.debug.all;`
24
25			`use work.config.all; -- configuration`
26
27			`entity testbench is`
28			`generic (`
29			`fabtech : integer := CFG_FABTECH;`
30			`memtech : integer := CFG_MEMTECH;`
31			`padtech : integer := CFG_PADTECH;`
32			`clktech : integer := CFG_CLKTECH;`
33			`disas : integer := CFG_DISAS; -- Enable disassembly to console`
34			`dbguart : integer := CFG_DUART; -- Print UART on console`
35			`pclow : integer := CFG_PCLOW;`
36
37			`clkperiod : integer := 20; -- system clock period`
38			`romwidth : integer := 32; -- rom data width (8/32)`
39			`romdepth : integer := 16; -- rom address depth`
40			`sramwidth : integer := 32; -- ram data width (8/16/32)`
41			`sramdepth : integer := 18; -- ram address depth`
42			`srambanks : integer := 2 -- number of ram banks`
43			`);`
44			`end;`
45
46			`architecture behav of testbench is`
47
48			`constant promfile : string := "prom.srec"; -- rom contents`
49			`constant sramfile : string := "sram.srec"; -- ram contents`
50			`constant sdramfile : string := "sdram.srec"; -- sdram contents`
51
52			`signal clk : std_logic := '0';`
53			`signal Rst : std_logic := '0'; -- Reset`
54			`constant ct : integer := clkperiod/2;`
55
56			`signal address : std_logic_vector(19 downto 0);`
57			`signal data : std_logic_vector(31 downto 0);`
58			`signal mben : std_logic_vector(3 downto 0);`
59			`signal pio : std_logic_vector(17 downto 0);`
60			`signal ramsn : std_logic_vector(1 downto 0);`
61			`signal oen : std_ulogic;`
62			`signal writen : std_ulogic;`
63			`signal dsuen, dsutx, dsurx, dsubre, dsuact : std_ulogic;`
64			`signal dsurst : std_ulogic;`
65			`signal GND : std_ulogic := '0';`
66			`signal VCC : std_ulogic := '1';`
67			`signal NC : std_ulogic := 'Z';`
68			`signal clk2 : std_ulogic := '1';`
69
70			`signal txd1, rxd1 : std_logic;`
71			`signal txd2, rxd2 : std_logic;`
72			`signal errorn : std_logic;`
73
74			`signal ps2clk : std_logic;`
75			`signal ps2data : std_logic;`
76
77			`signal vid_hsync : std_ulogic;`
78			`signal vid_vsync : std_ulogic;`
79			`signal vid_r : std_logic;`
80			`signal vid_g : std_logic;`
81			`signal vid_b : std_logic;`
82			`signal switch : std_logic_vector(7 downto 0); -- switches`
83			`signal button : std_logic_vector(2 downto 0);`
84			`constant lresp : boolean := false;`
85
86			`begin`
87
88			`-- clock and reset`
89
90			`clk <= not clk after ct * 1 ns;`
91			`rst <= dsurst; dsuen <= '1'; dsubre <= '0';`
92			`rxd1 <= 'H';`
93			`ps2clk <= 'H'; ps2data <= 'H';`
94			`pio(4) <= pio(5); pio(1) <= pio(2); pio <= (others => 'H');`
95			`address(1 downto 0) <= "00";`
96
97			`cpu : entity work.leon3mp`
98			`generic map ( fabtech, memtech, padtech, clktech, disas, dbguart, pclow)`
99			`port map (rst, clk, errorn, address(19 downto 2), data,`
100			`ramsn, mben, oen, writen,`
101			`dsubre, dsuact, txd1, rxd1, pio, --switch, button,`
102			`ps2clk, ps2data,`
103			`vid_hsync, vid_vsync, vid_r, vid_g, vid_b`
104			`);`
105
106			`sram0 : for i in 0 to 1 generate`
107			`sr0 : sram16 generic map (index => i*2, abits => 18, fname => sdramfile)`
108			`port map (address(19 downto 2), data(31-i16 downto 16-i16),`
109			`mben(i2), mben(i2+1), ramsn(i), writen, oen);`
110			`end generate;`
111
112
113			`iuerr : process`
114			`begin`
115			`wait for 5000 ns;`
116			`if to_x01(errorn) = '0' then wait on errorn; end if;`
117			`assert (to_x01(errorn) = '0')`
118			`report "* IU in error mode, simulation halted *"`
119			`severity failure ;`
120			`end process;`
121
122			`data <= buskeep(data), (others => 'H') after 250 ns;`
123
124			`dsucom : process`
125			`procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is`
126			`variable w32 : std_logic_vector(31 downto 0);`
127			`variable c8 : std_logic_vector(7 downto 0);`
128			`constant txp : time := 320 * 1 ns;`
129			`begin`
130			`dsutx <= '1';`
131			`dsurst <= '1';`
132			`wait for 2500 ns;`
133			`dsurst <= '0';`
134			`wait;`
135			`wait for 5000 ns;`
136			`txc(dsutx, 16#55#, txp); -- sync uart`
137
138			`txc(dsutx, 16#c0#, txp);`
139			`txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);`
140			`txa(dsutx, 16#00#, 16#00#, 16#20#, 16#2e#, txp);`
141
142			`wait for 25000 ns;`
143			`txc(dsutx, 16#c0#, txp);`
144			`txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);`
145			`txa(dsutx, 16#00#, 16#00#, 16#00#, 16#01#, txp);`
146
147			`txc(dsutx, 16#c0#, txp);`
148			`txa(dsutx, 16#90#, 16#40#, 16#00#, 16#24#, txp);`
149			`txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0D#, txp);`
150
151			`txc(dsutx, 16#c0#, txp);`
152			`txa(dsutx, 16#90#, 16#70#, 16#11#, 16#78#, txp);`
153			`txa(dsutx, 16#91#, 16#00#, 16#00#, 16#0D#, txp);`
154
155			`txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);`
156			`txa(dsutx, 16#00#, 16#00#, 16#20#, 16#00#, txp);`
157
158			`txc(dsutx, 16#80#, txp);`
159			`txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);`
160
161			`wait;`
162			`txc(dsutx, 16#c0#, txp);`
163			`txa(dsutx, 16#00#, 16#00#, 16#0a#, 16#aa#, txp);`
164			`txa(dsutx, 16#00#, 16#55#, 16#00#, 16#55#, txp);`
165			`txc(dsutx, 16#c0#, txp);`
166			`txa(dsutx, 16#00#, 16#00#, 16#0a#, 16#a0#, txp);`
167			`txa(dsutx, 16#01#, 16#02#, 16#09#, 16#33#, txp);`
168
169			`txc(dsutx, 16#c0#, txp);`
170			`txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);`
171			`txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2e#, txp);`
172			`txc(dsutx, 16#c0#, txp);`
173			`txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);`
174			`txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2e#, txp);`
175			`txc(dsutx, 16#c0#, txp);`
176			`txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);`
177			`txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);`
178			`txc(dsutx, 16#c0#, txp);`
179			`txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);`
180			`txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);`
181			`txc(dsutx, 16#c0#, txp);`
182			`txa(dsutx, 16#80#, 16#00#, 16#02#, 16#10#, txp);`
183			`txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);`
184
185			`txc(dsutx, 16#c0#, txp);`
186			`txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);`
187			`txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);`
188			`txc(dsutx, 16#c0#, txp);`
189			`txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);`
190			`txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);`
191
192
193
194
195
196			`txc(dsutx, 16#c0#, txp);`
197			`txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);`
198			`txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);`
199
200			`txc(dsutx, 16#c0#, txp);`
201			`txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);`
202			`txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);`
203
204			`txc(dsutx, 16#c0#, txp);`
205			`txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);`
206			`txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);`
207
208			`txc(dsutx, 16#80#, txp);`
209			`txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);`
210			`rxi(dsurx, w32, txp, lresp);`
211
212			`txc(dsutx, 16#a0#, txp);`
213			`txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);`
214			`rxi(dsurx, w32, txp, lresp);`
215
216			`end;`
217
218			`begin`
219
220			`dsucfg(txd2, rxd2);`
221
222			`wait;`
223			`end process;`
224			`end ;`
225