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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [designs/] [leon3-digilent-xc3s1000/] [tkconfig.h] - Blame information for rev 2

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#if defined CONFIG_SYN_INFERRED
#define CONFIG_SYN_TECH inferred
#elif defined CONFIG_SYN_UMC
#define CONFIG_SYN_TECH umc
#elif defined CONFIG_SYN_RHUMC
#define CONFIG_SYN_TECH rhumc
#elif defined CONFIG_SYN_ATC18
#define CONFIG_SYN_TECH atc18s
#elif defined CONFIG_SYN_AXCEL
#define CONFIG_SYN_TECH axcel
#elif defined CONFIG_SYN_PROASICPLUS
#define CONFIG_SYN_TECH proasic
#elif defined CONFIG_SYN_ALTERA
#define CONFIG_SYN_TECH altera
#elif defined CONFIG_SYN_STRATIX
#define CONFIG_SYN_TECH stratix1
#elif defined CONFIG_SYN_STRATIXII
#define CONFIG_SYN_TECH stratix2
#elif defined CONFIG_SYN_STRATIXIII
#define CONFIG_SYN_TECH stratix3
#elif defined CONFIG_SYN_CYCLONEIII
#define CONFIG_SYN_TECH cyclone3
#elif defined CONFIG_SYN_EASIC90
#define CONFIG_SYN_TECH easic90
#elif defined CONFIG_SYN_IHP25
#define CONFIG_SYN_TECH ihp25
#elif defined CONFIG_SYN_IHP25RH
#define CONFIG_SYN_TECH ihp25rh
#elif defined CONFIG_SYN_LATTICE
#define CONFIG_SYN_TECH lattice
#elif defined CONFIG_SYN_ECLIPSE
#define CONFIG_SYN_TECH eclipse
#elif defined CONFIG_SYN_PEREGRINE
#define CONFIG_SYN_TECH peregrine
#elif defined CONFIG_SYN_PROASIC
#define CONFIG_SYN_TECH proasic
#elif defined CONFIG_SYN_PROASIC3
#define CONFIG_SYN_TECH apa3
#elif defined CONFIG_SYN_SPARTAN2
#define CONFIG_SYN_TECH virtex
#elif defined CONFIG_SYN_VIRTEX
#define CONFIG_SYN_TECH virtex
#elif defined CONFIG_SYN_VIRTEXE
#define CONFIG_SYN_TECH virtex
#elif defined CONFIG_SYN_SPARTAN3
#define CONFIG_SYN_TECH spartan3
#elif defined CONFIG_SYN_SPARTAN3E
#define CONFIG_SYN_TECH spartan3e
#elif defined CONFIG_SYN_VIRTEX2
#define CONFIG_SYN_TECH virtex2
#elif defined CONFIG_SYN_VIRTEX4
#define CONFIG_SYN_TECH virtex4
#elif defined CONFIG_SYN_VIRTEX5
#define CONFIG_SYN_TECH virtex5
#elif defined CONFIG_SYN_RH_LIB18T
#define CONFIG_SYN_TECH rhlib18t
#elif defined CONFIG_SYN_UT025CRH
#define CONFIG_SYN_TECH ut25
#elif defined CONFIG_SYN_TSMC90
#define CONFIG_SYN_TECH tsmc90
#elif defined CONFIG_SYN_CUSTOM1
#define CONFIG_SYN_TECH custom1
#else
#error "unknown target technology"
#endif
 
#if defined CONFIG_SYN_INFER_RAM
#define CFG_RAM_TECH inferred
#elif defined CONFIG_MEM_UMC
#define CFG_RAM_TECH umc
#elif defined CONFIG_MEM_RHUMC
#define CFG_RAM_TECH rhumc
#elif defined CONFIG_MEM_VIRAGE
#define CFG_RAM_TECH memvirage
#elif defined CONFIG_MEM_ARTISAN
#define CFG_RAM_TECH memartisan
#elif defined CONFIG_MEM_CUSTOM1
#define CFG_RAM_TECH custom1
#elif defined CONFIG_MEM_VIRAGE90
#define CFG_RAM_TECH memvirage90
#elif defined CONFIG_MEM_INFERRED
#define CFG_RAM_TECH inferred
#else
#define CFG_RAM_TECH CONFIG_SYN_TECH
#endif
 
#if defined CONFIG_SYN_INFER_PADS
#define CFG_PAD_TECH inferred
#else
#define CFG_PAD_TECH CONFIG_SYN_TECH
#endif
 
#ifndef CONFIG_SYN_NO_ASYNC
#define CONFIG_SYN_NO_ASYNC 0
#endif
 
#ifndef CONFIG_SYN_SCAN
#define CONFIG_SYN_SCAN 0
#endif
 
 
#if defined CONFIG_CLK_ALTDLL
#define CFG_CLK_TECH CONFIG_SYN_TECH
#elif defined CONFIG_CLK_HCLKBUF
#define CFG_CLK_TECH axcel
#elif defined CONFIG_CLK_LATDLL
#define CFG_CLK_TECH lattice
#elif defined CONFIG_CLK_PRO3PLL
#define CFG_CLK_TECH apa3
#elif defined CONFIG_CLK_CLKDLL
#define CFG_CLK_TECH virtex
#elif defined CONFIG_CLK_DCM
#define CFG_CLK_TECH CONFIG_SYN_TECH
#elif defined CONFIG_CLK_LIB18T
#define CFG_CLK_TECH rhlib18t
#elif defined CONFIG_CLK_RHUMC
#define CFG_CLK_TECH rhumc
#else
#define CFG_CLK_TECH inferred
#endif
 
#ifndef CONFIG_CLK_MUL
#define CONFIG_CLK_MUL 2
#endif
 
#ifndef CONFIG_CLK_DIV
#define CONFIG_CLK_DIV 2
#endif
 
#ifndef CONFIG_OCLK_DIV
#define CONFIG_OCLK_DIV 2
#endif
 
#ifndef CONFIG_PCI_CLKDLL
#define CONFIG_PCI_CLKDLL 0
#endif
 
#ifndef CONFIG_PCI_SYSCLK
#define CONFIG_PCI_SYSCLK 0
#endif
 
#ifndef CONFIG_CLK_NOFB
#define CONFIG_CLK_NOFB 0
#endif
#ifndef CONFIG_LEON3
#define CONFIG_LEON3 0
#endif
 
#ifndef CONFIG_PROC_NUM
#define CONFIG_PROC_NUM 1
#endif
 
#ifndef CONFIG_IU_NWINDOWS
#define CONFIG_IU_NWINDOWS 8
#endif
 
#ifndef CONFIG_IU_RSTADDR
#define CONFIG_IU_RSTADDR 8
#endif
 
#ifndef CONFIG_IU_LDELAY
#define CONFIG_IU_LDELAY 1
#endif
 
#ifndef CONFIG_IU_WATCHPOINTS
#define CONFIG_IU_WATCHPOINTS 0
#endif
 
#ifdef CONFIG_IU_V8MULDIV
#ifdef CONFIG_IU_MUL_LATENCY_4
#define CFG_IU_V8 1
#else
#define CFG_IU_V8 2
#endif
#else
#define CFG_IU_V8 0
#endif
#ifndef CONFIG_PWD
#define CONFIG_PWD 0
#endif
 
#ifndef CONFIG_IU_MUL_MAC
#define CONFIG_IU_MUL_MAC 0
#endif
 
#ifndef CONFIG_IU_SVT
#define CONFIG_IU_SVT 0
#endif
 
#if defined CONFIG_FPU_GRFPC1
#define CONFIG_FPU_GRFPC 1
#elif defined CONFIG_FPU_GRFPC2
#define CONFIG_FPU_GRFPC 2
#else
#define CONFIG_FPU_GRFPC 0
#endif
 
#if defined CONFIG_FPU_GRFPU_INFMUL
#define CONFIG_FPU_GRFPU_MUL 0
#elif defined CONFIG_FPU_GRFPU_DWMUL
#define CONFIG_FPU_GRFPU_MUL 1
#elif defined CONFIG_FPU_GRFPU_MODGEN 
#define CONFIG_FPU_GRFPU_MUL 2
#else
#define CONFIG_FPU_GRFPU_MUL 0
#endif
 
#if defined CONFIG_FPU_GRFPU_SH
#define CONFIG_FPU_GRFPU_SHARED 1
#else
#define CONFIG_FPU_GRFPU_SHARED 0
#endif
 
#if defined CONFIG_FPU_GRFPU
#define CONFIG_FPU (1+CONFIG_FPU_GRFPU_MUL)
#elif defined CONFIG_FPU_MEIKO
#define CONFIG_FPU 15
#elif defined CONFIG_FPU_GRFPULITE
#define CONFIG_FPU (8+CONFIG_FPU_GRFPC)
#else
#define CONFIG_FPU 0
#endif
 
#ifndef CONFIG_FPU_NETLIST
#define CONFIG_FPU_NETLIST 0
#endif
 
#ifndef CONFIG_ICACHE_ENABLE
#define CONFIG_ICACHE_ENABLE 0
#endif
 
#if defined CONFIG_ICACHE_ASSO1
#define CFG_IU_ISETS 1
#elif defined CONFIG_ICACHE_ASSO2
#define CFG_IU_ISETS 2
#elif defined CONFIG_ICACHE_ASSO3
#define CFG_IU_ISETS 3
#elif defined CONFIG_ICACHE_ASSO4
#define CFG_IU_ISETS 4
#else
#define CFG_IU_ISETS 1
#endif
 
#if defined CONFIG_ICACHE_SZ1
#define CFG_ICACHE_SZ 1
#elif defined CONFIG_ICACHE_SZ2
#define CFG_ICACHE_SZ 2
#elif defined CONFIG_ICACHE_SZ4
#define CFG_ICACHE_SZ 4
#elif defined CONFIG_ICACHE_SZ8
#define CFG_ICACHE_SZ 8
#elif defined CONFIG_ICACHE_SZ16
#define CFG_ICACHE_SZ 16
#elif defined CONFIG_ICACHE_SZ32
#define CFG_ICACHE_SZ 32
#elif defined CONFIG_ICACHE_SZ64
#define CFG_ICACHE_SZ 64
#elif defined CONFIG_ICACHE_SZ128
#define CFG_ICACHE_SZ 128
#elif defined CONFIG_ICACHE_SZ256
#define CFG_ICACHE_SZ 256
#else
#define CFG_ICACHE_SZ 1
#endif
 
#ifdef CONFIG_ICACHE_LZ16
#define CFG_ILINE_SZ 4
#else
#define CFG_ILINE_SZ 8
#endif
 
#if defined CONFIG_ICACHE_ALGORND
#define CFG_ICACHE_ALGORND 2
#elif defined CONFIG_ICACHE_ALGOLRR
#define CFG_ICACHE_ALGORND 1
#else
#define CFG_ICACHE_ALGORND 0
#endif
 
#ifndef CONFIG_ICACHE_LOCK
#define CONFIG_ICACHE_LOCK 0
#endif
 
#ifndef CONFIG_ICACHE_LRAM
#define CONFIG_ICACHE_LRAM 0
#endif
 
#ifndef CONFIG_ICACHE_LRSTART
#define CONFIG_ICACHE_LRSTART 8E
#endif
 
#if defined CONFIG_ICACHE_LRAM_SZ2
#define CFG_ILRAM_SIZE 2
#elif defined CONFIG_ICACHE_LRAM_SZ4
#define CFG_ILRAM_SIZE 4
#elif defined CONFIG_ICACHE_LRAM_SZ8
#define CFG_ILRAM_SIZE 8
#elif defined CONFIG_ICACHE_LRAM_SZ16
#define CFG_ILRAM_SIZE 16
#elif defined CONFIG_ICACHE_LRAM_SZ32
#define CFG_ILRAM_SIZE 32
#elif defined CONFIG_ICACHE_LRAM_SZ64
#define CFG_ILRAM_SIZE 64
#elif defined CONFIG_ICACHE_LRAM_SZ128
#define CFG_ILRAM_SIZE 128
#elif defined CONFIG_ICACHE_LRAM_SZ256
#define CFG_ILRAM_SIZE 256
#else
#define CFG_ILRAM_SIZE 1
#endif
 
 
#ifndef CONFIG_DCACHE_ENABLE
#define CONFIG_DCACHE_ENABLE 0
#endif
 
#if defined CONFIG_DCACHE_ASSO1
#define CFG_IU_DSETS 1
#elif defined CONFIG_DCACHE_ASSO2
#define CFG_IU_DSETS 2
#elif defined CONFIG_DCACHE_ASSO3
#define CFG_IU_DSETS 3
#elif defined CONFIG_DCACHE_ASSO4
#define CFG_IU_DSETS 4
#else
#define CFG_IU_DSETS 1
#endif
 
#if defined CONFIG_DCACHE_SZ1
#define CFG_DCACHE_SZ 1
#elif defined CONFIG_DCACHE_SZ2
#define CFG_DCACHE_SZ 2
#elif defined CONFIG_DCACHE_SZ4
#define CFG_DCACHE_SZ 4
#elif defined CONFIG_DCACHE_SZ8
#define CFG_DCACHE_SZ 8
#elif defined CONFIG_DCACHE_SZ16
#define CFG_DCACHE_SZ 16
#elif defined CONFIG_DCACHE_SZ32
#define CFG_DCACHE_SZ 32
#elif defined CONFIG_DCACHE_SZ64
#define CFG_DCACHE_SZ 64
#elif defined CONFIG_DCACHE_SZ128
#define CFG_DCACHE_SZ 128
#elif defined CONFIG_DCACHE_SZ256
#define CFG_DCACHE_SZ 256
#else
#define CFG_DCACHE_SZ 1
#endif
 
#ifdef CONFIG_DCACHE_LZ16
#define CFG_DLINE_SZ 4
#else
#define CFG_DLINE_SZ 8
#endif
 
#if defined CONFIG_DCACHE_ALGORND
#define CFG_DCACHE_ALGORND 2
#elif defined CONFIG_DCACHE_ALGOLRR
#define CFG_DCACHE_ALGORND 1
#else
#define CFG_DCACHE_ALGORND 0
#endif
 
#ifndef CONFIG_DCACHE_LOCK
#define CONFIG_DCACHE_LOCK 0
#endif
 
#ifndef CONFIG_DCACHE_SNOOP
#define CONFIG_DCACHE_SNOOP 0
#endif
 
#ifndef CONFIG_DCACHE_SNOOP_FAST
#define CONFIG_DCACHE_SNOOP_FAST 0
#endif
 
#ifndef CONFIG_DCACHE_SNOOP_SEPTAG
#define CONFIG_DCACHE_SNOOP_SEPTAG 0
#endif
 
#ifndef CONFIG_CACHE_FIXED
#define CONFIG_CACHE_FIXED 0
#endif
 
#ifndef CONFIG_DCACHE_LRAM
#define CONFIG_DCACHE_LRAM 0
#endif
 
#ifndef CONFIG_DCACHE_LRSTART
#define CONFIG_DCACHE_LRSTART 8F
#endif
 
#if defined CONFIG_DCACHE_LRAM_SZ2
#define CFG_DLRAM_SIZE 2
#elif defined CONFIG_DCACHE_LRAM_SZ4
#define CFG_DLRAM_SIZE 4
#elif defined CONFIG_DCACHE_LRAM_SZ8
#define CFG_DLRAM_SIZE 8
#elif defined CONFIG_DCACHE_LRAM_SZ16
#define CFG_DLRAM_SIZE 16
#elif defined CONFIG_DCACHE_LRAM_SZ32
#define CFG_DLRAM_SIZE 32
#elif defined CONFIG_DCACHE_LRAM_SZ64
#define CFG_DLRAM_SIZE 64
#elif defined CONFIG_DCACHE_LRAM_SZ128
#define CFG_DLRAM_SIZE 128
#elif defined CONFIG_DCACHE_LRAM_SZ256
#define CFG_DLRAM_SIZE 256
#else
#define CFG_DLRAM_SIZE 1
#endif
 
 
#ifdef CONFIG_MMU_ENABLE
#define CONFIG_MMUEN 1
 
#ifdef CONFIG_MMU_SPLIT
#define CONFIG_TLB_TYPE 0
#endif
#ifdef CONFIG_MMU_COMBINED
#define CONFIG_TLB_TYPE 1
#endif
 
#ifdef CONFIG_MMU_REPARRAY
#define CONFIG_TLB_REP 0
#endif
#ifdef CONFIG_MMU_REPINCREMENT
#define CONFIG_TLB_REP 1
#endif
 
#ifdef CONFIG_MMU_I2 
#define CONFIG_ITLBNUM 2
#endif
#ifdef CONFIG_MMU_I4 
#define CONFIG_ITLBNUM 4
#endif
#ifdef CONFIG_MMU_I8 
#define CONFIG_ITLBNUM 8
#endif
#ifdef CONFIG_MMU_I16 
#define CONFIG_ITLBNUM 16
#endif
#ifdef CONFIG_MMU_I32
#define CONFIG_ITLBNUM 32
#endif
 
#define CONFIG_DTLBNUM 2
#ifdef CONFIG_MMU_D2 
#undef CONFIG_DTLBNUM 
#define CONFIG_DTLBNUM 2
#endif
#ifdef CONFIG_MMU_D4 
#undef CONFIG_DTLBNUM 
#define CONFIG_DTLBNUM 4
#endif
#ifdef CONFIG_MMU_D8 
#undef CONFIG_DTLBNUM 
#define CONFIG_DTLBNUM 8
#endif
#ifdef CONFIG_MMU_D16 
#undef CONFIG_DTLBNUM 
#define CONFIG_DTLBNUM 16
#endif
#ifdef CONFIG_MMU_D32
#undef CONFIG_DTLBNUM 
#define CONFIG_DTLBNUM 32
#endif
#ifdef CONFIG_MMU_FASTWB
#define CFG_MMU_FASTWB 1
#else
#define CFG_MMU_FASTWB 0
#endif
 
#else
#define CONFIG_MMUEN 0
#define CONFIG_ITLBNUM 2
#define CONFIG_DTLBNUM 2
#define CONFIG_TLB_TYPE 1
#define CONFIG_TLB_REP 1
#define CFG_MMU_FASTWB 0
#endif
 
#ifndef CONFIG_DSU_ENABLE
#define CONFIG_DSU_ENABLE 0
#endif
 
#if defined CONFIG_DSU_ITRACESZ1
#define CFG_DSU_ITB 1
#elif CONFIG_DSU_ITRACESZ2
#define CFG_DSU_ITB 2
#elif CONFIG_DSU_ITRACESZ4
#define CFG_DSU_ITB 4
#elif CONFIG_DSU_ITRACESZ8
#define CFG_DSU_ITB 8
#elif CONFIG_DSU_ITRACESZ16
#define CFG_DSU_ITB 16
#else
#define CFG_DSU_ITB 0
#endif
 
#if defined CONFIG_DSU_ATRACESZ1
#define CFG_DSU_ATB 1
#elif CONFIG_DSU_ATRACESZ2
#define CFG_DSU_ATB 2
#elif CONFIG_DSU_ATRACESZ4
#define CFG_DSU_ATB 4
#elif CONFIG_DSU_ATRACESZ8
#define CFG_DSU_ATB 8
#elif CONFIG_DSU_ATRACESZ16
#define CFG_DSU_ATB 16
#else
#define CFG_DSU_ATB 0
#endif
 
#ifndef CONFIG_LEON3FT_EN
#define CONFIG_LEON3FT_EN 0
#endif
 
#if defined CONFIG_IUFT_PAR
#define CONFIG_IUFT_EN 1
#elif defined CONFIG_IUFT_DMR
#define CONFIG_IUFT_EN 2
#elif defined CONFIG_IUFT_BCH
#define CONFIG_IUFT_EN 3
#elif defined CONFIG_IUFT_TMR
#define CONFIG_IUFT_EN 4
#else
#define CONFIG_IUFT_EN 0
#endif
#ifndef CONFIG_RF_ERRINJ
#define CONFIG_RF_ERRINJ 0
#endif
 
#ifndef CONFIG_FPUFT_EN
#define CONFIG_FPUFT 0
#else
#ifdef CONFIG_FPU_GRFPU
#define CONFIG_FPUFT 2
#else
#define CONFIG_FPUFT 1
#endif
#endif
 
#ifndef CONFIG_CACHE_FT_EN
#define CONFIG_CACHE_FT_EN 0
#endif
#ifndef CONFIG_CACHE_ERRINJ
#define CONFIG_CACHE_ERRINJ 0
#endif
 
#ifndef CONFIG_LEON3_NETLIST
#define CONFIG_LEON3_NETLIST 0
#endif
 
#ifdef CONFIG_DEBUG_PC32
#define CFG_DEBUG_PC32 0 
#else
#define CFG_DEBUG_PC32 2
#endif
#ifndef CONFIG_IU_DISAS
#define CONFIG_IU_DISAS 0
#endif
#ifndef CONFIG_IU_DISAS_NET
#define CONFIG_IU_DISAS_NET 0
#endif
 
 
#ifndef CONFIG_AHB_SPLIT
#define CONFIG_AHB_SPLIT 0
#endif
 
#ifndef CONFIG_AHB_RROBIN
#define CONFIG_AHB_RROBIN 0
#endif
 
#ifndef CONFIG_AHB_IOADDR
#define CONFIG_AHB_IOADDR FFF
#endif
 
#ifndef CONFIG_APB_HADDR
#define CONFIG_APB_HADDR 800
#endif
 
#ifndef CONFIG_AHB_MON
#define CONFIG_AHB_MON 0
#endif
 
#ifndef CONFIG_AHB_MONERR
#define CONFIG_AHB_MONERR 0
#endif
 
#ifndef CONFIG_AHB_MONWAR
#define CONFIG_AHB_MONWAR 0
#endif
 
#ifndef CONFIG_DSU_JTAG
#define CONFIG_DSU_JTAG 0
#endif
 
#ifndef CONFIG_MCTRL_LEON2
#define CONFIG_MCTRL_LEON2 0
#endif
 
#ifndef CONFIG_MCTRL_SDRAM
#define CONFIG_MCTRL_SDRAM 0
#endif
 
#ifndef CONFIG_MCTRL_SDRAM_SEPBUS
#define CONFIG_MCTRL_SDRAM_SEPBUS 0
#endif
 
#ifndef CONFIG_MCTRL_SDRAM_INVCLK
#define CONFIG_MCTRL_SDRAM_INVCLK 0
#endif
 
#ifndef CONFIG_MCTRL_SDRAM_BUS64
#define CONFIG_MCTRL_SDRAM_BUS64 0
#endif
 
#ifndef CONFIG_MCTRL_8BIT
#define CONFIG_MCTRL_8BIT 0
#endif
 
#ifndef CONFIG_MCTRL_16BIT
#define CONFIG_MCTRL_16BIT 0
#endif
 
#ifndef CONFIG_MCTRL_5CS
#define CONFIG_MCTRL_5CS 0
#endif
 
#ifndef CONFIG_MCTRL_EDAC
#define CONFIG_MCTRL_EDAC 0
#endif
 
#ifndef CONFIG_MCTRL_PAGE
#define CONFIG_MCTRL_PAGE 0
#endif
 
#ifndef CONFIG_MCTRL_PROGPAGE
#define CONFIG_MCTRL_PROGPAGE 0
#endif
 
#ifndef CONFIG_AHBROM_ENABLE
#define CONFIG_AHBROM_ENABLE 0
#endif
 
#ifndef CONFIG_AHBROM_START
#define CONFIG_AHBROM_START 000
#endif
 
#ifndef CONFIG_AHBROM_PIPE
#define CONFIG_AHBROM_PIPE 0
#endif
 
#if (CONFIG_AHBROM_START == 0) && (CONFIG_AHBROM_ENABLE == 1)
#define CONFIG_ROM_START 100
#else
#define CONFIG_ROM_START 000
#endif
 
 
#ifndef CONFIG_AHBRAM_ENABLE
#define CONFIG_AHBRAM_ENABLE 0
#endif
 
#ifndef CONFIG_AHBRAM_START
#define CONFIG_AHBRAM_START A00
#endif
 
#if defined CONFIG_AHBRAM_SZ1
#define CFG_AHBRAMSZ 1
#elif CONFIG_AHBRAM_SZ2
#define CFG_AHBRAMSZ 2
#elif CONFIG_AHBRAM_SZ4
#define CFG_AHBRAMSZ 4
#elif CONFIG_AHBRAM_SZ8
#define CFG_AHBRAMSZ 8
#elif CONFIG_AHBRAM_SZ16
#define CFG_AHBRAMSZ 16
#elif CONFIG_AHBRAM_SZ32
#define CFG_AHBRAMSZ 32
#elif CONFIG_AHBRAM_SZ64
#define CFG_AHBRAMSZ 64
#else
#define CFG_AHBRAMSZ 1
#endif
 
#ifndef CONFIG_UART1_ENABLE
#define CONFIG_UART1_ENABLE 0
#endif
 
#if defined CONFIG_UA1_FIFO1
#define CFG_UA1_FIFO 1
#elif defined CONFIG_UA1_FIFO2
#define CFG_UA1_FIFO 2
#elif defined CONFIG_UA1_FIFO4
#define CFG_UA1_FIFO 4
#elif defined CONFIG_UA1_FIFO8
#define CFG_UA1_FIFO 8
#elif defined CONFIG_UA1_FIFO16
#define CFG_UA1_FIFO 16
#elif defined CONFIG_UA1_FIFO32
#define CFG_UA1_FIFO 32
#else
#define CFG_UA1_FIFO 1
#endif
 
#ifndef CONFIG_IRQ3_ENABLE
#define CONFIG_IRQ3_ENABLE 0
#endif
#ifndef CONFIG_GPT_ENABLE
#define CONFIG_GPT_ENABLE 0
#endif
 
#ifndef CONFIG_GPT_NTIM
#define CONFIG_GPT_NTIM 1
#endif
 
#ifndef CONFIG_GPT_SW
#define CONFIG_GPT_SW 8
#endif
 
#ifndef CONFIG_GPT_TW
#define CONFIG_GPT_TW 8
#endif
 
#ifndef CONFIG_GPT_IRQ
#define CONFIG_GPT_IRQ 8
#endif
 
#ifndef CONFIG_GPT_SEPIRQ
#define CONFIG_GPT_SEPIRQ 0
#endif
#ifndef CONFIG_GPT_ENABLE
#define CONFIG_GPT_ENABLE 0
#endif
 
#ifndef CONFIG_GPT_NTIM
#define CONFIG_GPT_NTIM 1
#endif
 
#ifndef CONFIG_GPT_SW
#define CONFIG_GPT_SW 8
#endif
 
#ifndef CONFIG_GPT_TW
#define CONFIG_GPT_TW 8
#endif
 
#ifndef CONFIG_GPT_IRQ
#define CONFIG_GPT_IRQ 8
#endif
 
#ifndef CONFIG_GPT_SEPIRQ
#define CONFIG_GPT_SEPIRQ 0
#endif
 
#ifndef CONFIG_GPT_WDOGEN
#define CONFIG_GPT_WDOGEN 0
#endif
 
#ifndef CONFIG_GPT_WDOG
#define CONFIG_GPT_WDOG 0
#endif
 
#ifndef CONFIG_GRGPIO_ENABLE
#define CONFIG_GRGPIO_ENABLE 0
#endif
#ifndef CONFIG_GRGPIO_IMASK
#define CONFIG_GRGPIO_IMASK 0000
#endif
#ifndef CONFIG_GRGPIO_WIDTH
#define CONFIG_GRGPIO_WIDTH 1
#endif
 
#ifndef CONFIG_VGA_ENABLE
#define CONFIG_VGA_ENABLE 0
#endif
#ifndef CONFIG_SVGA_ENABLE
#define CONFIG_SVGA_ENABLE 0
#endif
#ifndef CONFIG_KBD_ENABLE
#define CONFIG_KBD_ENABLE 0
#endif
 
 
#ifndef CONFIG_DEBUG_UART
#define CONFIG_DEBUG_UART 0
#endif

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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [designs/] [leon3-digilent-xc3s1000/] [tkconfig.h] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	dimamali	`#if defined CONFIG_SYN_INFERRED`
2			`#define CONFIG_SYN_TECH inferred`
3			`#elif defined CONFIG_SYN_UMC`
4			`#define CONFIG_SYN_TECH umc`
5			`#elif defined CONFIG_SYN_RHUMC`
6			`#define CONFIG_SYN_TECH rhumc`
7			`#elif defined CONFIG_SYN_ATC18`
8			`#define CONFIG_SYN_TECH atc18s`
9			`#elif defined CONFIG_SYN_AXCEL`
10			`#define CONFIG_SYN_TECH axcel`
11			`#elif defined CONFIG_SYN_PROASICPLUS`
12			`#define CONFIG_SYN_TECH proasic`
13			`#elif defined CONFIG_SYN_ALTERA`
14			`#define CONFIG_SYN_TECH altera`
15			`#elif defined CONFIG_SYN_STRATIX`
16			`#define CONFIG_SYN_TECH stratix1`
17			`#elif defined CONFIG_SYN_STRATIXII`
18			`#define CONFIG_SYN_TECH stratix2`
19			`#elif defined CONFIG_SYN_STRATIXIII`
20			`#define CONFIG_SYN_TECH stratix3`
21			`#elif defined CONFIG_SYN_CYCLONEIII`
22			`#define CONFIG_SYN_TECH cyclone3`
23			`#elif defined CONFIG_SYN_EASIC90`
24			`#define CONFIG_SYN_TECH easic90`
25			`#elif defined CONFIG_SYN_IHP25`
26			`#define CONFIG_SYN_TECH ihp25`
27			`#elif defined CONFIG_SYN_IHP25RH`
28			`#define CONFIG_SYN_TECH ihp25rh`
29			`#elif defined CONFIG_SYN_LATTICE`
30			`#define CONFIG_SYN_TECH lattice`
31			`#elif defined CONFIG_SYN_ECLIPSE`
32			`#define CONFIG_SYN_TECH eclipse`
33			`#elif defined CONFIG_SYN_PEREGRINE`
34			`#define CONFIG_SYN_TECH peregrine`
35			`#elif defined CONFIG_SYN_PROASIC`
36			`#define CONFIG_SYN_TECH proasic`
37			`#elif defined CONFIG_SYN_PROASIC3`
38			`#define CONFIG_SYN_TECH apa3`
39			`#elif defined CONFIG_SYN_SPARTAN2`
40			`#define CONFIG_SYN_TECH virtex`
41			`#elif defined CONFIG_SYN_VIRTEX`
42			`#define CONFIG_SYN_TECH virtex`
43			`#elif defined CONFIG_SYN_VIRTEXE`
44			`#define CONFIG_SYN_TECH virtex`
45			`#elif defined CONFIG_SYN_SPARTAN3`
46			`#define CONFIG_SYN_TECH spartan3`
47			`#elif defined CONFIG_SYN_SPARTAN3E`
48			`#define CONFIG_SYN_TECH spartan3e`
49			`#elif defined CONFIG_SYN_VIRTEX2`
50			`#define CONFIG_SYN_TECH virtex2`
51			`#elif defined CONFIG_SYN_VIRTEX4`
52			`#define CONFIG_SYN_TECH virtex4`
53			`#elif defined CONFIG_SYN_VIRTEX5`
54			`#define CONFIG_SYN_TECH virtex5`
55			`#elif defined CONFIG_SYN_RH_LIB18T`
56			`#define CONFIG_SYN_TECH rhlib18t`
57			`#elif defined CONFIG_SYN_UT025CRH`
58			`#define CONFIG_SYN_TECH ut25`
59			`#elif defined CONFIG_SYN_TSMC90`
60			`#define CONFIG_SYN_TECH tsmc90`
61			`#elif defined CONFIG_SYN_CUSTOM1`
62			`#define CONFIG_SYN_TECH custom1`
63			`#else`
64			`#error "unknown target technology"`
65			`#endif`
66
67			`#if defined CONFIG_SYN_INFER_RAM`
68			`#define CFG_RAM_TECH inferred`
69			`#elif defined CONFIG_MEM_UMC`
70			`#define CFG_RAM_TECH umc`
71			`#elif defined CONFIG_MEM_RHUMC`
72			`#define CFG_RAM_TECH rhumc`
73			`#elif defined CONFIG_MEM_VIRAGE`
74			`#define CFG_RAM_TECH memvirage`
75			`#elif defined CONFIG_MEM_ARTISAN`
76			`#define CFG_RAM_TECH memartisan`
77			`#elif defined CONFIG_MEM_CUSTOM1`
78			`#define CFG_RAM_TECH custom1`
79			`#elif defined CONFIG_MEM_VIRAGE90`
80			`#define CFG_RAM_TECH memvirage90`
81			`#elif defined CONFIG_MEM_INFERRED`
82			`#define CFG_RAM_TECH inferred`
83			`#else`
84			`#define CFG_RAM_TECH CONFIG_SYN_TECH`
85			`#endif`
86
87			`#if defined CONFIG_SYN_INFER_PADS`
88			`#define CFG_PAD_TECH inferred`
89			`#else`
90			`#define CFG_PAD_TECH CONFIG_SYN_TECH`
91			`#endif`
92
93			`#ifndef CONFIG_SYN_NO_ASYNC`
94			`#define CONFIG_SYN_NO_ASYNC 0`
95			`#endif`
96
97			`#ifndef CONFIG_SYN_SCAN`
98			`#define CONFIG_SYN_SCAN 0`
99			`#endif`
100
101
102			`#if defined CONFIG_CLK_ALTDLL`
103			`#define CFG_CLK_TECH CONFIG_SYN_TECH`
104			`#elif defined CONFIG_CLK_HCLKBUF`
105			`#define CFG_CLK_TECH axcel`
106			`#elif defined CONFIG_CLK_LATDLL`
107			`#define CFG_CLK_TECH lattice`
108			`#elif defined CONFIG_CLK_PRO3PLL`
109			`#define CFG_CLK_TECH apa3`
110			`#elif defined CONFIG_CLK_CLKDLL`
111			`#define CFG_CLK_TECH virtex`
112			`#elif defined CONFIG_CLK_DCM`
113			`#define CFG_CLK_TECH CONFIG_SYN_TECH`
114			`#elif defined CONFIG_CLK_LIB18T`
115			`#define CFG_CLK_TECH rhlib18t`
116			`#elif defined CONFIG_CLK_RHUMC`
117			`#define CFG_CLK_TECH rhumc`
118			`#else`
119			`#define CFG_CLK_TECH inferred`
120			`#endif`
121
122			`#ifndef CONFIG_CLK_MUL`
123			`#define CONFIG_CLK_MUL 2`
124			`#endif`
125
126			`#ifndef CONFIG_CLK_DIV`
127			`#define CONFIG_CLK_DIV 2`
128			`#endif`
129
130			`#ifndef CONFIG_OCLK_DIV`
131			`#define CONFIG_OCLK_DIV 2`
132			`#endif`
133
134			`#ifndef CONFIG_PCI_CLKDLL`
135			`#define CONFIG_PCI_CLKDLL 0`
136			`#endif`
137
138			`#ifndef CONFIG_PCI_SYSCLK`
139			`#define CONFIG_PCI_SYSCLK 0`
140			`#endif`
141
142			`#ifndef CONFIG_CLK_NOFB`
143			`#define CONFIG_CLK_NOFB 0`
144			`#endif`
145			`#ifndef CONFIG_LEON3`
146			`#define CONFIG_LEON3 0`
147			`#endif`
148
149			`#ifndef CONFIG_PROC_NUM`
150			`#define CONFIG_PROC_NUM 1`
151			`#endif`
152
153			`#ifndef CONFIG_IU_NWINDOWS`
154			`#define CONFIG_IU_NWINDOWS 8`
155			`#endif`
156
157			`#ifndef CONFIG_IU_RSTADDR`
158			`#define CONFIG_IU_RSTADDR 8`
159			`#endif`
160
161			`#ifndef CONFIG_IU_LDELAY`
162			`#define CONFIG_IU_LDELAY 1`
163			`#endif`
164
165			`#ifndef CONFIG_IU_WATCHPOINTS`
166			`#define CONFIG_IU_WATCHPOINTS 0`
167			`#endif`
168
169			`#ifdef CONFIG_IU_V8MULDIV`
170			`#ifdef CONFIG_IU_MUL_LATENCY_4`
171			`#define CFG_IU_V8 1`
172			`#else`
173			`#define CFG_IU_V8 2`
174			`#endif`
175			`#else`
176			`#define CFG_IU_V8 0`
177			`#endif`
178			`#ifndef CONFIG_PWD`
179			`#define CONFIG_PWD 0`
180			`#endif`
181
182			`#ifndef CONFIG_IU_MUL_MAC`
183			`#define CONFIG_IU_MUL_MAC 0`
184			`#endif`
185
186			`#ifndef CONFIG_IU_SVT`
187			`#define CONFIG_IU_SVT 0`
188			`#endif`
189
190			`#if defined CONFIG_FPU_GRFPC1`
191			`#define CONFIG_FPU_GRFPC 1`
192			`#elif defined CONFIG_FPU_GRFPC2`
193			`#define CONFIG_FPU_GRFPC 2`
194			`#else`
195			`#define CONFIG_FPU_GRFPC 0`
196			`#endif`
197
198			`#if defined CONFIG_FPU_GRFPU_INFMUL`
199			`#define CONFIG_FPU_GRFPU_MUL 0`
200			`#elif defined CONFIG_FPU_GRFPU_DWMUL`
201			`#define CONFIG_FPU_GRFPU_MUL 1`
202			`#elif defined CONFIG_FPU_GRFPU_MODGEN`
203			`#define CONFIG_FPU_GRFPU_MUL 2`
204			`#else`
205			`#define CONFIG_FPU_GRFPU_MUL 0`
206			`#endif`
207
208			`#if defined CONFIG_FPU_GRFPU_SH`
209			`#define CONFIG_FPU_GRFPU_SHARED 1`
210			`#else`
211			`#define CONFIG_FPU_GRFPU_SHARED 0`
212			`#endif`
213
214			`#if defined CONFIG_FPU_GRFPU`
215			`#define CONFIG_FPU (1+CONFIG_FPU_GRFPU_MUL)`
216			`#elif defined CONFIG_FPU_MEIKO`
217			`#define CONFIG_FPU 15`
218			`#elif defined CONFIG_FPU_GRFPULITE`
219			`#define CONFIG_FPU (8+CONFIG_FPU_GRFPC)`
220			`#else`
221			`#define CONFIG_FPU 0`
222			`#endif`
223
224			`#ifndef CONFIG_FPU_NETLIST`
225			`#define CONFIG_FPU_NETLIST 0`
226			`#endif`
227
228			`#ifndef CONFIG_ICACHE_ENABLE`
229			`#define CONFIG_ICACHE_ENABLE 0`
230			`#endif`
231
232			`#if defined CONFIG_ICACHE_ASSO1`
233			`#define CFG_IU_ISETS 1`
234			`#elif defined CONFIG_ICACHE_ASSO2`
235			`#define CFG_IU_ISETS 2`
236			`#elif defined CONFIG_ICACHE_ASSO3`
237			`#define CFG_IU_ISETS 3`
238			`#elif defined CONFIG_ICACHE_ASSO4`
239			`#define CFG_IU_ISETS 4`
240			`#else`
241			`#define CFG_IU_ISETS 1`
242			`#endif`
243
244			`#if defined CONFIG_ICACHE_SZ1`
245			`#define CFG_ICACHE_SZ 1`
246			`#elif defined CONFIG_ICACHE_SZ2`
247			`#define CFG_ICACHE_SZ 2`
248			`#elif defined CONFIG_ICACHE_SZ4`
249			`#define CFG_ICACHE_SZ 4`
250			`#elif defined CONFIG_ICACHE_SZ8`
251			`#define CFG_ICACHE_SZ 8`
252			`#elif defined CONFIG_ICACHE_SZ16`
253			`#define CFG_ICACHE_SZ 16`
254			`#elif defined CONFIG_ICACHE_SZ32`
255			`#define CFG_ICACHE_SZ 32`
256			`#elif defined CONFIG_ICACHE_SZ64`
257			`#define CFG_ICACHE_SZ 64`
258			`#elif defined CONFIG_ICACHE_SZ128`
259			`#define CFG_ICACHE_SZ 128`
260			`#elif defined CONFIG_ICACHE_SZ256`
261			`#define CFG_ICACHE_SZ 256`
262			`#else`
263			`#define CFG_ICACHE_SZ 1`
264			`#endif`
265
266			`#ifdef CONFIG_ICACHE_LZ16`
267			`#define CFG_ILINE_SZ 4`
268			`#else`
269			`#define CFG_ILINE_SZ 8`
270			`#endif`
271
272			`#if defined CONFIG_ICACHE_ALGORND`
273			`#define CFG_ICACHE_ALGORND 2`
274			`#elif defined CONFIG_ICACHE_ALGOLRR`
275			`#define CFG_ICACHE_ALGORND 1`
276			`#else`
277			`#define CFG_ICACHE_ALGORND 0`
278			`#endif`
279
280			`#ifndef CONFIG_ICACHE_LOCK`
281			`#define CONFIG_ICACHE_LOCK 0`
282			`#endif`
283
284			`#ifndef CONFIG_ICACHE_LRAM`
285			`#define CONFIG_ICACHE_LRAM 0`
286			`#endif`
287
288			`#ifndef CONFIG_ICACHE_LRSTART`
289			`#define CONFIG_ICACHE_LRSTART 8E`
290			`#endif`
291
292			`#if defined CONFIG_ICACHE_LRAM_SZ2`
293			`#define CFG_ILRAM_SIZE 2`
294			`#elif defined CONFIG_ICACHE_LRAM_SZ4`
295			`#define CFG_ILRAM_SIZE 4`
296			`#elif defined CONFIG_ICACHE_LRAM_SZ8`
297			`#define CFG_ILRAM_SIZE 8`
298			`#elif defined CONFIG_ICACHE_LRAM_SZ16`
299			`#define CFG_ILRAM_SIZE 16`
300			`#elif defined CONFIG_ICACHE_LRAM_SZ32`
301			`#define CFG_ILRAM_SIZE 32`
302			`#elif defined CONFIG_ICACHE_LRAM_SZ64`
303			`#define CFG_ILRAM_SIZE 64`
304			`#elif defined CONFIG_ICACHE_LRAM_SZ128`
305			`#define CFG_ILRAM_SIZE 128`
306			`#elif defined CONFIG_ICACHE_LRAM_SZ256`
307			`#define CFG_ILRAM_SIZE 256`
308			`#else`
309			`#define CFG_ILRAM_SIZE 1`
310			`#endif`
311
312
313			`#ifndef CONFIG_DCACHE_ENABLE`
314			`#define CONFIG_DCACHE_ENABLE 0`
315			`#endif`
316
317			`#if defined CONFIG_DCACHE_ASSO1`
318			`#define CFG_IU_DSETS 1`
319			`#elif defined CONFIG_DCACHE_ASSO2`
320			`#define CFG_IU_DSETS 2`
321			`#elif defined CONFIG_DCACHE_ASSO3`
322			`#define CFG_IU_DSETS 3`
323			`#elif defined CONFIG_DCACHE_ASSO4`
324			`#define CFG_IU_DSETS 4`
325			`#else`
326			`#define CFG_IU_DSETS 1`
327			`#endif`
328
329			`#if defined CONFIG_DCACHE_SZ1`
330			`#define CFG_DCACHE_SZ 1`
331			`#elif defined CONFIG_DCACHE_SZ2`
332			`#define CFG_DCACHE_SZ 2`
333			`#elif defined CONFIG_DCACHE_SZ4`
334			`#define CFG_DCACHE_SZ 4`
335			`#elif defined CONFIG_DCACHE_SZ8`
336			`#define CFG_DCACHE_SZ 8`
337			`#elif defined CONFIG_DCACHE_SZ16`
338			`#define CFG_DCACHE_SZ 16`
339			`#elif defined CONFIG_DCACHE_SZ32`
340			`#define CFG_DCACHE_SZ 32`
341			`#elif defined CONFIG_DCACHE_SZ64`
342			`#define CFG_DCACHE_SZ 64`
343			`#elif defined CONFIG_DCACHE_SZ128`
344			`#define CFG_DCACHE_SZ 128`
345			`#elif defined CONFIG_DCACHE_SZ256`
346			`#define CFG_DCACHE_SZ 256`
347			`#else`
348			`#define CFG_DCACHE_SZ 1`
349			`#endif`
350
351			`#ifdef CONFIG_DCACHE_LZ16`
352			`#define CFG_DLINE_SZ 4`
353			`#else`
354			`#define CFG_DLINE_SZ 8`
355			`#endif`
356
357			`#if defined CONFIG_DCACHE_ALGORND`
358			`#define CFG_DCACHE_ALGORND 2`
359			`#elif defined CONFIG_DCACHE_ALGOLRR`
360			`#define CFG_DCACHE_ALGORND 1`
361			`#else`
362			`#define CFG_DCACHE_ALGORND 0`
363			`#endif`
364
365			`#ifndef CONFIG_DCACHE_LOCK`
366			`#define CONFIG_DCACHE_LOCK 0`
367			`#endif`
368
369			`#ifndef CONFIG_DCACHE_SNOOP`
370			`#define CONFIG_DCACHE_SNOOP 0`
371			`#endif`
372
373			`#ifndef CONFIG_DCACHE_SNOOP_FAST`
374			`#define CONFIG_DCACHE_SNOOP_FAST 0`
375			`#endif`
376
377			`#ifndef CONFIG_DCACHE_SNOOP_SEPTAG`
378			`#define CONFIG_DCACHE_SNOOP_SEPTAG 0`
379			`#endif`
380
381			`#ifndef CONFIG_CACHE_FIXED`
382			`#define CONFIG_CACHE_FIXED 0`
383			`#endif`
384
385			`#ifndef CONFIG_DCACHE_LRAM`
386			`#define CONFIG_DCACHE_LRAM 0`
387			`#endif`
388
389			`#ifndef CONFIG_DCACHE_LRSTART`
390			`#define CONFIG_DCACHE_LRSTART 8F`
391			`#endif`
392
393			`#if defined CONFIG_DCACHE_LRAM_SZ2`
394			`#define CFG_DLRAM_SIZE 2`
395			`#elif defined CONFIG_DCACHE_LRAM_SZ4`
396			`#define CFG_DLRAM_SIZE 4`
397			`#elif defined CONFIG_DCACHE_LRAM_SZ8`
398			`#define CFG_DLRAM_SIZE 8`
399			`#elif defined CONFIG_DCACHE_LRAM_SZ16`
400			`#define CFG_DLRAM_SIZE 16`
401			`#elif defined CONFIG_DCACHE_LRAM_SZ32`
402			`#define CFG_DLRAM_SIZE 32`
403			`#elif defined CONFIG_DCACHE_LRAM_SZ64`
404			`#define CFG_DLRAM_SIZE 64`
405			`#elif defined CONFIG_DCACHE_LRAM_SZ128`
406			`#define CFG_DLRAM_SIZE 128`
407			`#elif defined CONFIG_DCACHE_LRAM_SZ256`
408			`#define CFG_DLRAM_SIZE 256`
409			`#else`
410			`#define CFG_DLRAM_SIZE 1`
411			`#endif`
412
413
414			`#ifdef CONFIG_MMU_ENABLE`
415			`#define CONFIG_MMUEN 1`
416
417			`#ifdef CONFIG_MMU_SPLIT`
418			`#define CONFIG_TLB_TYPE 0`
419			`#endif`
420			`#ifdef CONFIG_MMU_COMBINED`
421			`#define CONFIG_TLB_TYPE 1`
422			`#endif`
423
424			`#ifdef CONFIG_MMU_REPARRAY`
425			`#define CONFIG_TLB_REP 0`
426			`#endif`
427			`#ifdef CONFIG_MMU_REPINCREMENT`
428			`#define CONFIG_TLB_REP 1`
429			`#endif`
430
431			`#ifdef CONFIG_MMU_I2`
432			`#define CONFIG_ITLBNUM 2`
433			`#endif`
434			`#ifdef CONFIG_MMU_I4`
435			`#define CONFIG_ITLBNUM 4`
436			`#endif`
437			`#ifdef CONFIG_MMU_I8`
438			`#define CONFIG_ITLBNUM 8`
439			`#endif`
440			`#ifdef CONFIG_MMU_I16`
441			`#define CONFIG_ITLBNUM 16`
442			`#endif`
443			`#ifdef CONFIG_MMU_I32`
444			`#define CONFIG_ITLBNUM 32`
445			`#endif`
446
447			`#define CONFIG_DTLBNUM 2`
448			`#ifdef CONFIG_MMU_D2`
449			`#undef CONFIG_DTLBNUM`
450			`#define CONFIG_DTLBNUM 2`
451			`#endif`
452			`#ifdef CONFIG_MMU_D4`
453			`#undef CONFIG_DTLBNUM`
454			`#define CONFIG_DTLBNUM 4`
455			`#endif`
456			`#ifdef CONFIG_MMU_D8`
457			`#undef CONFIG_DTLBNUM`
458			`#define CONFIG_DTLBNUM 8`
459			`#endif`
460			`#ifdef CONFIG_MMU_D16`
461			`#undef CONFIG_DTLBNUM`
462			`#define CONFIG_DTLBNUM 16`
463			`#endif`
464			`#ifdef CONFIG_MMU_D32`
465			`#undef CONFIG_DTLBNUM`
466			`#define CONFIG_DTLBNUM 32`
467			`#endif`
468			`#ifdef CONFIG_MMU_FASTWB`
469			`#define CFG_MMU_FASTWB 1`
470			`#else`
471			`#define CFG_MMU_FASTWB 0`
472			`#endif`
473
474			`#else`
475			`#define CONFIG_MMUEN 0`
476			`#define CONFIG_ITLBNUM 2`
477			`#define CONFIG_DTLBNUM 2`
478			`#define CONFIG_TLB_TYPE 1`
479			`#define CONFIG_TLB_REP 1`
480			`#define CFG_MMU_FASTWB 0`
481			`#endif`
482
483			`#ifndef CONFIG_DSU_ENABLE`
484			`#define CONFIG_DSU_ENABLE 0`
485			`#endif`
486
487			`#if defined CONFIG_DSU_ITRACESZ1`
488			`#define CFG_DSU_ITB 1`
489			`#elif CONFIG_DSU_ITRACESZ2`
490			`#define CFG_DSU_ITB 2`
491			`#elif CONFIG_DSU_ITRACESZ4`
492			`#define CFG_DSU_ITB 4`
493			`#elif CONFIG_DSU_ITRACESZ8`
494			`#define CFG_DSU_ITB 8`
495			`#elif CONFIG_DSU_ITRACESZ16`
496			`#define CFG_DSU_ITB 16`
497			`#else`
498			`#define CFG_DSU_ITB 0`
499			`#endif`
500
501			`#if defined CONFIG_DSU_ATRACESZ1`
502			`#define CFG_DSU_ATB 1`
503			`#elif CONFIG_DSU_ATRACESZ2`
504			`#define CFG_DSU_ATB 2`
505			`#elif CONFIG_DSU_ATRACESZ4`
506			`#define CFG_DSU_ATB 4`
507			`#elif CONFIG_DSU_ATRACESZ8`
508			`#define CFG_DSU_ATB 8`
509			`#elif CONFIG_DSU_ATRACESZ16`
510			`#define CFG_DSU_ATB 16`
511			`#else`
512			`#define CFG_DSU_ATB 0`
513			`#endif`
514
515			`#ifndef CONFIG_LEON3FT_EN`
516			`#define CONFIG_LEON3FT_EN 0`
517			`#endif`
518
519			`#if defined CONFIG_IUFT_PAR`
520			`#define CONFIG_IUFT_EN 1`
521			`#elif defined CONFIG_IUFT_DMR`
522			`#define CONFIG_IUFT_EN 2`
523			`#elif defined CONFIG_IUFT_BCH`
524			`#define CONFIG_IUFT_EN 3`
525			`#elif defined CONFIG_IUFT_TMR`
526			`#define CONFIG_IUFT_EN 4`
527			`#else`
528			`#define CONFIG_IUFT_EN 0`
529			`#endif`
530			`#ifndef CONFIG_RF_ERRINJ`
531			`#define CONFIG_RF_ERRINJ 0`
532			`#endif`
533
534			`#ifndef CONFIG_FPUFT_EN`
535			`#define CONFIG_FPUFT 0`
536			`#else`
537			`#ifdef CONFIG_FPU_GRFPU`
538			`#define CONFIG_FPUFT 2`
539			`#else`
540			`#define CONFIG_FPUFT 1`
541			`#endif`
542			`#endif`
543
544			`#ifndef CONFIG_CACHE_FT_EN`
545			`#define CONFIG_CACHE_FT_EN 0`
546			`#endif`
547			`#ifndef CONFIG_CACHE_ERRINJ`
548			`#define CONFIG_CACHE_ERRINJ 0`
549			`#endif`
550
551			`#ifndef CONFIG_LEON3_NETLIST`
552			`#define CONFIG_LEON3_NETLIST 0`
553			`#endif`
554
555			`#ifdef CONFIG_DEBUG_PC32`
556			`#define CFG_DEBUG_PC32 0`
557			`#else`
558			`#define CFG_DEBUG_PC32 2`
559			`#endif`
560			`#ifndef CONFIG_IU_DISAS`
561			`#define CONFIG_IU_DISAS 0`
562			`#endif`
563			`#ifndef CONFIG_IU_DISAS_NET`
564			`#define CONFIG_IU_DISAS_NET 0`
565			`#endif`
566
567
568			`#ifndef CONFIG_AHB_SPLIT`
569			`#define CONFIG_AHB_SPLIT 0`
570			`#endif`
571
572			`#ifndef CONFIG_AHB_RROBIN`
573			`#define CONFIG_AHB_RROBIN 0`
574			`#endif`
575
576			`#ifndef CONFIG_AHB_IOADDR`
577			`#define CONFIG_AHB_IOADDR FFF`
578			`#endif`
579
580			`#ifndef CONFIG_APB_HADDR`
581			`#define CONFIG_APB_HADDR 800`
582			`#endif`
583
584			`#ifndef CONFIG_AHB_MON`
585			`#define CONFIG_AHB_MON 0`
586			`#endif`
587
588			`#ifndef CONFIG_AHB_MONERR`
589			`#define CONFIG_AHB_MONERR 0`
590			`#endif`
591
592			`#ifndef CONFIG_AHB_MONWAR`
593			`#define CONFIG_AHB_MONWAR 0`
594			`#endif`
595
596			`#ifndef CONFIG_DSU_JTAG`
597			`#define CONFIG_DSU_JTAG 0`
598			`#endif`
599
600			`#ifndef CONFIG_MCTRL_LEON2`
601			`#define CONFIG_MCTRL_LEON2 0`
602			`#endif`
603
604			`#ifndef CONFIG_MCTRL_SDRAM`
605			`#define CONFIG_MCTRL_SDRAM 0`
606			`#endif`
607
608			`#ifndef CONFIG_MCTRL_SDRAM_SEPBUS`
609			`#define CONFIG_MCTRL_SDRAM_SEPBUS 0`
610			`#endif`
611
612			`#ifndef CONFIG_MCTRL_SDRAM_INVCLK`
613			`#define CONFIG_MCTRL_SDRAM_INVCLK 0`
614			`#endif`
615
616			`#ifndef CONFIG_MCTRL_SDRAM_BUS64`
617			`#define CONFIG_MCTRL_SDRAM_BUS64 0`
618			`#endif`
619
620			`#ifndef CONFIG_MCTRL_8BIT`
621			`#define CONFIG_MCTRL_8BIT 0`
622			`#endif`
623
624			`#ifndef CONFIG_MCTRL_16BIT`
625			`#define CONFIG_MCTRL_16BIT 0`
626			`#endif`
627
628			`#ifndef CONFIG_MCTRL_5CS`
629			`#define CONFIG_MCTRL_5CS 0`
630			`#endif`
631
632			`#ifndef CONFIG_MCTRL_EDAC`
633			`#define CONFIG_MCTRL_EDAC 0`
634			`#endif`
635
636			`#ifndef CONFIG_MCTRL_PAGE`
637			`#define CONFIG_MCTRL_PAGE 0`
638			`#endif`
639
640			`#ifndef CONFIG_MCTRL_PROGPAGE`
641			`#define CONFIG_MCTRL_PROGPAGE 0`
642			`#endif`
643
644			`#ifndef CONFIG_AHBROM_ENABLE`
645			`#define CONFIG_AHBROM_ENABLE 0`
646			`#endif`
647
648			`#ifndef CONFIG_AHBROM_START`
649			`#define CONFIG_AHBROM_START 000`
650			`#endif`
651
652			`#ifndef CONFIG_AHBROM_PIPE`
653			`#define CONFIG_AHBROM_PIPE 0`
654			`#endif`
655
656			`#if (CONFIG_AHBROM_START == 0) && (CONFIG_AHBROM_ENABLE == 1)`
657			`#define CONFIG_ROM_START 100`
658			`#else`
659			`#define CONFIG_ROM_START 000`
660			`#endif`
661
662
663			`#ifndef CONFIG_AHBRAM_ENABLE`
664			`#define CONFIG_AHBRAM_ENABLE 0`
665			`#endif`
666
667			`#ifndef CONFIG_AHBRAM_START`
668			`#define CONFIG_AHBRAM_START A00`
669			`#endif`
670
671			`#if defined CONFIG_AHBRAM_SZ1`
672			`#define CFG_AHBRAMSZ 1`
673			`#elif CONFIG_AHBRAM_SZ2`
674			`#define CFG_AHBRAMSZ 2`
675			`#elif CONFIG_AHBRAM_SZ4`
676			`#define CFG_AHBRAMSZ 4`
677			`#elif CONFIG_AHBRAM_SZ8`
678			`#define CFG_AHBRAMSZ 8`
679			`#elif CONFIG_AHBRAM_SZ16`
680			`#define CFG_AHBRAMSZ 16`
681			`#elif CONFIG_AHBRAM_SZ32`
682			`#define CFG_AHBRAMSZ 32`
683			`#elif CONFIG_AHBRAM_SZ64`
684			`#define CFG_AHBRAMSZ 64`
685			`#else`
686			`#define CFG_AHBRAMSZ 1`
687			`#endif`
688
689			`#ifndef CONFIG_UART1_ENABLE`
690			`#define CONFIG_UART1_ENABLE 0`
691			`#endif`
692
693			`#if defined CONFIG_UA1_FIFO1`
694			`#define CFG_UA1_FIFO 1`
695			`#elif defined CONFIG_UA1_FIFO2`
696			`#define CFG_UA1_FIFO 2`
697			`#elif defined CONFIG_UA1_FIFO4`
698			`#define CFG_UA1_FIFO 4`
699			`#elif defined CONFIG_UA1_FIFO8`
700			`#define CFG_UA1_FIFO 8`
701			`#elif defined CONFIG_UA1_FIFO16`
702			`#define CFG_UA1_FIFO 16`
703			`#elif defined CONFIG_UA1_FIFO32`
704			`#define CFG_UA1_FIFO 32`
705			`#else`
706			`#define CFG_UA1_FIFO 1`
707			`#endif`
708
709			`#ifndef CONFIG_IRQ3_ENABLE`
710			`#define CONFIG_IRQ3_ENABLE 0`
711			`#endif`
712			`#ifndef CONFIG_GPT_ENABLE`
713			`#define CONFIG_GPT_ENABLE 0`
714			`#endif`
715
716			`#ifndef CONFIG_GPT_NTIM`
717			`#define CONFIG_GPT_NTIM 1`
718			`#endif`
719
720			`#ifndef CONFIG_GPT_SW`
721			`#define CONFIG_GPT_SW 8`
722			`#endif`
723
724			`#ifndef CONFIG_GPT_TW`
725			`#define CONFIG_GPT_TW 8`
726			`#endif`
727
728			`#ifndef CONFIG_GPT_IRQ`
729			`#define CONFIG_GPT_IRQ 8`
730			`#endif`
731
732			`#ifndef CONFIG_GPT_SEPIRQ`
733			`#define CONFIG_GPT_SEPIRQ 0`
734			`#endif`
735			`#ifndef CONFIG_GPT_ENABLE`
736			`#define CONFIG_GPT_ENABLE 0`
737			`#endif`
738
739			`#ifndef CONFIG_GPT_NTIM`
740			`#define CONFIG_GPT_NTIM 1`
741			`#endif`
742
743			`#ifndef CONFIG_GPT_SW`
744			`#define CONFIG_GPT_SW 8`
745			`#endif`
746
747			`#ifndef CONFIG_GPT_TW`
748			`#define CONFIG_GPT_TW 8`
749			`#endif`
750
751			`#ifndef CONFIG_GPT_IRQ`
752			`#define CONFIG_GPT_IRQ 8`
753			`#endif`
754
755			`#ifndef CONFIG_GPT_SEPIRQ`
756			`#define CONFIG_GPT_SEPIRQ 0`
757			`#endif`
758
759			`#ifndef CONFIG_GPT_WDOGEN`
760			`#define CONFIG_GPT_WDOGEN 0`
761			`#endif`
762
763			`#ifndef CONFIG_GPT_WDOG`
764			`#define CONFIG_GPT_WDOG 0`
765			`#endif`
766
767			`#ifndef CONFIG_GRGPIO_ENABLE`
768			`#define CONFIG_GRGPIO_ENABLE 0`
769			`#endif`
770			`#ifndef CONFIG_GRGPIO_IMASK`
771			`#define CONFIG_GRGPIO_IMASK 0000`
772			`#endif`
773			`#ifndef CONFIG_GRGPIO_WIDTH`
774			`#define CONFIG_GRGPIO_WIDTH 1`
775			`#endif`
776
777			`#ifndef CONFIG_VGA_ENABLE`
778			`#define CONFIG_VGA_ENABLE 0`
779			`#endif`
780			`#ifndef CONFIG_SVGA_ENABLE`
781			`#define CONFIG_SVGA_ENABLE 0`
782			`#endif`
783			`#ifndef CONFIG_KBD_ENABLE`
784			`#define CONFIG_KBD_ENABLE 0`
785			`#endif`
786
787
788			`#ifndef CONFIG_DEBUG_UART`
789			`#define CONFIG_DEBUG_UART 0`
790			`#endif`