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# Synplicity, Inc. constraint file

# /home/jiri/ibm/vhdl/grlib/designs/leon3-digilent-xc3s1600e/default.sdc

# Written on Thu Jan 25 01:39:56 2007

# by Synplify Pro, Synplify Pro 8.8 Scope Editor

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# Collections

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# Clocks

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define_clock            {etx_clk} -name {etx_clk}  -freq 25 -clockgroup phy_rx_clkgroup -route 10

define_clock            {erx_clk} -name {erx_clk}  -freq 25 -clockgroup phy_tx_clkgroup -route 10

define_clock            {ddr_clk_fb} -name {ddr_clk_fb}  -freq 125 -clockgroup ddr_read_group

define_clock            {leon3mp|ddrsp0.ddrc.ddr_phy0.ddr_phy0.clk} -name {leon3mp|ddrsp0.ddrc.ddr_phy0.ddr_phy0.clk}  -freq 100 -clockgroup ddr_clkgroup -route 1

define_clock            {clk_50mhz} -name {clk_50mhz}  -freq 55 -clockgroup default_clkgroup_0 -route 2

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# Clock to Clock

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define_clock_delay           -rise {leon3mp|ddrsp0.ddrc.ddr_phy0.ddr_phy0.clk} -rise {clkm} -false

define_clock_delay           -rise {clk_50mhz} -rise {leon3mp|ddrsp0.ddrc.ddr_phy0.ddr_phy0.clk} -false

define_clock_delay           -rise {leon3mp|clkgen0.xc3s.v.clk0B_derived_clock} -rise {leon3mp|ddrsp0.ddrc.ddr_phy0.ddr_phy0.clk} -false

define_clock_delay           -rise {leon3mp|clkgen0.xc3s.v.clk0B_derived_clock} -rise {leon3mp|clkgen0.xc3s.v.clk_x_derived_clock} -false

define_clock_delay           -rise {leon3mp|clkgen0.xc3s.v.clk0B_derived_clock} -rise {ddrspa|ddr_phy0.ddr_phy0.xc3se.ddr_phy0.clk_270ro_derived_clock} -false

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# Inputs/Outputs

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define_output_delay -disable     -default  10.00 -improve 0.00 -route 0.00 -ref {clk:r}

define_input_delay -disable      -default  10.00 -improve 0.00 -route 0.00 -ref {clk:r}

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# Registers

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# Multicycle Path

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# False Path

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# Path Delay

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# Attributes

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define_global_attribute          syn_useioff {1}

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# I/O standards

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# Compile Points

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# Other Constraints

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