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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [designs/] [leon3-digilent-xc3s1600e/] [system.ucf] - Blame information for rev 2

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1 2 dimamali 
##
2 
###########################################################################
3 
##  Copyright(C) 2006 by Xilinx, Inc. All rights reserved.               ##
4 
##                                                                       ##
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##  You may copy and modify these files for your own internal use solely ##
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##  with Xilinx programmable logic devices and  Xilinx EDK system or     ##
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##  create IP modules solely for Xilinx programmable logic devices and   ##
8 
##  Xilinx EDK system. No rights are granted to distribute any files     ##
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##  unless they are distributed in Xilinx programmable logic devices.    ##
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##                                                                       ##
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##  Source code is provided "as-is", with no obligation on the part of   ##
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##  Xilinx to provide support.                                           ##
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##                                                                       ##
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###########################################################################
15 
#
16 
##########################################################################
17 
# Target Board: Xilinx Spartan-3E 1600E Board Rev A                     ##
18 
# Family: spartan3e                                                     ##
19 
# Device: XC3S1600e                                                     ##
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# Package: FG320                                                        ##
21 
# Speed Grade: -4                                                       ##
22 
##########################################################################
23 
#
24 
 
25 
Net sys_clk_pin LOC=B8;
26 
Net sys_clk_pin IOSTANDARD = LVCMOS33;
27 
Net sys_rst_pin LOC=K17;
28 
Net sys_rst_pin IOSTANDARD = LVCMOS33;
29 
Net sys_rst_pin PULLDOWN;
30 
 
31 
## System level constraints
32 
Net sys_clk_pin TNM_NET = sys_clk_pin;
33 
TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 14600 ps;
34 
Net sys_rst_pin TIG;
35 
 
36 
NET "dlmb_port_BRAM_Clk" TNM_NET = "sys_clk_s";
37 
NET "ddr_dev_clk_s" TNM_NET = "Device_Clk";
38 
 
39 
NET "fpga_0_DDR_CLK_FB" TNM_NET = "fpga_0_DDR_CLK_FB";
40 
TIMESPEC "TS_fpga_0_DDR_CLK_FB" = PERIOD "fpga_0_DDR_CLK_FB" 7.2 ns HIGH 50 %;
41 
 
42 
 
43 
NET "DBG_CLK_s" TNM_NET = "DBG_CLK_s";
44 
TIMESPEC "TS_DBG_CLK_s" = PERIOD "DBG_CLK_s" 30 MHz HIGH 50 %;
45 
 
46 
TIMESPEC "TS_OPB_TO_DDR" = FROM "sys_clk_s" TO "Device_Clk"  TIG;
47 
TIMESPEC "TS_DDR_TO_OPB" = FROM "Device_Clk" TO "sys_clk_s"  TIG;
48 
 
49 
 
50 
## IO Devices constraints
51 
 
52 
#### Module RS232_DTE constraints
53 
 
54 
Net fpga_0_RS232_DTE_RX_pin LOC=U8;
55 
Net fpga_0_RS232_DTE_RX_pin IOSTANDARD = LVCMOS33;
56 
Net fpga_0_RS232_DTE_TX_pin LOC=M13;
57 
Net fpga_0_RS232_DTE_TX_pin IOSTANDARD = LVCMOS33;
58 
 
59 
#### Module FLASH_16Mx8 constraints
60 
 
61 
Net fpga_0_FLASH_16Mx8_Mem_A_pin<31> LOC=h17;
62 
Net fpga_0_FLASH_16Mx8_Mem_A_pin<31> IOSTANDARD = LVCMOS33;
63 
Net fpga_0_FLASH_16Mx8_Mem_A_pin<30> LOC=j13;
64 
Net fpga_0_FLASH_16Mx8_Mem_A_pin<30> IOSTANDARD = LVCMOS33;
65 
Net fpga_0_FLASH_16Mx8_Mem_A_pin<29> LOC=j12;
66 
Net fpga_0_FLASH_16Mx8_Mem_A_pin<29> IOSTANDARD = LVCMOS33;
67 
Net fpga_0_FLASH_16Mx8_Mem_A_pin<28> LOC=j14;
68 
Net fpga_0_FLASH_16Mx8_Mem_A_pin<28> IOSTANDARD = LVCMOS33;
69 
Net fpga_0_FLASH_16Mx8_Mem_A_pin<27> LOC=j15;
70 
Net fpga_0_FLASH_16Mx8_Mem_A_pin<27> IOSTANDARD = LVCMOS33;
71 
Net fpga_0_FLASH_16Mx8_Mem_A_pin<26> LOC=j16;
72 
Net fpga_0_FLASH_16Mx8_Mem_A_pin<26> IOSTANDARD = LVCMOS33;
73 
Net fpga_0_FLASH_16Mx8_Mem_A_pin<25> LOC=j17;
74 
Net fpga_0_FLASH_16Mx8_Mem_A_pin<25> IOSTANDARD = LVCMOS33;
75 
Net fpga_0_FLASH_16Mx8_Mem_A_pin<24> LOC=k14;
76 
Net fpga_0_FLASH_16Mx8_Mem_A_pin<24> IOSTANDARD = LVCMOS33;
77 
Net fpga_0_FLASH_16Mx8_Mem_A_pin<23> LOC=k15;
78 
Net fpga_0_FLASH_16Mx8_Mem_A_pin<23> IOSTANDARD = LVCMOS33;
79 
Net fpga_0_FLASH_16Mx8_Mem_A_pin<22> LOC=k12;
80 
Net fpga_0_FLASH_16Mx8_Mem_A_pin<22> IOSTANDARD = LVCMOS33;
81 
Net fpga_0_FLASH_16Mx8_Mem_A_pin<21> LOC=k13;
82 
Net fpga_0_FLASH_16Mx8_Mem_A_pin<21> IOSTANDARD = LVCMOS33;
83 
Net fpga_0_FLASH_16Mx8_Mem_A_pin<20> LOC=l15;
84 
Net fpga_0_FLASH_16Mx8_Mem_A_pin<20> IOSTANDARD = LVCMOS33;
85 
Net fpga_0_FLASH_16Mx8_Mem_A_pin<19> LOC=l16;
86 
Net fpga_0_FLASH_16Mx8_Mem_A_pin<19> IOSTANDARD = LVCMOS33;
87 
Net fpga_0_FLASH_16Mx8_Mem_A_pin<18> LOC=t18;
88 
Net fpga_0_FLASH_16Mx8_Mem_A_pin<18> IOSTANDARD = LVCMOS33;
89 
Net fpga_0_FLASH_16Mx8_Mem_A_pin<17> LOC=r18;
90 
Net fpga_0_FLASH_16Mx8_Mem_A_pin<17> IOSTANDARD = LVCMOS33;
91 
Net fpga_0_FLASH_16Mx8_Mem_A_pin<16> LOC=t17;
92 
Net fpga_0_FLASH_16Mx8_Mem_A_pin<16> IOSTANDARD = LVCMOS33;
93 
Net fpga_0_FLASH_16Mx8_Mem_A_pin<15> LOC=u18;
94 
Net fpga_0_FLASH_16Mx8_Mem_A_pin<15> IOSTANDARD = LVCMOS33;
95 
Net fpga_0_FLASH_16Mx8_Mem_A_pin<14> LOC=t16;
96 
Net fpga_0_FLASH_16Mx8_Mem_A_pin<14> IOSTANDARD = LVCMOS33;
97 
Net fpga_0_FLASH_16Mx8_Mem_A_pin<13> LOC=u15;
98 
Net fpga_0_FLASH_16Mx8_Mem_A_pin<13> IOSTANDARD = LVCMOS33;
99 
Net fpga_0_FLASH_16Mx8_Mem_A_pin<12> LOC=v15;
100 
Net fpga_0_FLASH_16Mx8_Mem_A_pin<12> IOSTANDARD = LVCMOS33;
101 
Net fpga_0_FLASH_16Mx8_Mem_A_pin<11> LOC=t12;
102 
Net fpga_0_FLASH_16Mx8_Mem_A_pin<11> IOSTANDARD = LVCMOS33;
103 
Net fpga_0_FLASH_16Mx8_Mem_A_pin<10> LOC=v13;
104 
Net fpga_0_FLASH_16Mx8_Mem_A_pin<10> IOSTANDARD = LVCMOS33;
105 
Net fpga_0_FLASH_16Mx8_Mem_A_pin<9> LOC=v12;
106 
Net fpga_0_FLASH_16Mx8_Mem_A_pin<9> IOSTANDARD = LVCMOS33;
107 
Net fpga_0_FLASH_16Mx8_Mem_A_pin<8> LOC=n11;
108 
Net fpga_0_FLASH_16Mx8_Mem_A_pin<8> IOSTANDARD = LVCMOS33;
109 
Net fpga_0_FLASH_16Mx8_Mem_DQ_pin<7> LOC=n10;
110 
Net fpga_0_FLASH_16Mx8_Mem_DQ_pin<7> IOSTANDARD = LVCMOS33;
111 
Net fpga_0_FLASH_16Mx8_Mem_DQ_pin<6> LOC=p10;
112 
Net fpga_0_FLASH_16Mx8_Mem_DQ_pin<6> IOSTANDARD = LVCMOS33;
113 
Net fpga_0_FLASH_16Mx8_Mem_DQ_pin<5> LOC=r10;
114 
Net fpga_0_FLASH_16Mx8_Mem_DQ_pin<5> IOSTANDARD = LVCMOS33;
115 
Net fpga_0_FLASH_16Mx8_Mem_DQ_pin<4> LOC=v9;
116 
Net fpga_0_FLASH_16Mx8_Mem_DQ_pin<4> IOSTANDARD = LVCMOS33;
117 
Net fpga_0_FLASH_16Mx8_Mem_DQ_pin<3> LOC=u9;
118 
Net fpga_0_FLASH_16Mx8_Mem_DQ_pin<3> IOSTANDARD = LVCMOS33;
119 
Net fpga_0_FLASH_16Mx8_Mem_DQ_pin<2> LOC=r9;
120 
Net fpga_0_FLASH_16Mx8_Mem_DQ_pin<2> IOSTANDARD = LVCMOS33;
121 
Net fpga_0_FLASH_16Mx8_Mem_DQ_pin<1> LOC=m9;
122 
Net fpga_0_FLASH_16Mx8_Mem_DQ_pin<1> IOSTANDARD = LVCMOS33;
123 
Net fpga_0_FLASH_16Mx8_Mem_DQ_pin<0> LOC=n9;
124 
Net fpga_0_FLASH_16Mx8_Mem_DQ_pin<0> IOSTANDARD = LVCMOS33;
125 
Net fpga_0_FLASH_16Mx8_Mem_OEN_pin LOC=c18;
126 
Net fpga_0_FLASH_16Mx8_Mem_OEN_pin IOSTANDARD = LVCMOS33;
127 
Net fpga_0_FLASH_16Mx8_Mem_WEN_pin LOC=d17;
128 
Net fpga_0_FLASH_16Mx8_Mem_WEN_pin IOSTANDARD = LVCMOS33;
129 
Net fpga_0_FLASH_16Mx8_Mem_CEN_pin<0> LOC=d16;
130 
Net fpga_0_FLASH_16Mx8_Mem_CEN_pin<0> IOSTANDARD = LVCMOS33;
131 
Net fpga_0_FLASH_16Mx8_emc_ben_gnd_pin LOC=c17;
132 
Net fpga_0_FLASH_16Mx8_emc_ben_gnd_pin IOSTANDARD = LVCMOS33;
133 
 
134 
#### Module DDR_SDRAM_32Mx16 constraints
135 
 
136 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_Clk_pin LOC=J5;
137 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_Clk_pin IOSTANDARD = SSTL2_I;
138 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_Clkn_pin LOC=J4;
139 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_Clkn_pin IOSTANDARD = SSTL2_I;
140 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<0> LOC=P2;
141 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<0> IOSTANDARD = SSTL2_I;
142 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<1> LOC=N5;
143 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<1> IOSTANDARD = SSTL2_I;
144 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<2> LOC=T2;
145 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<2> IOSTANDARD = SSTL2_I;
146 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<3> LOC=N4;
147 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<3> IOSTANDARD = SSTL2_I;
148 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<4> LOC=H2;
149 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<4> IOSTANDARD = SSTL2_I;
150 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<5> LOC=H1;
151 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<5> IOSTANDARD = SSTL2_I;
152 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<6> LOC=H3;
153 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<6> IOSTANDARD = SSTL2_I;
154 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<7> LOC=H4;
155 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<7> IOSTANDARD = SSTL2_I;
156 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<8> LOC=E4;
157 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<8> IOSTANDARD = SSTL2_I;
158 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<9> LOC=P1;
159 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<9> IOSTANDARD = SSTL2_I;
160 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<10> LOC=R2;
161 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<10> IOSTANDARD = SSTL2_I;
162 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<11> LOC=R3;
163 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<11> IOSTANDARD = SSTL2_I;
164 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<12> LOC=T1;
165 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<12> IOSTANDARD = SSTL2_I;
166 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_BankAddr_pin<0> LOC=K6;
167 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_BankAddr_pin<0> IOSTANDARD = SSTL2_I;
168 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_BankAddr_pin<1> LOC=K5;
169 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_BankAddr_pin<1> IOSTANDARD = SSTL2_I;
170 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_CASn_pin LOC=C2;
171 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_CASn_pin IOSTANDARD = SSTL2_I;
172 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_CKE_pin LOC=K3;
173 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_CKE_pin IOSTANDARD = SSTL2_I;
174 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_CSn_pin LOC=K4;
175 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_CSn_pin IOSTANDARD = SSTL2_I;
176 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_RASn_pin LOC=C1;
177 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_RASn_pin IOSTANDARD = SSTL2_I;
178 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_WEn_pin LOC=D1;
179 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_WEn_pin IOSTANDARD = SSTL2_I;
180 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DM_pin<0> LOC=J1;
181 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DM_pin<0> IOSTANDARD = SSTL2_I;
182 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DM_pin<1> LOC=J2;
183 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DM_pin<1> IOSTANDARD = SSTL2_I;
184 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQS_pin<0> LOC=G3;
185 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQS_pin<0> IOSTANDARD = SSTL2_I;
186 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQS_pin<1> LOC=L6;
187 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQS_pin<1> IOSTANDARD = SSTL2_I;
188 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQS_pin<1> PULLUP;
189 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<0> LOC=H5;
190 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<0> IOSTANDARD = SSTL2_I;
191 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<0> PULLUP;
192 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<1> LOC=H6;
193 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<1> IOSTANDARD = SSTL2_I;
194 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<1> PULLUP;
195 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<2> LOC=G5;
196 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<2> IOSTANDARD = SSTL2_I;
197 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<2> PULLUP;
198 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<3> LOC=G6;
199 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<3> IOSTANDARD = SSTL2_I;
200 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<3> PULLUP;
201 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<4> LOC=F2;
202 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<4> IOSTANDARD = SSTL2_I;
203 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<4> PULLUP;
204 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<5> LOC=F1;
205 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<5> IOSTANDARD = SSTL2_I;
206 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<5> PULLUP;
207 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<6> LOC=E1;
208 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<6> IOSTANDARD = SSTL2_I;
209 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<6> PULLUP;
210 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<7> LOC=E2;
211 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<7> IOSTANDARD = SSTL2_I;
212 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<7> PULLUP;
213 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<8> LOC=M6;
214 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<8> IOSTANDARD = SSTL2_I;
215 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<8> PULLUP;
216 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<9> LOC=M5;
217 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<9> IOSTANDARD = SSTL2_I;
218 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<9> PULLUP;
219 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<10> LOC=M4;
220 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<10> IOSTANDARD = SSTL2_I;
221 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<10> PULLUP;
222 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<11> LOC=M3;
223 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<11> IOSTANDARD = SSTL2_I;
224 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<11> PULLUP;
225 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<12> LOC=L4;
226 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<12> IOSTANDARD = SSTL2_I;
227 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<12> PULLUP;
228 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<13> LOC=L3;
229 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<13> IOSTANDARD = SSTL2_I;
230 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<13> PULLUP;
231 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<14> LOC=L1;
232 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<14> IOSTANDARD = SSTL2_I;
233 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<14> PULLUP;
234 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<15> LOC=L2;
235 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<15> IOSTANDARD = SSTL2_I;
236 
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<15> PULLUP;
237 
 
238 
#### Module Ethernet_MAC constraints
239 
 
240 
Net fpga_0_Ethernet_MAC_PHY_tx_clk_pin LOC=T7;
241 
Net fpga_0_Ethernet_MAC_PHY_tx_clk_pin IOSTANDARD = LVCMOS33;
242 
Net fpga_0_Ethernet_MAC_PHY_rx_clk_pin LOC=V3;
243 
Net fpga_0_Ethernet_MAC_PHY_rx_clk_pin IOSTANDARD = LVCMOS33;
244 
Net fpga_0_Ethernet_MAC_PHY_crs_pin LOC=U13;
245 
Net fpga_0_Ethernet_MAC_PHY_crs_pin IOSTANDARD = LVCMOS33;
246 
Net fpga_0_Ethernet_MAC_PHY_dv_pin LOC=V2;
247 
Net fpga_0_Ethernet_MAC_PHY_dv_pin IOSTANDARD = LVCMOS33;
248 
Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<0> LOC=V8;
249 
Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<0> IOSTANDARD = LVCMOS33;
250 
Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<1> LOC=T11;
251 
Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<1> IOSTANDARD = LVCMOS33;
252 
Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<2> LOC=U11;
253 
Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<2> IOSTANDARD = LVCMOS33;
254 
Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<3> LOC=V14;
255 
Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<3> IOSTANDARD = LVCMOS33;
256 
Net fpga_0_Ethernet_MAC_PHY_col_pin LOC=U6;
257 
Net fpga_0_Ethernet_MAC_PHY_col_pin IOSTANDARD = LVCMOS33;
258 
Net fpga_0_Ethernet_MAC_PHY_rx_er_pin LOC=U14;
259 
Net fpga_0_Ethernet_MAC_PHY_rx_er_pin IOSTANDARD = LVCMOS33;
260 
Net fpga_0_Ethernet_MAC_PHY_tx_en_pin LOC=P16;
261 
Net fpga_0_Ethernet_MAC_PHY_tx_en_pin IOSTANDARD = LVCMOS33;
262 
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<0> LOC=R11;
263 
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<0> IOSTANDARD = LVCMOS33;
264 
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<1> LOC=T15;
265 
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<1> IOSTANDARD = LVCMOS33;
266 
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<2> LOC=R5;
267 
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<2> IOSTANDARD = LVCMOS33;
268 
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<3> LOC=T5;
269 
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<3> IOSTANDARD = LVCMOS33;
270 
Net fpga_0_Ethernet_MAC_PHY_Mii_clk_pin LOC=P9;
271 
Net fpga_0_Ethernet_MAC_PHY_Mii_clk_pin IOSTANDARD = LVCMOS33;
272 
Net fpga_0_Ethernet_MAC_PHY_Mii_data_pin LOC=U5;
273 
Net fpga_0_Ethernet_MAC_PHY_Mii_data_pin IOSTANDARD = LVCMOS33;
274 
 
275 
Net fpga_0_DDR_CLK_FB LOC=B9;
276 
Net fpga_0_DDR_CLK_FB IOSTANDARD = LVCMOS33;
277 
 
278 
Net SPI_ROM_CS_pin LOC=U3 | PULLUP;  ## This is to force the SPI ROM to not be selected(drive high)
279 
Net SPI_ROM_CS_pin IOSTANDARD = LVCMOS33;
280 
 

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