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# Synplicity, Inc. constraint file

# /home/jiri/ibm/vhdl/grlib/designs/leon3-avnet-eval-xc4vlx25/default.sdc

# Written on Sun Oct  1 16:16:08 2006

# by Synplify Pro, Synplify Pro 8.6.1 Scope Editor

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# Collections

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# Clocks

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#define_clock            -name {clk}  -freq 100.000 -route 1.0 -clockgroup default_clkgroup

define_clock            -name {etx_clk}  -freq 25.000 -clockgroup phy_rx_clkgroup -route 10.000

define_clock            -name {erx_clk}  -freq 25.000 -clockgroup phy_tx_clkgroup -route 10.000

define_clock            -name {ddr_clk_fb} -freq 125.000 -clockgroup ddr_read_group

define_clock            -name {clkvga} -freq 65.000 -clockgroup clkvga_group -route 4.0

define_clock            -name {leon3mp|ddrsp0.ddr0.ddr_phy0.clk} -freq 100.000 -route 1.0 -clockgroup ddr_clkgroup

define_clock            -name {leon3mp|clkgen0.clkin}  -freq 100.000 -route 1.0 -clockgroup ahb_clkgroup

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# Clock to Clock

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#define_clock_delay           -rise {ddr_clk_fb} -rise {leon3mp|clkgen0.clkin} 4.0

define_clock_delay -rise leon3mp|clkgen0.xc2v.v.clk0B_derived_clock  -rise ddrspa|ddr_phy0.ddr_phy0.xc2v.ddr_phy0.clk_270ro_derived_clock -false

define_clock_delay -rise ddrspa|ddr_phy0.ddr_phy0.xc2v.ddr_phy0.clk_0ro_derived_clock -rise leon3mp|clkgen0.xc2v.v.clk0B_derived_clock -false

define_clock_delay -rise ddrspa|ddr_phy0.ddr_phy0.xc2v.ddr_phy0.clk_270ro_derived_clock -rise leon3mp|clkgen0.xc2v.v.clk0B_derived_clock -false

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# Inputs/Outputs

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define_output_delay -disable     -default  10.00 -improve 0.00 -route 0.00 -ref {clk:r}

define_input_delay -disable      -default  10.00 -improve 0.00 -route 0.00 -ref {clk:r}

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# Registers

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# Multicycle Path

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# False Path

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# Path Delay

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# Attributes

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define_global_attribute          syn_useioff {1}

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# I/O standards

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# Compile Points

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# Other Constraints

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