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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [designs/] [leon3-gr-cpci-ax/] [leon3ax.h] - Blame information for rev 2

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#include "config.h"
#if defined CONFIG_SYN_INFERRED
#define CONFIG_SYN_TECH inferred
#elif defined CONFIG_SYN_ATC18
#define CONFIG_SYN_TECH atc18
#elif defined CONFIG_SYN_AXCEL
#define CONFIG_SYN_TECH axcel
#elif defined CONFIG_SYN_PROASIC
#define CONFIG_SYN_TECH proasic
#elif defined CONFIG_SYN_VIRTEX
#define CONFIG_SYN_TECH virtex
#elif defined CONFIG_SYN_VIRTEX2
#define CONFIG_SYN_TECH virtex2
#else
#error "unknown target technology"
#endif
 
#if defined CONFIG_SYN_INFER_RAM
#define CFG_RAM_TECH inferred
#elif defined CONFIG_MEM_VIRAGE
#define CFG_RAM_TECH memvirage
#else
#define CFG_RAM_TECH CONFIG_SYN_TECH
#endif
 
#if defined CONFIG_SYN_INFER_PADS
#define CFG_PAD_TECH inferred
#else
#define CFG_PAD_TECH CONFIG_SYN_TECH
#endif
 
#if defined CONFIG_CLK_ALTDLL
#define CFG_CLK_TECH stratix
#elif defined CONFIG_CLK_HCLKBUF
#define CFG_CLK_TECH axcel
#elif defined CONFIG_CLK_CLKDLL
#define CFG_CLK_TECH virtex
#elif defined CONFIG_CLK_DCM
#define CFG_CLK_TECH virtex2
#else
#define CFG_CLK_TECH inferred
#endif
 
#ifndef CONFIG_CLK_MUL
#define CONFIG_CLK_MUL 2
#endif
 
#ifndef CONFIG_CLK_DIV
#define CONFIG_CLK_DIV 2
#endif
 
#ifndef CONFIG_PCI_CLKDLL
#define CONFIG_PCI_CLKDLL 0
#endif
 
#ifndef CONFIG_PCI_SYSCLK
#define CONFIG_PCI_SYSCLK 0
#endif
 
#ifdef CONFIG_IU_V8MULDIV
#ifdef CONFIG_IU_MUL_LATENCY_4
#define CFG_IU_V8 1
#else
#define CFG_IU_V8 2
#endif
#else
#define CFG_IU_V8 0
#endif
#ifndef CONFIG_PWD
#define CONFIG_PWD 0
#endif
 
#ifndef CONFIG_IU_MUL_MAC
#define CONFIG_IU_MUL_MAC 0
#endif
 
#if defined CONFIG_FPU_GRFPU
#define CONFIG_FPU 1
#elif defined CONFIG_FPU_MEIKO
#define CONFIG_FPU 2
#else
#define CONFIG_FPU 0
#endif
 
#ifndef CONFIG_ICACHE_ENABLE
#define CONFIG_ICACHE_ENABLE 0
#endif
 
#if defined CONFIG_ICACHE_ASSO1
#define CFG_IU_ISETS 1
#elif defined CONFIG_ICACHE_ASSO2
#define CFG_IU_ISETS 2
#elif defined CONFIG_ICACHE_ASSO3
#define CFG_IU_ISETS 3
#elif defined CONFIG_ICACHE_ASSO4
#define CFG_IU_ISETS 4
#else
#define CFG_IU_ISETS 1
#endif
 
#if defined CONFIG_ICACHE_SZ1
#define CFG_ICACHE_SZ 1
#elif defined CONFIG_ICACHE_SZ2
#define CFG_ICACHE_SZ 2
#elif defined CONFIG_ICACHE_SZ4
#define CFG_ICACHE_SZ 4
#elif defined CONFIG_ICACHE_SZ8
#define CFG_ICACHE_SZ 8
#elif defined CONFIG_ICACHE_SZ16
#define CFG_ICACHE_SZ 16
#elif defined CONFIG_ICACHE_SZ32
#define CFG_ICACHE_SZ 32
#elif defined CONFIG_ICACHE_SZ64
#define CFG_ICACHE_SZ 64
#else
#define CFG_ICACHE_SZ 1
#endif
 
#ifdef CONFIG_ICACHE_LZ16
#define CFG_ILINE_SZ 4
#else
#define CFG_ILINE_SZ 8
#endif
 
#if defined CONFIG_ICACHE_ALGORND
#define CFG_ICACHE_ALGORND 2
#elif defined CONFIG_ICACHE_ALGOLRR
#define CFG_ICACHE_ALGORND 1
#else
#define CFG_ICACHE_ALGORND 0
#endif
 
#ifndef CONFIG_ICACHE_LOCK
#define CONFIG_ICACHE_LOCK 0
#endif
 
#ifndef CONFIG_ICACHE_LRAM
#define CONFIG_ICACHE_LRAM 0
#endif
 
#ifndef CONFIG_ICACHE_LRSTART
#define CONFIG_ICACHE_LRSTART 8E
#endif
 
#if defined CONFIG_ICACHE_LRAM_SZ2
#define CFG_ILRAM_SIZE 2
#elif defined CONFIG_ICACHE_LRAM_SZ4
#define CFG_ILRAM_SIZE 4
#elif defined CONFIG_ICACHE_LRAM_SZ8
#define CFG_ILRAM_SIZE 8
#elif defined CONFIG_ICACHE_LRAM_SZ16
#define CFG_ILRAM_SIZE 16
#elif defined CONFIG_ICACHE_LRAM_SZ32
#define CFG_ILRAM_SIZE 32
#elif defined CONFIG_ICACHE_LRAM_SZ64
#define CFG_ILRAM_SIZE 64
#else
#define CFG_ILRAM_SIZE 1
#endif
 
 
#ifndef CONFIG_DCACHE_ENABLE
#define CONFIG_DCACHE_ENABLE 0
#endif
 
#if defined CONFIG_DCACHE_ASSO1
#define CFG_IU_DSETS 1
#elif defined CONFIG_DCACHE_ASSO2
#define CFG_IU_DSETS 2
#elif defined CONFIG_DCACHE_ASSO3
#define CFG_IU_DSETS 3
#elif defined CONFIG_DCACHE_ASSO4
#define CFG_IU_DSETS 4
#else
#define CFG_IU_DSETS 1
#endif
 
#if defined CONFIG_DCACHE_SZ1
#define CFG_DCACHE_SZ 1
#elif defined CONFIG_DCACHE_SZ2
#define CFG_DCACHE_SZ 2
#elif defined CONFIG_DCACHE_SZ4
#define CFG_DCACHE_SZ 4
#elif defined CONFIG_DCACHE_SZ8
#define CFG_DCACHE_SZ 8
#elif defined CONFIG_DCACHE_SZ16
#define CFG_DCACHE_SZ 16
#elif defined CONFIG_DCACHE_SZ32
#define CFG_DCACHE_SZ 32
#elif defined CONFIG_DCACHE_SZ64
#define CFG_DCACHE_SZ 64
#else
#define CFG_DCACHE_SZ 1
#endif
 
#ifdef CONFIG_DCACHE_LZ16
#define CFG_DLINE_SZ 4
#else
#define CFG_DLINE_SZ 8
#endif
 
#if defined CONFIG_DCACHE_ALGORND
#define CFG_DCACHE_ALGORND 2
#elif defined CONFIG_DCACHE_ALGOLRR
#define CFG_DCACHE_ALGORND 1
#else
#define CFG_DCACHE_ALGORND 0
#endif
 
#ifndef CONFIG_DCACHE_LOCK
#define CONFIG_DCACHE_LOCK 0
#endif
 
#ifndef CONFIG_DCACHE_SNOOP
#define CONFIG_DCACHE_SNOOP 0
#endif
 
#ifndef CONFIG_DCACHE_LRAM
#define CONFIG_DCACHE_LRAM 0
#endif
 
#ifndef CONFIG_DCACHE_LRSTART
#define CONFIG_DCACHE_LRSTART 8F
#endif
 
#if defined CONFIG_DCACHE_LRAM_SZ2
#define CFG_DLRAM_SIZE 2
#elif defined CONFIG_DCACHE_LRAM_SZ4
#define CFG_DLRAM_SIZE 4
#elif defined CONFIG_DCACHE_LRAM_SZ8
#define CFG_DLRAM_SIZE 8
#elif defined CONFIG_DCACHE_LRAM_SZ16
#define CFG_DLRAM_SIZE 16
#elif defined CONFIG_DCACHE_LRAM_SZ32
#define CFG_DLRAM_SIZE 32
#elif defined CONFIG_DCACHE_LRAM_SZ64
#define CFG_DLRAM_SIZE 64
#else
#define CFG_DLRAM_SIZE 1
#endif
 
 
#ifdef CONFIG_MMU_ENABLE
#define CONFIG_MMUEN 1
 
#ifdef CONFIG_MMU_SPLIT
#define CONFIG_TLB_TYPE 0
#endif
#ifdef CONFIG_MMU_COMBINED
#define CONFIG_TLB_TYPE 1
#endif
 
#ifdef CONFIG_MMU_REPARRAY
#define CONFIG_TLB_REP 0
#endif
#ifdef CONFIG_MMU_REPINCREMENT
#define CONFIG_TLB_REP 1
#endif
 
#ifdef CONFIG_MMU_I2 
#define CONFIG_ITLBNUM 2
#endif
#ifdef CONFIG_MMU_I4 
#define CONFIG_ITLBNUM 4
#endif
#ifdef CONFIG_MMU_I8 
#define CONFIG_ITLBNUM 8
#endif
#ifdef CONFIG_MMU_I16 
#define CONFIG_ITLBNUM 16
#endif
#ifdef CONFIG_MMU_I32
#define CONFIG_ITLBNUM 32
#endif
 
#define CONFIG_DTLBNUM 2
#ifdef CONFIG_MMU_D2 
#undef CONFIG_DTLBNUM 
#define CONFIG_DTLBNUM 2
#endif
#ifdef CONFIG_MMU_D4 
#undef CONFIG_DTLBNUM 
#define CONFIG_DTLBNUM 4
#endif
#ifdef CONFIG_MMU_D8 
#undef CONFIG_DTLBNUM 
#define CONFIG_DTLBNUM 8
#endif
#ifdef CONFIG_MMU_D16 
#undef CONFIG_DTLBNUM 
#define CONFIG_DTLBNUM 16
#endif
#ifdef CONFIG_MMU_D32
#undef CONFIG_DTLBNUM 
#define CONFIG_DTLBNUM 32
#endif
 
#else
#define CONFIG_MMUEN 0
#define CONFIG_ITLBNUM 2
#define CONFIG_DTLBNUM 2
#define CONFIG_TLB_TYPE 1
#define CONFIG_TLB_REP 1
#endif
 
 
#ifndef CONFIG_DSU_ENABLE
#define CONFIG_DSU_ENABLE 0
#endif
 
#ifndef CONFIG_DSU_UART
#define CONFIG_DSU_UART 0
#endif
 
#ifndef CONFIG_DSU_ETH
#define CONFIG_DSU_ETH 0
#endif
 
#ifndef CONFIG_DSU_ETH100
#define CONFIG_DSU_ETH100 0
#endif
 
#ifndef CONFIG_DSU_IPMSB
#define CONFIG_DSU_IPMSB C0A8
#endif
 
#ifndef CONFIG_DSU_IPLSB
#define CONFIG_DSU_IPLSB 0033
#endif
 
#ifndef CONFIG_DSU_ETHMSB
#define CONFIG_DSU_ETHMSB 00007A
#endif
 
#ifndef CONFIG_DSU_ETHLSB
#define CONFIG_DSU_ETHLSB CC0001
#endif
 
#ifndef CONFIG_DSU_ETHUDP
#define CONFIG_DSU_ETHUDP 8000
#endif
 
#if defined CONFIG_DSU_ETHSZ1
#define CFG_DSU_ETHB 1
#elif CONFIG_DSU_ETHSZ2
#define CFG_DSU_ETHB 2
#elif CONFIG_DSU_ETHSZ4
#define CFG_DSU_ETHB 4
#elif CONFIG_DSU_ETHSZ8
#define CFG_DSU_ETHB 8
#elif CONFIG_DSU_ETHSZ16
#define CFG_DSU_ETHB 16
#elif CONFIG_DSU_ETHSZ32
#define CFG_DSU_ETHB 32
#else
#define CFG_DSU_ETHB 1
#endif
 
#if defined CONFIG_DSU_ITRACESZ1
#define CFG_DSU_ITB 1
#elif CONFIG_DSU_ITRACESZ2
#define CFG_DSU_ITB 2
#elif CONFIG_DSU_ITRACESZ4
#define CFG_DSU_ITB 4
#elif CONFIG_DSU_ITRACESZ8
#define CFG_DSU_ITB 8
#elif CONFIG_DSU_ITRACESZ16
#define CFG_DSU_ITB 16
#else
#define CFG_DSU_ITB 0
#endif
 
#if defined CONFIG_DSU_ATRACESZ1
#define CFG_DSU_ATB 1
#elif CONFIG_DSU_ATRACESZ2
#define CFG_DSU_ATB 2
#elif CONFIG_DSU_ATRACESZ4
#define CFG_DSU_ATB 4
#elif CONFIG_DSU_ATRACESZ8
#define CFG_DSU_ATB 8
#elif CONFIG_DSU_ATRACESZ16
#define CFG_DSU_ATB 16
#else
#define CFG_DSU_ATB 0
#endif
 
#ifndef CONFIG_AHB_SPLIT
#define CONFIG_AHB_SPLIT 0
#endif
 
#ifndef CONFIG_AHB_RROBIN
#define CONFIG_AHB_RROBIN 0
#endif
 
#ifndef CONFIG_AHB_IOADDR
#define CONFIG_AHB_IOADDR FFF
#endif
 
#ifndef CONFIG_APB_HADDR
#define CONFIG_APB_HADDR 800
#endif
 
#if defined CONFIG_MCTRL_SMALL
#define CFG_MCTRL_TYPE 1
#ifdef CONFIG_MCTRL_SDRAM
#define CONFIG_MCTRL_SDRAM_SEPBUS 1
#endif
#elif defined CONFIG_MCTRL_LEON2
#define CFG_MCTRL_TYPE 2
#else
#define CFG_MCTRL_TYPE 0
#ifdef CONFIG_MCTRL_SDRAM
#define CONFIG_MCTRL_SDRAM_SEPBUS 1
#endif
#endif
 
#ifndef CONFIG_MCTRL_PROMWS
#define CONFIG_MCTRL_PROMWS 0
#endif
 
#ifndef CONFIG_MCTRL_RAMWS
#define CONFIG_MCTRL_RAMWS 0
#endif
 
#ifndef CONFIG_MCTRL_SDRAM
#define CONFIG_MCTRL_SDRAM 0
#endif
 
#ifndef CONFIG_MCTRL_SDRAM_SEPBUS
#define CONFIG_MCTRL_SDRAM_SEPBUS 0
#endif
 
#ifndef CONFIG_MCTRL_SDRAM_INVCLK
#define CONFIG_MCTRL_SDRAM_INVCLK 0
#endif
 
#ifndef CONFIG_MCTRL_SDRAM_BUS64
#define CONFIG_MCTRL_SDRAM_BUS64 0
#endif
 
#ifndef CONFIG_AHBRAM_ENABLE
#define CONFIG_AHBRAM_ENABLE 0
#endif
 
#ifndef CONFIG_AHBRAM_START
#define CONFIG_AHBRAM_START A00
#endif
 
#if defined CONFIG_AHBRAM_SZ1
#define CFG_AHBRAMSZ 1
#elif CONFIG_AHBRAM_SZ2
#define CFG_AHBRAMSZ 2
#elif CONFIG_AHBRAM_SZ4
#define CFG_AHBRAMSZ 4
#elif CONFIG_AHBRAM_SZ8
#define CFG_AHBRAMSZ 8
#elif CONFIG_AHBRAM_SZ16
#define CFG_AHBRAMSZ 16
#elif CONFIG_AHBRAM_SZ32
#define CFG_AHBRAMSZ 32
#elif CONFIG_AHBRAM_SZ64
#define CFG_AHBRAMSZ 64
#else
#define CFG_AHBRAMSZ 1
#endif
 
#ifndef CONFIG_AHBRAM_START
#define CONFIG_AHBRAM_START 0
#endif
 
#ifndef CONFIG_ETH_ENABLE
#define CONFIG_ETH_ENABLE 0
#endif
 
#ifndef CONFIG_ETH_START
#define CONFIG_ETH_START B00
#endif
 
#if defined CONFIG_PCI_SIMPLE_TARGET
#define CFG_PCITYPE 1
#elif defined CONFIG_PCI_MASTER_TAGET
#define CFG_PCITYPE 2
#elif defined CONFIG_PCI_MASTER_TAGET_DMA
#define CFG_PCITYPE 3
#else
#define CFG_PCITYPE 0
#endif
 
#ifndef CONFIG_PCI_VENDORID
#define CONFIG_PCI_VENDORID 0
#endif
 
#ifndef CONFIG_PCI_DEVICEID
#define CONFIG_PCI_DEVICEID 0
#endif
 
#ifndef CONFIG_PCI_REVID
#define CONFIG_PCI_REVID 0
#endif
 
#if defined CONFIG_PCI_FIFO16
#define CFG_PCIFIFO 16
#elif defined CONFIG_PCI_FIFO32
#define CFG_PCIFIFO 32
#elif defined CONFIG_PCI_FIFO64
#define CFG_PCIFIFO 64
#elif defined CONFIG_PCI_FIFO128
#define CFG_PCIFIFO 128
#elif defined CONFIG_PCI_FIFO256
#define CFG_PCIFIFO 256
#else
#define CFG_PCIFIFO 8
#endif
 
#ifndef CONFIG_PCI_ARBITER_APB
#define CONFIG_PCI_ARBITER_APB 0
#endif
 
#ifndef CONFIG_PCI_ARBITER
#define CONFIG_PCI_ARBITER 0
#endif
 
#ifndef CONFIG_PCI_TRACE
#define CONFIG_PCI_TRACE 0
#endif
 
#if defined CONFIG_PCI_TRACE512
#define CFG_PCI_TRACEBUF 512
#elif defined CONFIG_PCI_TRACE1024
#define CFG_PCI_TRACEBUF 1024
#elif defined CONFIG_PCI_TRACE2048
#define CFG_PCI_TRACEBUF 2048
#elif defined CONFIG_PCI_TRACE4096
#define CFG_PCI_TRACEBUF 4096
#else
#define CFG_PCI_TRACEBUF 256
#endif
 
#ifndef CONFIG_UART1_ENABLE
#define CONFIG_UART1_ENABLE 0
#endif
 
#if defined CONFIG_UA1_FIFO1
#define CFG_UA1_FIFO 1
#elif defined CONFIG_UA1_FIFO2
#define CFG_UA1_FIFO 2
#elif defined CONFIG_UA1_FIFO4
#define CFG_UA1_FIFO 4
#elif defined CONFIG_UA1_FIFO8
#define CFG_UA1_FIFO 8
#elif defined CONFIG_UA1_FIFO16
#define CFG_UA1_FIFO 16
#elif defined CONFIG_UA1_FIFO32
#define CFG_UA1_FIFO 32
#else
#define CFG_UA1_FIFO 1
#endif
 
#ifndef CONFIG_UART2_ENABLE
#define CONFIG_UART2_ENABLE 0
#endif
 
#if defined CONFIG_UA2_FIFO1
#define CFG_UA2_FIFO 1
#elif defined CONFIG_UA2_FIFO2
#define CFG_UA2_FIFO 2
#elif defined CONFIG_UA2_FIFO4
#define CFG_UA2_FIFO 4
#elif defined CONFIG_UA2_FIFO8
#define CFG_UA2_FIFO 8
#elif defined CONFIG_UA2_FIFO16
#define CFG_UA2_FIFO 16
#elif defined CONFIG_UA2_FIFO32
#define CFG_UA2_FIFO 32
#else
#define CFG_UA2_FIFO 1
#endif
 
#ifndef CONFIG_IRQ3_ENABLE
#define CONFIG_IRQ3_ENABLE 0
#endif
 
#ifndef CONFIG_GPT_ENABLE
#define CONFIG_GPT_ENABLE 0
#endif
 
#ifndef CONFIG_GPT_NTIM
#define CONFIG_GPT_NTIM 1
#endif
 
#ifndef CONFIG_GPT_SW
#define CONFIG_GPT_SW 8
#endif
 
#ifndef CONFIG_GPT_TW
#define CONFIG_GPT_TW 8
#endif
 
#ifndef CONFIG_GPT_IRQ
#define CONFIG_GPT_IRQ 8
#endif
 
#ifndef CONFIG_GPT_SEPIRQ
#define CONFIG_GPT_SEPIRQ 0
#endif
 
#ifndef CONFIG_GPIO_ENABLE
#define CONFIG_GPIO_ENABLE 0
#endif
 
#ifndef CONFIG_GPIO_IMASK
#define CONFIG_GPIO_IMASK 0000
#endif
 
#ifndef CONFIG_PCI_RESETALL
#define CONFIG_PCI_RESETALL 0
#endif
 
#ifndef CONFIG_IU_DISAS
#define CONFIG_IU_DISAS 0
#endif
 
#ifndef CONFIG_CAN_ENABLE
#define CONFIG_CAN_ENABLE 0
#endif
 
#ifndef CONFIG_CANIO
#define CONFIG_CANIO 0
#endif
 
#ifndef CONFIG_CANIRQ
#define CONFIG_CANIRQ 0
#endif
 
#ifndef CONFIG_CANLOOP
#define CONFIG_CANLOOP 0
#endif
 
#ifndef CONFIG_DEBUG_UART
#define CONFIG_DEBUG_UART 0
#endif
 
#ifdef CONFIG_DEBUG_PC32
#define CFG_DEBUG_PC32 0 
#else
#define CFG_DEBUG_PC32 2
#endif
 

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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [designs/] [leon3-gr-cpci-ax/] [leon3ax.h] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	dimamali	`#include "config.h"`
2			`#if defined CONFIG_SYN_INFERRED`
3			`#define CONFIG_SYN_TECH inferred`
4			`#elif defined CONFIG_SYN_ATC18`
5			`#define CONFIG_SYN_TECH atc18`
6			`#elif defined CONFIG_SYN_AXCEL`
7			`#define CONFIG_SYN_TECH axcel`
8			`#elif defined CONFIG_SYN_PROASIC`
9			`#define CONFIG_SYN_TECH proasic`
10			`#elif defined CONFIG_SYN_VIRTEX`
11			`#define CONFIG_SYN_TECH virtex`
12			`#elif defined CONFIG_SYN_VIRTEX2`
13			`#define CONFIG_SYN_TECH virtex2`
14			`#else`
15			`#error "unknown target technology"`
16			`#endif`
17
18			`#if defined CONFIG_SYN_INFER_RAM`
19			`#define CFG_RAM_TECH inferred`
20			`#elif defined CONFIG_MEM_VIRAGE`
21			`#define CFG_RAM_TECH memvirage`
22			`#else`
23			`#define CFG_RAM_TECH CONFIG_SYN_TECH`
24			`#endif`
25
26			`#if defined CONFIG_SYN_INFER_PADS`
27			`#define CFG_PAD_TECH inferred`
28			`#else`
29			`#define CFG_PAD_TECH CONFIG_SYN_TECH`
30			`#endif`
31
32			`#if defined CONFIG_CLK_ALTDLL`
33			`#define CFG_CLK_TECH stratix`
34			`#elif defined CONFIG_CLK_HCLKBUF`
35			`#define CFG_CLK_TECH axcel`
36			`#elif defined CONFIG_CLK_CLKDLL`
37			`#define CFG_CLK_TECH virtex`
38			`#elif defined CONFIG_CLK_DCM`
39			`#define CFG_CLK_TECH virtex2`
40			`#else`
41			`#define CFG_CLK_TECH inferred`
42			`#endif`
43
44			`#ifndef CONFIG_CLK_MUL`
45			`#define CONFIG_CLK_MUL 2`
46			`#endif`
47
48			`#ifndef CONFIG_CLK_DIV`
49			`#define CONFIG_CLK_DIV 2`
50			`#endif`
51
52			`#ifndef CONFIG_PCI_CLKDLL`
53			`#define CONFIG_PCI_CLKDLL 0`
54			`#endif`
55
56			`#ifndef CONFIG_PCI_SYSCLK`
57			`#define CONFIG_PCI_SYSCLK 0`
58			`#endif`
59
60			`#ifdef CONFIG_IU_V8MULDIV`
61			`#ifdef CONFIG_IU_MUL_LATENCY_4`
62			`#define CFG_IU_V8 1`
63			`#else`
64			`#define CFG_IU_V8 2`
65			`#endif`
66			`#else`
67			`#define CFG_IU_V8 0`
68			`#endif`
69			`#ifndef CONFIG_PWD`
70			`#define CONFIG_PWD 0`
71			`#endif`
72
73			`#ifndef CONFIG_IU_MUL_MAC`
74			`#define CONFIG_IU_MUL_MAC 0`
75			`#endif`
76
77			`#if defined CONFIG_FPU_GRFPU`
78			`#define CONFIG_FPU 1`
79			`#elif defined CONFIG_FPU_MEIKO`
80			`#define CONFIG_FPU 2`
81			`#else`
82			`#define CONFIG_FPU 0`
83			`#endif`
84
85			`#ifndef CONFIG_ICACHE_ENABLE`
86			`#define CONFIG_ICACHE_ENABLE 0`
87			`#endif`
88
89			`#if defined CONFIG_ICACHE_ASSO1`
90			`#define CFG_IU_ISETS 1`
91			`#elif defined CONFIG_ICACHE_ASSO2`
92			`#define CFG_IU_ISETS 2`
93			`#elif defined CONFIG_ICACHE_ASSO3`
94			`#define CFG_IU_ISETS 3`
95			`#elif defined CONFIG_ICACHE_ASSO4`
96			`#define CFG_IU_ISETS 4`
97			`#else`
98			`#define CFG_IU_ISETS 1`
99			`#endif`
100
101			`#if defined CONFIG_ICACHE_SZ1`
102			`#define CFG_ICACHE_SZ 1`
103			`#elif defined CONFIG_ICACHE_SZ2`
104			`#define CFG_ICACHE_SZ 2`
105			`#elif defined CONFIG_ICACHE_SZ4`
106			`#define CFG_ICACHE_SZ 4`
107			`#elif defined CONFIG_ICACHE_SZ8`
108			`#define CFG_ICACHE_SZ 8`
109			`#elif defined CONFIG_ICACHE_SZ16`
110			`#define CFG_ICACHE_SZ 16`
111			`#elif defined CONFIG_ICACHE_SZ32`
112			`#define CFG_ICACHE_SZ 32`
113			`#elif defined CONFIG_ICACHE_SZ64`
114			`#define CFG_ICACHE_SZ 64`
115			`#else`
116			`#define CFG_ICACHE_SZ 1`
117			`#endif`
118
119			`#ifdef CONFIG_ICACHE_LZ16`
120			`#define CFG_ILINE_SZ 4`
121			`#else`
122			`#define CFG_ILINE_SZ 8`
123			`#endif`
124
125			`#if defined CONFIG_ICACHE_ALGORND`
126			`#define CFG_ICACHE_ALGORND 2`
127			`#elif defined CONFIG_ICACHE_ALGOLRR`
128			`#define CFG_ICACHE_ALGORND 1`
129			`#else`
130			`#define CFG_ICACHE_ALGORND 0`
131			`#endif`
132
133			`#ifndef CONFIG_ICACHE_LOCK`
134			`#define CONFIG_ICACHE_LOCK 0`
135			`#endif`
136
137			`#ifndef CONFIG_ICACHE_LRAM`
138			`#define CONFIG_ICACHE_LRAM 0`
139			`#endif`
140
141			`#ifndef CONFIG_ICACHE_LRSTART`
142			`#define CONFIG_ICACHE_LRSTART 8E`
143			`#endif`
144
145			`#if defined CONFIG_ICACHE_LRAM_SZ2`
146			`#define CFG_ILRAM_SIZE 2`
147			`#elif defined CONFIG_ICACHE_LRAM_SZ4`
148			`#define CFG_ILRAM_SIZE 4`
149			`#elif defined CONFIG_ICACHE_LRAM_SZ8`
150			`#define CFG_ILRAM_SIZE 8`
151			`#elif defined CONFIG_ICACHE_LRAM_SZ16`
152			`#define CFG_ILRAM_SIZE 16`
153			`#elif defined CONFIG_ICACHE_LRAM_SZ32`
154			`#define CFG_ILRAM_SIZE 32`
155			`#elif defined CONFIG_ICACHE_LRAM_SZ64`
156			`#define CFG_ILRAM_SIZE 64`
157			`#else`
158			`#define CFG_ILRAM_SIZE 1`
159			`#endif`
160
161
162			`#ifndef CONFIG_DCACHE_ENABLE`
163			`#define CONFIG_DCACHE_ENABLE 0`
164			`#endif`
165
166			`#if defined CONFIG_DCACHE_ASSO1`
167			`#define CFG_IU_DSETS 1`
168			`#elif defined CONFIG_DCACHE_ASSO2`
169			`#define CFG_IU_DSETS 2`
170			`#elif defined CONFIG_DCACHE_ASSO3`
171			`#define CFG_IU_DSETS 3`
172			`#elif defined CONFIG_DCACHE_ASSO4`
173			`#define CFG_IU_DSETS 4`
174			`#else`
175			`#define CFG_IU_DSETS 1`
176			`#endif`
177
178			`#if defined CONFIG_DCACHE_SZ1`
179			`#define CFG_DCACHE_SZ 1`
180			`#elif defined CONFIG_DCACHE_SZ2`
181			`#define CFG_DCACHE_SZ 2`
182			`#elif defined CONFIG_DCACHE_SZ4`
183			`#define CFG_DCACHE_SZ 4`
184			`#elif defined CONFIG_DCACHE_SZ8`
185			`#define CFG_DCACHE_SZ 8`
186			`#elif defined CONFIG_DCACHE_SZ16`
187			`#define CFG_DCACHE_SZ 16`
188			`#elif defined CONFIG_DCACHE_SZ32`
189			`#define CFG_DCACHE_SZ 32`
190			`#elif defined CONFIG_DCACHE_SZ64`
191			`#define CFG_DCACHE_SZ 64`
192			`#else`
193			`#define CFG_DCACHE_SZ 1`
194			`#endif`
195
196			`#ifdef CONFIG_DCACHE_LZ16`
197			`#define CFG_DLINE_SZ 4`
198			`#else`
199			`#define CFG_DLINE_SZ 8`
200			`#endif`
201
202			`#if defined CONFIG_DCACHE_ALGORND`
203			`#define CFG_DCACHE_ALGORND 2`
204			`#elif defined CONFIG_DCACHE_ALGOLRR`
205			`#define CFG_DCACHE_ALGORND 1`
206			`#else`
207			`#define CFG_DCACHE_ALGORND 0`
208			`#endif`
209
210			`#ifndef CONFIG_DCACHE_LOCK`
211			`#define CONFIG_DCACHE_LOCK 0`
212			`#endif`
213
214			`#ifndef CONFIG_DCACHE_SNOOP`
215			`#define CONFIG_DCACHE_SNOOP 0`
216			`#endif`
217
218			`#ifndef CONFIG_DCACHE_LRAM`
219			`#define CONFIG_DCACHE_LRAM 0`
220			`#endif`
221
222			`#ifndef CONFIG_DCACHE_LRSTART`
223			`#define CONFIG_DCACHE_LRSTART 8F`
224			`#endif`
225
226			`#if defined CONFIG_DCACHE_LRAM_SZ2`
227			`#define CFG_DLRAM_SIZE 2`
228			`#elif defined CONFIG_DCACHE_LRAM_SZ4`
229			`#define CFG_DLRAM_SIZE 4`
230			`#elif defined CONFIG_DCACHE_LRAM_SZ8`
231			`#define CFG_DLRAM_SIZE 8`
232			`#elif defined CONFIG_DCACHE_LRAM_SZ16`
233			`#define CFG_DLRAM_SIZE 16`
234			`#elif defined CONFIG_DCACHE_LRAM_SZ32`
235			`#define CFG_DLRAM_SIZE 32`
236			`#elif defined CONFIG_DCACHE_LRAM_SZ64`
237			`#define CFG_DLRAM_SIZE 64`
238			`#else`
239			`#define CFG_DLRAM_SIZE 1`
240			`#endif`
241
242
243			`#ifdef CONFIG_MMU_ENABLE`
244			`#define CONFIG_MMUEN 1`
245
246			`#ifdef CONFIG_MMU_SPLIT`
247			`#define CONFIG_TLB_TYPE 0`
248			`#endif`
249			`#ifdef CONFIG_MMU_COMBINED`
250			`#define CONFIG_TLB_TYPE 1`
251			`#endif`
252
253			`#ifdef CONFIG_MMU_REPARRAY`
254			`#define CONFIG_TLB_REP 0`
255			`#endif`
256			`#ifdef CONFIG_MMU_REPINCREMENT`
257			`#define CONFIG_TLB_REP 1`
258			`#endif`
259
260			`#ifdef CONFIG_MMU_I2`
261			`#define CONFIG_ITLBNUM 2`
262			`#endif`
263			`#ifdef CONFIG_MMU_I4`
264			`#define CONFIG_ITLBNUM 4`
265			`#endif`
266			`#ifdef CONFIG_MMU_I8`
267			`#define CONFIG_ITLBNUM 8`
268			`#endif`
269			`#ifdef CONFIG_MMU_I16`
270			`#define CONFIG_ITLBNUM 16`
271			`#endif`
272			`#ifdef CONFIG_MMU_I32`
273			`#define CONFIG_ITLBNUM 32`
274			`#endif`
275
276			`#define CONFIG_DTLBNUM 2`
277			`#ifdef CONFIG_MMU_D2`
278			`#undef CONFIG_DTLBNUM`
279			`#define CONFIG_DTLBNUM 2`
280			`#endif`
281			`#ifdef CONFIG_MMU_D4`
282			`#undef CONFIG_DTLBNUM`
283			`#define CONFIG_DTLBNUM 4`
284			`#endif`
285			`#ifdef CONFIG_MMU_D8`
286			`#undef CONFIG_DTLBNUM`
287			`#define CONFIG_DTLBNUM 8`
288			`#endif`
289			`#ifdef CONFIG_MMU_D16`
290			`#undef CONFIG_DTLBNUM`
291			`#define CONFIG_DTLBNUM 16`
292			`#endif`
293			`#ifdef CONFIG_MMU_D32`
294			`#undef CONFIG_DTLBNUM`
295			`#define CONFIG_DTLBNUM 32`
296			`#endif`
297
298			`#else`
299			`#define CONFIG_MMUEN 0`
300			`#define CONFIG_ITLBNUM 2`
301			`#define CONFIG_DTLBNUM 2`
302			`#define CONFIG_TLB_TYPE 1`
303			`#define CONFIG_TLB_REP 1`
304			`#endif`
305
306
307			`#ifndef CONFIG_DSU_ENABLE`
308			`#define CONFIG_DSU_ENABLE 0`
309			`#endif`
310
311			`#ifndef CONFIG_DSU_UART`
312			`#define CONFIG_DSU_UART 0`
313			`#endif`
314
315			`#ifndef CONFIG_DSU_ETH`
316			`#define CONFIG_DSU_ETH 0`
317			`#endif`
318
319			`#ifndef CONFIG_DSU_ETH100`
320			`#define CONFIG_DSU_ETH100 0`
321			`#endif`
322
323			`#ifndef CONFIG_DSU_IPMSB`
324			`#define CONFIG_DSU_IPMSB C0A8`
325			`#endif`
326
327			`#ifndef CONFIG_DSU_IPLSB`
328			`#define CONFIG_DSU_IPLSB 0033`
329			`#endif`
330
331			`#ifndef CONFIG_DSU_ETHMSB`
332			`#define CONFIG_DSU_ETHMSB 00007A`
333			`#endif`
334
335			`#ifndef CONFIG_DSU_ETHLSB`
336			`#define CONFIG_DSU_ETHLSB CC0001`
337			`#endif`
338
339			`#ifndef CONFIG_DSU_ETHUDP`
340			`#define CONFIG_DSU_ETHUDP 8000`
341			`#endif`
342
343			`#if defined CONFIG_DSU_ETHSZ1`
344			`#define CFG_DSU_ETHB 1`
345			`#elif CONFIG_DSU_ETHSZ2`
346			`#define CFG_DSU_ETHB 2`
347			`#elif CONFIG_DSU_ETHSZ4`
348			`#define CFG_DSU_ETHB 4`
349			`#elif CONFIG_DSU_ETHSZ8`
350			`#define CFG_DSU_ETHB 8`
351			`#elif CONFIG_DSU_ETHSZ16`
352			`#define CFG_DSU_ETHB 16`
353			`#elif CONFIG_DSU_ETHSZ32`
354			`#define CFG_DSU_ETHB 32`
355			`#else`
356			`#define CFG_DSU_ETHB 1`
357			`#endif`
358
359			`#if defined CONFIG_DSU_ITRACESZ1`
360			`#define CFG_DSU_ITB 1`
361			`#elif CONFIG_DSU_ITRACESZ2`
362			`#define CFG_DSU_ITB 2`
363			`#elif CONFIG_DSU_ITRACESZ4`
364			`#define CFG_DSU_ITB 4`
365			`#elif CONFIG_DSU_ITRACESZ8`
366			`#define CFG_DSU_ITB 8`
367			`#elif CONFIG_DSU_ITRACESZ16`
368			`#define CFG_DSU_ITB 16`
369			`#else`
370			`#define CFG_DSU_ITB 0`
371			`#endif`
372
373			`#if defined CONFIG_DSU_ATRACESZ1`
374			`#define CFG_DSU_ATB 1`
375			`#elif CONFIG_DSU_ATRACESZ2`
376			`#define CFG_DSU_ATB 2`
377			`#elif CONFIG_DSU_ATRACESZ4`
378			`#define CFG_DSU_ATB 4`
379			`#elif CONFIG_DSU_ATRACESZ8`
380			`#define CFG_DSU_ATB 8`
381			`#elif CONFIG_DSU_ATRACESZ16`
382			`#define CFG_DSU_ATB 16`
383			`#else`
384			`#define CFG_DSU_ATB 0`
385			`#endif`
386
387			`#ifndef CONFIG_AHB_SPLIT`
388			`#define CONFIG_AHB_SPLIT 0`
389			`#endif`
390
391			`#ifndef CONFIG_AHB_RROBIN`
392			`#define CONFIG_AHB_RROBIN 0`
393			`#endif`
394
395			`#ifndef CONFIG_AHB_IOADDR`
396			`#define CONFIG_AHB_IOADDR FFF`
397			`#endif`
398
399			`#ifndef CONFIG_APB_HADDR`
400			`#define CONFIG_APB_HADDR 800`
401			`#endif`
402
403			`#if defined CONFIG_MCTRL_SMALL`
404			`#define CFG_MCTRL_TYPE 1`
405			`#ifdef CONFIG_MCTRL_SDRAM`
406			`#define CONFIG_MCTRL_SDRAM_SEPBUS 1`
407			`#endif`
408			`#elif defined CONFIG_MCTRL_LEON2`
409			`#define CFG_MCTRL_TYPE 2`
410			`#else`
411			`#define CFG_MCTRL_TYPE 0`
412			`#ifdef CONFIG_MCTRL_SDRAM`
413			`#define CONFIG_MCTRL_SDRAM_SEPBUS 1`
414			`#endif`
415			`#endif`
416
417			`#ifndef CONFIG_MCTRL_PROMWS`
418			`#define CONFIG_MCTRL_PROMWS 0`
419			`#endif`
420
421			`#ifndef CONFIG_MCTRL_RAMWS`
422			`#define CONFIG_MCTRL_RAMWS 0`
423			`#endif`
424
425			`#ifndef CONFIG_MCTRL_SDRAM`
426			`#define CONFIG_MCTRL_SDRAM 0`
427			`#endif`
428
429			`#ifndef CONFIG_MCTRL_SDRAM_SEPBUS`
430			`#define CONFIG_MCTRL_SDRAM_SEPBUS 0`
431			`#endif`
432
433			`#ifndef CONFIG_MCTRL_SDRAM_INVCLK`
434			`#define CONFIG_MCTRL_SDRAM_INVCLK 0`
435			`#endif`
436
437			`#ifndef CONFIG_MCTRL_SDRAM_BUS64`
438			`#define CONFIG_MCTRL_SDRAM_BUS64 0`
439			`#endif`
440
441			`#ifndef CONFIG_AHBRAM_ENABLE`
442			`#define CONFIG_AHBRAM_ENABLE 0`
443			`#endif`
444
445			`#ifndef CONFIG_AHBRAM_START`
446			`#define CONFIG_AHBRAM_START A00`
447			`#endif`
448
449			`#if defined CONFIG_AHBRAM_SZ1`
450			`#define CFG_AHBRAMSZ 1`
451			`#elif CONFIG_AHBRAM_SZ2`
452			`#define CFG_AHBRAMSZ 2`
453			`#elif CONFIG_AHBRAM_SZ4`
454			`#define CFG_AHBRAMSZ 4`
455			`#elif CONFIG_AHBRAM_SZ8`
456			`#define CFG_AHBRAMSZ 8`
457			`#elif CONFIG_AHBRAM_SZ16`
458			`#define CFG_AHBRAMSZ 16`
459			`#elif CONFIG_AHBRAM_SZ32`
460			`#define CFG_AHBRAMSZ 32`
461			`#elif CONFIG_AHBRAM_SZ64`
462			`#define CFG_AHBRAMSZ 64`
463			`#else`
464			`#define CFG_AHBRAMSZ 1`
465			`#endif`
466
467			`#ifndef CONFIG_AHBRAM_START`
468			`#define CONFIG_AHBRAM_START 0`
469			`#endif`
470
471			`#ifndef CONFIG_ETH_ENABLE`
472			`#define CONFIG_ETH_ENABLE 0`
473			`#endif`
474
475			`#ifndef CONFIG_ETH_START`
476			`#define CONFIG_ETH_START B00`
477			`#endif`
478
479			`#if defined CONFIG_PCI_SIMPLE_TARGET`
480			`#define CFG_PCITYPE 1`
481			`#elif defined CONFIG_PCI_MASTER_TAGET`
482			`#define CFG_PCITYPE 2`
483			`#elif defined CONFIG_PCI_MASTER_TAGET_DMA`
484			`#define CFG_PCITYPE 3`
485			`#else`
486			`#define CFG_PCITYPE 0`
487			`#endif`
488
489			`#ifndef CONFIG_PCI_VENDORID`
490			`#define CONFIG_PCI_VENDORID 0`
491			`#endif`
492
493			`#ifndef CONFIG_PCI_DEVICEID`
494			`#define CONFIG_PCI_DEVICEID 0`
495			`#endif`
496
497			`#ifndef CONFIG_PCI_REVID`
498			`#define CONFIG_PCI_REVID 0`
499			`#endif`
500
501			`#if defined CONFIG_PCI_FIFO16`
502			`#define CFG_PCIFIFO 16`
503			`#elif defined CONFIG_PCI_FIFO32`
504			`#define CFG_PCIFIFO 32`
505			`#elif defined CONFIG_PCI_FIFO64`
506			`#define CFG_PCIFIFO 64`
507			`#elif defined CONFIG_PCI_FIFO128`
508			`#define CFG_PCIFIFO 128`
509			`#elif defined CONFIG_PCI_FIFO256`
510			`#define CFG_PCIFIFO 256`
511			`#else`
512			`#define CFG_PCIFIFO 8`
513			`#endif`
514
515			`#ifndef CONFIG_PCI_ARBITER_APB`
516			`#define CONFIG_PCI_ARBITER_APB 0`
517			`#endif`
518
519			`#ifndef CONFIG_PCI_ARBITER`
520			`#define CONFIG_PCI_ARBITER 0`
521			`#endif`
522
523			`#ifndef CONFIG_PCI_TRACE`
524			`#define CONFIG_PCI_TRACE 0`
525			`#endif`
526
527			`#if defined CONFIG_PCI_TRACE512`
528			`#define CFG_PCI_TRACEBUF 512`
529			`#elif defined CONFIG_PCI_TRACE1024`
530			`#define CFG_PCI_TRACEBUF 1024`
531			`#elif defined CONFIG_PCI_TRACE2048`
532			`#define CFG_PCI_TRACEBUF 2048`
533			`#elif defined CONFIG_PCI_TRACE4096`
534			`#define CFG_PCI_TRACEBUF 4096`
535			`#else`
536			`#define CFG_PCI_TRACEBUF 256`
537			`#endif`
538
539			`#ifndef CONFIG_UART1_ENABLE`
540			`#define CONFIG_UART1_ENABLE 0`
541			`#endif`
542
543			`#if defined CONFIG_UA1_FIFO1`
544			`#define CFG_UA1_FIFO 1`
545			`#elif defined CONFIG_UA1_FIFO2`
546			`#define CFG_UA1_FIFO 2`
547			`#elif defined CONFIG_UA1_FIFO4`
548			`#define CFG_UA1_FIFO 4`
549			`#elif defined CONFIG_UA1_FIFO8`
550			`#define CFG_UA1_FIFO 8`
551			`#elif defined CONFIG_UA1_FIFO16`
552			`#define CFG_UA1_FIFO 16`
553			`#elif defined CONFIG_UA1_FIFO32`
554			`#define CFG_UA1_FIFO 32`
555			`#else`
556			`#define CFG_UA1_FIFO 1`
557			`#endif`
558
559			`#ifndef CONFIG_UART2_ENABLE`
560			`#define CONFIG_UART2_ENABLE 0`
561			`#endif`
562
563			`#if defined CONFIG_UA2_FIFO1`
564			`#define CFG_UA2_FIFO 1`
565			`#elif defined CONFIG_UA2_FIFO2`
566			`#define CFG_UA2_FIFO 2`
567			`#elif defined CONFIG_UA2_FIFO4`
568			`#define CFG_UA2_FIFO 4`
569			`#elif defined CONFIG_UA2_FIFO8`
570			`#define CFG_UA2_FIFO 8`
571			`#elif defined CONFIG_UA2_FIFO16`
572			`#define CFG_UA2_FIFO 16`
573			`#elif defined CONFIG_UA2_FIFO32`
574			`#define CFG_UA2_FIFO 32`
575			`#else`
576			`#define CFG_UA2_FIFO 1`
577			`#endif`
578
579			`#ifndef CONFIG_IRQ3_ENABLE`
580			`#define CONFIG_IRQ3_ENABLE 0`
581			`#endif`
582
583			`#ifndef CONFIG_GPT_ENABLE`
584			`#define CONFIG_GPT_ENABLE 0`
585			`#endif`
586
587			`#ifndef CONFIG_GPT_NTIM`
588			`#define CONFIG_GPT_NTIM 1`
589			`#endif`
590
591			`#ifndef CONFIG_GPT_SW`
592			`#define CONFIG_GPT_SW 8`
593			`#endif`
594
595			`#ifndef CONFIG_GPT_TW`
596			`#define CONFIG_GPT_TW 8`
597			`#endif`
598
599			`#ifndef CONFIG_GPT_IRQ`
600			`#define CONFIG_GPT_IRQ 8`
601			`#endif`
602
603			`#ifndef CONFIG_GPT_SEPIRQ`
604			`#define CONFIG_GPT_SEPIRQ 0`
605			`#endif`
606
607			`#ifndef CONFIG_GPIO_ENABLE`
608			`#define CONFIG_GPIO_ENABLE 0`
609			`#endif`
610
611			`#ifndef CONFIG_GPIO_IMASK`
612			`#define CONFIG_GPIO_IMASK 0000`
613			`#endif`
614
615			`#ifndef CONFIG_PCI_RESETALL`
616			`#define CONFIG_PCI_RESETALL 0`
617			`#endif`
618
619			`#ifndef CONFIG_IU_DISAS`
620			`#define CONFIG_IU_DISAS 0`
621			`#endif`
622
623			`#ifndef CONFIG_CAN_ENABLE`
624			`#define CONFIG_CAN_ENABLE 0`
625			`#endif`
626
627			`#ifndef CONFIG_CANIO`
628			`#define CONFIG_CANIO 0`
629			`#endif`
630
631			`#ifndef CONFIG_CANIRQ`
632			`#define CONFIG_CANIRQ 0`
633			`#endif`
634
635			`#ifndef CONFIG_CANLOOP`
636			`#define CONFIG_CANLOOP 0`
637			`#endif`
638
639			`#ifndef CONFIG_DEBUG_UART`
640			`#define CONFIG_DEBUG_UART 0`
641			`#endif`
642
643			`#ifdef CONFIG_DEBUG_PC32`
644			`#define CFG_DEBUG_PC32 0`
645			`#else`
646			`#define CFG_DEBUG_PC32 2`
647			`#endif`
648