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Prompt for target technology

CONFIG_SYN_INFERRED

  Selects the target technology for memory and pads.

  The following are available:

  - Inferred: Generic FPGA or ASIC targets if your synthesis tool

    is capable of inferring RAMs and pads automatically.

  - Actel ProAsic/P/3 and Axellerator FPGAs

  - Aeroflex UT25CRH Rad-Hard 0.25 um CMOS

  - Altera: Most Altera FPGA families

  - Altera-Stratix: Altera Stratix FPGA family

  - Altera-StratixII: Altera Stratix-II FPGA family

  - ATC18: Atmel-Nantes 0.18 um rad-hard CMOS

  - IHP25: IHP 0.25 um CMOS

  - IHP25RH: IHP Rad-Hard 0.25 um CMOS

  - Lattice : EC/ECP/XP FPGAs

  - Quicklogic : Eclipse/E/II FPGAs

  - UMC-0.18 : UMC 0.18 um CMOS with Virtual Silicon libraries

  - Xilinx-Spartan/2/3: Xilinx Spartan/2/3 libraries

  - Xilinx-Spartan3E: Xilinx Spartan3E libraries

  - Xilinx-Virtex/E: Xilinx Virtex/E libraries

  - Xilinx-Virtex2/4/5: Xilinx Virtex2/4/5 libraries

Ram library

CONFIG_MEM_VIRAGE

  Select RAM generators for ASIC targets.

Infer ram

CONFIG_SYN_INFER_RAM

  Say Y here if you want the synthesis tool to infer your

  RAM automatically. Say N to directly instantiate technology-

  specific RAM cells for the selected target technology package.

Infer pads

CONFIG_SYN_INFER_PADS

  Say Y here if you want the synthesis tool to infer pads.

  Say N to directly instantiate technology-specific pads from

  the selected target technology package.

No async reset

CONFIG_SYN_NO_ASYNC

  Say Y here if you disable asynchronous reset in some of the IP cores.

  Might be necessary if the target library does not have cells with

  asynchronous set/reset.

Scan support

CONFIG_SYN_SCAN

  Say Y here to enable scan support in some cores. This will enable

  the scan support generics where available and add logic to make

  the design testable using full-scan.

Use Virtex CLKDLL for clock synchronisation

CONFIG_CLK_INFERRED

  Certain target technologies include clock generators to scale or

  phase-adjust the system and SDRAM clocks. This is currently supported

  for Xilinx, Altera and Proasic3 FPGAs. Depending on technology, you

  can select to use the Xilinx CKLDLL macro (Virtex, VirtexE, Spartan1/2),

  the Xilinx DCM (Virtex-2, Spartan3, Virtex-4), the Altera ALTDLL

  (Stratix, Cyclone), or the Proasic3 PLL. Choose the 'inferred'

  option to skip a clock generator.

Clock multiplier

CONFIG_CLK_MUL

  When using the Xilinx DCM or Altera ALTPLL, the system clock can

  be multiplied with a factor of 2 - 32, and divided by a factor of

  1 - 32. This makes it possible to generate almost any desired

  processor frequency. When using the Xilinx CLKDLL generator,

  the resulting frequency scale factor (mul/div) must be one of

  1/2, 1 or 2. On Proasic3, the factor can be 1 - 128.

  WARNING: The resulting clock must be within the limits specified

  by the target FPGA family.

Clock divider

CONFIG_CLK_DIV

  When using the Xilinx DCM or Altera ALTPLL, the system clock can

  be multiplied with a factor of 2 - 32, and divided by a factor of

  1 - 32. This makes it possible to generate almost any desired

  processor frequency. When using the Xilinx CLKDLL generator,

  the resulting frequency scale factor (mul/div) must be one of

  1/2, 1 or 2. On Proasic3, the factor can be 1 - 128.

  WARNING: The resulting clock must be within the limits specified

  by the target FPGA family.

Output clock divider

CONFIG_OCLK_DIV

  When using the Proasic3 PLL, the system clock is generated by three

  parameters: input clock multiplication, input clock division and

  output clock division. Only certain values of these parameters

  are allowed, but unfortunately this is not documented by Actel.

  To find the correct values, run the Libero Smartgen tool and

  insert you desired input and output clock frequencies in the

  Static PLL configurator. The mul/div factors can then be read

  out from tool.

System clock multiplier

CONFIG_CLKDLL_1_2

  The Xilinx CLKDLL can scale the input clock with a factor of 0.5, 1.0,

  or 2.0. Useful when the target board has an oscillator with a too high

  (or low) frequency for your design. The divided clock will be used as the

  main clock for the whole processor (except PCI and ethernet clocks).

System clock multiplier

CONFIG_DCM_2_3

  The Xilinx DCM and Altera ALTDLL can scale the input clock with a large

  range of factors. Useful when the target board has an oscillator with a

  too high (or low) frequency for your design. The divided clock will

  be used as the main clock for the whole processor (except PCI and

  ethernet clocks). NOTE: the resulting frequency must be at least

  24 MHz or the DCM and ALTDLL might not work.

Enable CLKDLL for PCI clock

CONFIG_PCI_CLKDLL

  Say Y here to re-synchronize the PCI clock using a

  Virtex BUFGDLL macro. Will improve PCI clock-to-output

  delays on the expense of input-setup requirements.

Use PCI clock system clock

CONFIG_PCI_SYSCLK

  Say Y here to the PCI clock to generate the system clock.

  The PCI clock can be scaled using the DCM or CLKDLL to

  generate a suitable processor clock.

External SDRAM clock feedback

CONFIG_CLK_NOFB

  Say Y here to disable the external clock feedback to synchronize the

  SDRAM clock. This option is necessary if your board or design does not

  have an external clock feedback that is connected to the pllref input

  of the clock generator.

Number of processors

CONFIG_PROC_NUM

  The number of processor cores. The LEON3MP design can accomodate

  up to 4 LEON3 processor cores. Use 1 unless you know what you are

  doing ...

Number of SPARC register windows

CONFIG_IU_NWINDOWS

  The SPARC architecture (and LEON) allows 2 - 32 register windows.

  However, any number except 8 will require that you modify and

  recompile your run-time system or kernel. Unless you know what

  you are doing, use 8.

SPARC V8 multiply and divide instruction

CONFIG_IU_V8MULDIV

  If you say Y here, the SPARC V8 multiply and divide instructions

  will be implemented. The instructions are: UMUL, UMULCC, SMUL,

  SMULCC, UDIV, UDIVCC, SDIV, SDIVCC. In code containing frequent

  integer multiplications and divisions, significant performance

  increase can be achieved. Emulated floating-point operations will

  also benefit from this option.

  By default, the gcc compiler does not emit multiply or divide

  instructions and your code must be compiled with -mv8 to see any

  performance increase. On the other hand, code compiled with -mv8

  will generate an illegal instruction trap when executed on processors

  with this option disabled.

  The divider consumes approximately 2 kgates, the multiplier 6 kgates.

Multiplier latency

CONFIG_IU_MUL_LATENCY_2

  Implementation options for the integer multiplier.

  Type        Implementation              issue-rate/latency

  2-clocks    32x32 pipelined multiplier     1/2

  4-clocks    16x16 standard multiplier      4/4

  5-clocks    16x16 pipelined multiplier     4/5

Multiplier latency

CONFIG_IU_MUL_MAC

  If you say Y here, the SPARC V8e UMAC/SMAC (multiply-accumulate)

  instructions will be enabled. The instructions implement a

  single-cycle 16x16->32 bits multiply with a 40-bits accumulator.

  The details of these instructions can be found in the LEON manual,

  This option is only available when 16x16 multiplier is used.

Single vector trapping

CONFIG_IU_SVT

  Single-vector trapping is a SPARC V8e option to reduce code-size

  in small applications. If enabled, the processor will jump to

  the address of trap 0 (tt = 0x00) for all traps. No trap table

  is then needed. The trap type is present in %psr.tt and must

  be decoded by the O/S. Saves 4 Kbyte of code, but increases

  trap and interrupt overhead. Currently, the only O/S supporting

  this option is eCos. To enable SVT, the O/S must also set bit 13

  in %asr17.

Load latency

CONFIG_IU_LDELAY

  Defines the pipeline load delay (= pipeline cycles before the data

  from a load instruction is available for the next instruction).

  One cycle gives best performance, but might create a critical path

  on targets with slow (data) cache memories. A 2-cycle delay can

  improve timing but will reduce performance with about 5%.

Reset address

CONFIG_IU_RSTADDR

  By default, a SPARC processor starts execution at address 0.

  With this option, any 4-kbyte aligned reset start address can be

  choosen. Keep at 0 unless you really know what you are doing.

Power-down

CONFIG_PWD

  Say Y here to enable the power-down feature of the processor.

  Might reduce the maximum frequency slightly on FPGA targets.

  For details on the power-down operation, see the LEON3 manual.

Hardware watchpoints

CONFIG_IU_WATCHPOINTS

  The processor can have up to 4 hardware watchpoints, allowing to

  create both data and instruction breakpoints at any memory location,

  also in PROM. Each watchpoint will use approximately 500 gates.

  Use 0 to disable the watchpoint function.

Floating-point enable

CONFIG_FPU_ENABLE

  Say Y here to enable the floating-point interface for the MEIKO

  or GRFPU. Note that no FPU's are provided with the GPL version

  of GRLIB. Both the Gaisler GRFPU and the Meiko FPU are commercial

  cores and must be obtained separately.

FPU selection

CONFIG_FPU_GRFPU

  Select between Gaisler Research's GRFPU and GRFPU-lite FPUs or the Sun

  Meiko FPU core. All cores  are fully IEEE-754 compatible and support

  all SPARC FPU instructions.

GRFPU Multiplier

CONFIG_FPU_GRFPU_INFMUL

  On FPGA targets choose inferred multiplier. For ASIC implementations

  choose between Synopsys Design Ware (DW) multiplier or Module

  Generator (ModGen) multiplier. The DW multiplier gives better results

  (smaller area and better timing) but requires a DW license.

  The ModGen multiplier is part of GRLIB and does not require a license.

Shared GRFPU

CONFIG_FPU_GRFPU_SH

  If enabled multiple CPU cores will share one GRFPU.

GRFPC Configuration

CONFIG_FPU_GRFPC0

  Configures the GRFPU-LITE controller.

  In simple configuration controller executes FP instructions

  in parallel with  integer instructions. FP operands are fetched

  in the register file stage and the result is written in the write

  stage. This option uses least area resources.

  Data forwarding configuration gives ~ 10 % higher FP performance than

  the simple configuration by adding data forwarding between the pipeline

  stages.

  Non-blocking controller allows FP load and store instructions to

  execute in parallel with FP instructions. The performance increase is

  ~ 20 % for FP applications. This option uses most logic resources and

  is suitable for ASIC implementations.

Floating-point netlist

CONFIG_FPU_NETLIST

  Say Y here to use a VHDL netlist of the GRFPU-Lite. This is

  only available in certain versions of grlib.

Enable Instruction cache

CONFIG_ICACHE_ENABLE

  The instruction cache should always be enabled to allow

  maximum performance. Some low-end system might want to

  save area and disable the cache, but this will reduce

  the performance with a factor of 2 - 3.

Enable Data cache

CONFIG_DCACHE_ENABLE

  The data cache should always be enabled to allow

  maximum performance. Some low-end system might want to

  save area and disable the cache, but this will reduce

  the performance with a factor of 2 at least.

Instruction cache associativity

CONFIG_ICACHE_ASSO1

  The instruction cache can be implemented as a multi-set cache with

  1 - 4 sets. Higher associativity usually increases the cache hit

  rate and thereby the performance. The downside is higher power

  consumption and increased gate-count for tag comparators.

  Note that a 1-set cache is effectively a direct-mapped cache.

Instruction cache set size

CONFIG_ICACHE_SZ1

  The size of each set in the instuction cache (kbytes). Valid values

  are 1 - 64 in binary steps. Note that the full range is only supported

  by the generic and virtex2 targets. Most target packages are limited

  to 2 - 16 kbyte. Large set size gives higher performance but might

  affect the maximum frequency (on ASIC targets). The total instruction

  cache size is the number of set multiplied with the set size.

Instruction cache line size

CONFIG_ICACHE_LZ16

  The instruction cache line size. Can be set to either 16 or 32

  bytes per line. Instruction caches typically benefit from larger

  line sizes, but on small caches it migh be better with 16 bytes/line

  to limit eviction miss rate.

Instruction cache replacement algorithm

CONFIG_ICACHE_ALGORND

  Cache replacement algorithm for caches with 2 - 4 sets. The 'random'

  algorithm selects the set to evict randomly. The least-recently-used

  (LRR) algorithm evicts the set least recently replaced. The least-

  recently-used (LRU) algorithm evicts the set least recently accessed.

  The random algorithm uses a simple 1- or 2-bit counter to select

  the eviction set and has low area overhead. The LRR scheme uses one

  extra bit in the tag ram and has therefore also low area overhead.

  However, the LRR scheme can only be used with 2-set caches. The LRU

  scheme has typically the best performance but also highest area overhead.

  A 2-set LRU uses 1 flip-flop per line, a 3-set LRU uses 3 flip-flops

  per line, and a 4-set LRU uses 5 flip-flops per line to store the access

  history.

Instruction cache locking

CONFIG_ICACHE_LOCK

  Say Y here to enable cache locking in the instruction cache.

  Locking can be done on cache-line level, but will increase the

  width of the tag ram with one bit. If you don't know what

  locking is good for, it is safe to say N.

Data cache associativity

CONFIG_DCACHE_ASSO1

  The data cache can be implemented as a multi-set cache with

  1 - 4 sets. Higher associativity usually increases the cache hit

  rate and thereby the performance. The downside is higher power

  consumption and increased gate-count for tag comparators.

  Note that a 1-set cache is effectively a direct-mapped cache.

Data cache set size

CONFIG_DCACHE_SZ1

  The size of each set in the data cache (kbytes). Valid values are

  1 - 64 in binary steps. Note that the full range is only supported

  by the generic and virtex2 targets. Most target packages are limited

  to 2 - 16 kbyte. A large cache gives higher performance but the

  data cache is timing critical an a too large setting might affect

  the maximum frequency (on ASIC targets). The total data cache size

  is the number of set multiplied with the set size.

Data cache line size

CONFIG_DCACHE_LZ16

  The data cache line size. Can be set to either 16 or 32 bytes per

  line. A smaller line size gives better associativity and higher

  cache hit rate, but requires a larger tag memory.

Data cache replacement algorithm

CONFIG_DCACHE_ALGORND

  See the explanation for instruction cache replacement algorithm.

Data cache locking

CONFIG_DCACHE_LOCK

  Say Y here to enable cache locking in the data cache.

  Locking can be done on cache-line level, but will increase the

  width of the tag ram with one bit. If you don't know what

  locking is good for, it is safe to say N.

Data cache snooping

CONFIG_DCACHE_SNOOP

  Say Y here to enable data cache snooping on the AHB bus. Is only

  useful if you have additional AHB masters such as the DSU or a

  target PCI interface. Note that the target technology must support

  dual-port RAMs for this option to be enabled. Dual-port RAMS are

  currently supported on Virtex/2, Virage and Actel targets.

Data cache snooping implementation

CONFIG_DCACHE_SNOOP_FAST

  The default snooping implementation is 'slow', which works if you

  don't have AHB slaves in cacheable areas capable of zero-waitstates

  non-sequential write accesses. Otherwise use 'fast' and suffer a

  few kgates extra area. This option is currently only needed in

  multi-master systems with the SSRAM or DDR memory controllers.

Separate snoop tags

CONFIG_DCACHE_SNOOP_SEPTAG

  Enable a separate memory to store the data tags used for snooping.

  This is necessary when snooping support is wanted in systems

  with MMU, typically for SMP systems. In this case, the snoop

  tags will contain the physical tag address while the normal

  tags contain the virtual tag address. This option can also be

  together with the 'fast snooping' option to enable snooping

  support on technologies without dual-port RAMs. In such case,

  the snoop tag RAM will be implemented using a two-port RAM.

Fixed cacheability map

CONFIG_CACHE_FIXED

  If this variable is 0, the cacheable memory regions are defined

  by the AHB plug&play information (default). To overriden the

  plug&play settings, this variable can be set to indicate which

  areas should be cached. The value is treated as a 16-bit hex value

  with each bit defining if a 256 Mbyte segment should be cached or not.

  The right-most (LSB) bit defines the cacheability of AHB address

  3840 - 4096 MByte. If the bit is set, the corresponding area is

  cacheable. A value of 00F3 defines address 0 - 0x20000000 and

  0x40000000 - 0x80000000 as cacheable.

Local data ram

CONFIG_DCACHE_LRAM

  Say Y here to add a local ram to the data cache controller.

  Accesses to the ram (load/store) will be performed at 0 waitstates

  and store data will never be written back to the AHB bus.

Size of local data ram

CONFIG_DCACHE_LRAM_SZ1

  Defines the size of the local data ram in Kbytes. Note that most

  technology libraries do not support larger rams than 16 Kbyte.

Start address of local data ram

CONFIG_DCACHE_LRSTART

  Defines the 8 MSB bits of start address of the local data ram.

  By default set to 8f (start address = 0x8f000000), but any value

  (except 0) is possible. Note that the local data ram 'shadows'

  a 16 Mbyte block of the address space.

MMU enable

CONFIG_MMU_ENABLE

  Say Y here to enable the Memory Management Unit.

MMU split icache/dcache table lookaside buffer

CONFIG_MMU_COMBINED

  Select "combined" for a combined icache/dcache table lookaside buffer,

  "split" for a split icache/dcache table lookaside buffer

MMU tlb replacement scheme

CONFIG_MMU_REPARRAY

  Select "LRU" to use the "least recently used" algorithm for TLB

  replacement, or "Increment" for a simple incremental replacement

  scheme.

Combined i/dcache tlb

CONFIG_MMU_I2

  Select the number of entries for the instruction TLB, or the

  combined icache/dcache TLB if such is used.

Split tlb, dcache

CONFIG_MMU_D2

  Select the number of entries for the dcache TLB.

Fast writebuffer

CONFIG_MMU_FASTWB

  Only selectable if split tlb is enabled. In case fast writebuffer is

  enabled the tlb hit will be made concurrent to the cache hit. This

  leads to higher store performance, but increased power and area.

DSU enable

CONFIG_DSU_ENABLE

  The debug support unit (DSU) allows non-intrusive debugging and tracing

  of both executed instructions and AHB transfers. If you want to enable

  the DSU, say Y here and select the configuration below.

Trace buffer enable

CONFIG_DSU_TRACEBUF

  Say Y to enable the trace buffer. The buffer is not necessary for

  debugging, only for tracing instructions and data transfers.

Enable instruction tracing

CONFIG_DSU_ITRACE

  If you say Y here, an instruction trace buffer will be implemented

  in each processor. The trace buffer will trace executed instructions

  and their results, and place them in a circular buffer. The buffer

  can be read out by any AHB master, and in particular by the debug

  communication link.

Size of trace buffer

CONFIG_DSU_ITRACESZ1

  Select the buffer size (in kbytes) for the instruction trace buffer.

  Each line in the buffer needs 16 bytes. A 128-entry buffer will thus

  need 2 kbyte.

Enable AHB tracing

CONFIG_DSU_ATRACE

  If you say Y here, an AHB trace buffer will be implemented in the

  debug support unit processor. The AHB buffer will trace all transfers

  on the AHB bus and save them in a circular buffer. The trace buffer

  can be read out by any AHB master, and in particular by the debug

  communication link.

Size of trace buffer

CONFIG_DSU_ATRACESZ1

  Select the buffer size (in kbytes) for the AHB trace buffer.

  Each line in the buffer needs 16 bytes. A 128-entry buffer will thus

  need 2 kbyte.

LEON3FT enable

CONFIG_LEON3FT_EN

  Say Y here to use the fault-tolerant LEON3FT core instead of the

  standard non-FT LEON3.

IU Register file protection

CONFIG_IUFT_NONE

  Select the FT implementation in the LEON3FT integer unit

  register file. The options include parity, parity with

  sparing, 7-bit BCH and TMR.

FPU Register file protection

CONFIG_FPUFT_EN

  Say Y to enable SEU protection of the FPU register file.

  The GRFPU will be protected using 8-bit parity without restart, while

  the GRFPU-Lite will be protected with 4-bit parity with restart. If

  disabled the FPU register file will be implemented using flip-flops.

Cache memory error injection

CONFIG_RF_ERRINJ

  Say Y here to enable error injection in to the IU/FPU regfiles.

  Affects only simulation.

Cache memory protection

CONFIG_CACHE_FT_EN

  Enable SEU error-correction in the cache memories.

Cache memory error injection

CONFIG_CACHE_ERRINJ

  Say Y here to enable error injection in to the cache memories.

  Affects only simulation.

Leon3ft netlist

CONFIG_LEON3_NETLIST

  Say Y here to use a VHDL netlist of the LEON3FT. This is

  only available in certain versions of grlib.

IU assembly printing

CONFIG_IU_DISAS

  Enable printing of executed instructions to the console.

IU assembly printing in netlist

CONFIG_IU_DISAS_NET

  Enable printing of executed instructions to the console also

  when simulating a netlist. NOTE: with this option enabled, it

  will not be possible to pass place&route.

32-bit program counters

CONFIG_DEBUG_PC32

  Since the LSB 2 bits of the program counters always are zero, they are

  normally not implemented. If you say Y here, the program counters will

  be implemented with full 32 bits, making debugging of the VHDL model

  much easier. Turn of this option for synthesis or you will be wasting

  area.

CONFIG_AHB_DEFMST

  Sets the default AHB master (see AMBA 2.0 specification for definition).

  Should not be set to a value larger than the number of AHB masters - 1.

  For highest processor performance, leave it at 0.

Default AHB master

CONFIG_AHB_RROBIN

  Say Y here to enable round-robin arbitration of the AHB bus. A N will

  select fixed priority, with the master with the highest bus index having

  the highest priority.

Support AHB split-transactions

CONFIG_AHB_SPLIT

  Say Y here to enable AHB split-transaction support in the AHB arbiter.

  Unless you actually have an AHB slave that can generate AHB split

  responses, say N and save some gates.

Default AHB master

CONFIG_AHB_IOADDR

  Selects the MSB adddress (HADDR[31:20]) of the AHB IO area, as defined

  in the plug&play extentions of the AMBA bus. Should be kept to FFF

  unless you really know what you are doing.

APB bridge address

CONFIG_APB_HADDR

  Selects the MSB adddress (HADDR[31:20]) of the APB bridge. Should be

  kept at 800 for software compatibility.

AHB monitor

CONFIG_AHB_MON

  Say Y to enable the AHB bus monitor. The monitor will check for

  illegal AHB transactions during simulation. It has no impact on

  synthesis.

Report AHB errors

CONFIG_AHB_MONERR

  Print out detected AHB violations on console.

Report AHB warnings

CONFIG_AHB_MONWAR

  Print out detected AHB warnings on console.

DSU enable

CONFIG_DSU_UART

  Say Y to enable the AHB uart (serial-to-AHB). This is the most

  commonly used debug communication link.

JTAG Enable

CONFIG_DSU_JTAG

  Say Y to enable the JTAG debug link (JTAG-to-AHB). Debugging is done

  with GRMON through the boards JTAG chain at speed of 300 kbits/s.

  Supported JTAG cables are Xilinx Parallel Cable III and IV.

Ethernet DSU enable

CONFIG_DSU_ETH

  Say Y to enable the Ethernet Debug Communication Link (EDCL). The link

  provides a DSU gateway between ethernet and the AHB bus. Debugging is

  done at 10 or 100 Mbit/s, using the GRMON debug monitor. You must

  enable the GRETH Ethernet MAC for this option to become active.

Size of EDCL trace buffer

CONFIG_DSU_ETHSZ1

  Select the buffer size (in kbytes) for the EDCL. 1 or 2 kbyte is

  usually enough, while a larger buffer will increase the transfer rate.

  When operating at 100 Mbit, use a buffer size of at least 8 kbyte for

  maximum throughput.

MSB IP address

CONFIG_DSU_IPMSB

  Set the MSB 16 bits of the IP address of the EDCL.

LSB IP address

CONFIG_DSU_IPLSB

  Set the LSB 16 bits of the IP address of the EDCL.

MSB ethernet address

CONFIG_DSU_ETHMSB

  Set the MSB 24 bits of the ethernet address of the EDCL.

LSB ethernet address

CONFIG_DSU_ETHLSB

  Set the LSB 24 bits of the ethernet address of the EDCL.

Programmable MAC/IP address

CONFIG_DSU_ETH_PROG

  Say Y to make the LSB 4 bits of the EDCL MAC and IP address

  configurable using the ethi.edcladdr inputs.

PROM/SRAM memory controller

CONFIG_SRCTRL

  Say Y here to enable a simple (and small) PROM/SRAM memory controller.

  The controller has a fixed number of waitstates, and is primarily

  intended for FPGA implementations. The RAM data bus is always 32 bits,

  the PROM can be configured to either 8 or 32 bits (hardwired).

8-bit memory support

CONFIG_SRCTRL_8BIT

  If you say Y here, the simple PROM/SRAM memory controller will

  implement 8-bit PROM mode.

PROM waitstates

CONFIG_SRCTRL_PROMWS

  Select the number of waitstates for PROM access.

RAM waitstates

CONFIG_SRCTRL_RAMWS

  Select the number of waitstates for RAM access.

IO waitstates

CONFIG_SRCTRL_IOWS

  Select the number of waitstates for IO access.

Read-modify-write support

CONFIG_SRCTRL_RMW

  Say Y here to perform byte- and half-word writes as a

  read-modify-write sequence. This is necessary if your

  SRAM does not have individual byte enables. If you are

  unsure, it is safe to say Y.

SRAM bank select

CONFIG_SRCTRL_SRBANKS

  Select number of SRAM banks.

SRAM bank size select

CONFIG_SRCTRL_BANKSZ

  Select size of SRAM banks in kBytes.

PROM address bit select

CONFIG_SRCTRL_ROMASEL

  Select address bit for PROM bank decoding.

Leon2 memory controller

CONFIG_MCTRL_LEON2

  Say Y here to enable the LEON2 memory controller. The controller

  can access PROM, I/O, SRAM and SDRAM. The bus width for PROM

  and SRAM is programmable to 8-, 16- or 32-bits.

8-bit memory support

CONFIG_MCTRL_8BIT

  If you say Y here, the PROM/SRAM memory controller will support

  8-bit mode, i.e. operate from 8-bit devices as if they were 32-bit.

  Say N to save a few hundred gates.

16-bit memory support

CONFIG_MCTRL_16BIT

  If you say Y here, the PROM/SRAM memory controller will support

  16-bit mode, i.e. operate from 16-bit devices as if they were 32-bit.

  Say N to save a few hundred gates.

Write strobe feedback

CONFIG_MCTRL_WFB

  If you say Y here, the PROM/SRAM write strobes (WRITEN, WEN) will

  be used to enable the data bus drivers during write cycles. This

  will guarantee that the data is still valid on the rising edge of

  the write strobe. If you say N, the write strobes and the data bus

  drivers will be clocked on the rising edge, potentially creating

  a hold time problem in external memory or I/O. However, in all

  practical cases, there is enough capacitance in the data bus lines

  to keep the value stable for a few (many?) nano-seconds after the

  buffers have been disabled, making it safe to say N and remove a

  combinational path in the netlist that might be difficult to

  analyze.

Write strobe feedback

CONFIG_MCTRL_5CS

  If you say Y here, the 5th (RAMSN[4]) SRAM chip select signal will

  be enabled. If you don't intend to use it, say N and save some gates.

SDRAM controller enable

CONFIG_MCTRL_SDRAM

  Say Y here to enabled the PC100/PC133 SDRAM controller. If you don't

  intend to use SDRAM, say N and save about 1 kgates.

SDRAM controller inverted clock

CONFIG_MCTRL_SDRAM_INVCLK

  If you say Y here, the SDRAM controller output signals will be delayed

  with 1/2 clock in respect to the SDRAM clock. This will allow the used

  of an SDRAM clock which in not strictly in phase with the internal

  clock. This option will limit the SDRAM frequency to 40 - 50 MHz.

  On FPGA targets without SDRAM clock synchronizations through PLL/DLL,

  say Y. On ASIC targets, say N and tell your foundry to balance the

  SDRAM clock output.

SDRAM separate address buses

CONFIG_MCTRL_SDRAM_SEPBUS

  Say Y here if your SDRAM is connected through separate address

  and data buses (SA & SD). This is the case on the GR-CPCI-XC2V6000

  board, but not on the GR-PCI-XC2V3000 or Avnet XCV1500E boards.

64-bit data bus

CONFIG_MCTRL_SDRAM_BUS64

  Say Y here to enable 64-bit SDRAM data bus.

Page burst enable

CONFIG_MCTRL_PAGE

  Say Y here to enable SDRAM page burst operation. This will implement

  read operations using page bursts rather than 8-word bursts and save

  about 500 gates (100 LUTs). Note that not all SDRAM supports page

  burst, so use this option with care.

Programmable page burst enable

CONFIG_MCTRL_PROGPAGE

  Say Y here to enable programmable SDRAM page burst operation. This

  will allow to dynamically enable/disable page burst by setting

  bit 17 in MCFG2.

SDRAM controller enable

CONFIG_SDCTRL

  Say Y here to enabled a 32/64-bit PC133 SDRAM controller.

SDRAM controller inverted clock

CONFIG_SDCTRL_INVCLK

  If you say Y here, the SDRAM clock will be inverted in respect to the

  system clock and the SDRAM signals. This will limit the SDRAM frequency

  to 50/66 MHz, but has the benefit that you will not need a PLL to

  generate the SDRAM clock. On FPGA targets, say Y. On ASIC targets,

  say N and tell your foundry to balance the SDRAM clock output.

64-bit data bus

CONFIG_SDCTRL_BUS64

  Say Y here to enable 64-bit data bus.

Page burst enable

CONFIG_SDCTRL_PAGE

  Say Y here to enable SDRAM page burst operation. This will implement

  read operations using page bursts rather than 8-word bursts and save

  about 500 gates (100 LUTs). Note that not all SDRAM supports page

  burst, so use this option with care.

Programmable page burst enable

CONFIG_SDCTRL_PROGPAGE

  Say Y here to enable programmable SDRAM page burst operation. This

  will allow to dynamically enable/disable page burst by setting

  bit 17 in MCFG2.

On-chip rom

CONFIG_AHBROM_ENABLE

  Say Y here to add a block on on-chip rom to the AHB bus. The ram

  provides 0-waitstates read access,  burst support, and 8-, 16-

  and 32-bit data size. The rom will be syntheised into block rams

  on Xilinx and Altera FPGA devices, and into gates on ASIC

  technologies. GRLIB includes a utility to automatically create

  the rom VHDL model (ahbrom.vhd) from an ELF file. Refer to the GRLIB

  documentation for details.

On-chip rom address

CONFIG_AHBROM_START

  Set the start address of AHB ROM (HADDR[31:20]). The ROM will occupy

  a 1 Mbyte slot at the selected address. Default is 000, corresponding

  to AHB address 0x00000000. When address 0x0 is selected, the rom area

  of any other memory controller is set to 0x10000000 to avoid conflicts.

Enable pipeline register for on-chip rom

CONFIG_AHBROM_PIPE

  Say Y here to add a data pipeline register to the on-chip rom.

  This should be done when the rom is implemenented in (ASIC) gates,

  or in logic cells on FPGAs. Do not use this option when the rom is

  implemented in block rams. If enabled, the rom will operate with

  one waitstate.

On-chip ram

CONFIG_AHBRAM_ENABLE

  Say Y here to add a block on on-chip ram to the AHB bus. The ram

  provides 0-waitstates read access and 0/1 waitstates write access.

  All AHB burst types are supported, as well as 8-, 16- and 32-bit

  data size.

On-chip ram size

CONFIG_AHBRAM_SZ1

  Set the size of the on-chip AHB ram. The ram is infered/instantiated

  as four byte-wide ram slices to allow byte and half-word write

  accesses. It is therefore essential that the target package can

  infer byte-wide rams. This is currently supported on the generic,

  virtex, virtex2, proasic and axellerator targets.

On-chip ram address

CONFIG_AHBRAM_START

  Set the start address of AHB RAM (HADDR[31:20]). The RAM will occupy

  a 1 Mbyte slot at the selected address. Default is A00, corresponding

  to AHB address 0xA0000000.

Gaisler Ethernet MAC enable

CONFIG_GRETH_ENABLE

  Say Y here to enable the Gaisler Research Ethernet MAC . The MAC has

  one AHB master interface to read and write packets to memory, and one

  APB slave interface for accessing the control registers.

Gaisler Ethernet 1G MAC enable

CONFIG_GRETH_GIGA

  Say Y here to enable the Gaisler Research 1000 Mbit Ethernet MAC .

  The 1G MAC is only available in the commercial version of GRLIB,

  so do NOT enable it if you are using the GPL version.

CONFIG_GRETH_FIFO4

  Set the depth of the receive and transmit FIFOs in the MAC core.

  The MAC core will perform AHB burst read/writes with half the

  size of the FIFO depth.

CAN interface enable

CONFIG_CAN_ENABLE

  Say Y here to enable the CAN interace from OpenCores. The core has one

  AHB slave interface for accessing the control registers. The CAN core

  ir register-compatible with the SAJ1000 core from Philips.

CAN register address

CONFIG_CANIO

  The control registers of the CAN core occupy 4 kbyte, and are

  mapped in the AHB bus I/O area (0xFFF00000 - 0xFFFFF000). This setting

  defines at which address in the I/O area the registers appear (HADDR[19:8]).

CAN interrupt

CONFIG_CANIRQ

  Defines which interrupt number the CAN core will generate.

CAN loob-back testing

CONFIG_CANLOOP

  If you say Y here, the receiver and trasmitter of the CAN core will

  be connected together in a loop-back fashion. This will make it

  possible to perform loop-back test, but not data will be sent

  or received from the outside. ONLY for testing!

CAN Synchronous reset

CONFIG_CAN_SYNCRST

  If you say Y here, the CAN core will be implemented with

  synchronous reset rather than asynchronous. This is needed

  when the target library does not implement registers with

  async reset. Unless you know what you are doing, say N.

CAN FT memories

CONFIG_CAN_FT

  If you say Y here, the CAN FIFOs will be implemented using

  SEU protected RAM blocks. Only applicable to the FT version

  of grlib.

Spacewire link

CONFIG_SPW_ENABLE

  Say Y here to enable one or more Spacewire serial links. The links

  are based on the GRSPW core from Gaisler Research.

Number of spacewire links

CONFIG_SPW_NUM

  Select the number of links to implement. Each link will be a

  separate AHB master and APB slave for configuration.

AHB FIFO depth

CONFIG_SPW_AHBFIFO4

  Select the AHB FIFO depth (in 32-bit words).

RX FIFO depth

CONFIG_SPW_RXFIFO16

  Select the receiver FIFO depth (in bytes).

RMAP protocol

CONFIG_SPW_RMAP

  Enable hardware support for the RMAP protocol (draft C).

RMAP Buffer depth

CONFIG_SPW_RMAPBUF2

  Select the size of the RMAP buffer (in bytes).

RMAP CRC

CONFIG_SPW_RMAPCRC

  Enable hardware calculation of the RMAP CRC checksum

Netlists

CONFIG_SPW_NETLIST

  Use the netlist version of GRSPWC. This option is required if

  you have not licensed the source code of the Spacewire core.

  Currently only supported for Virtex and Axcelerator FPGAs.

  The AHB/RX FIFO sizes should be set to 16 word/byte, and the

  RMAP should be disabled.

Spacewire FT

CONFIG_SPW_FT

  Say Y here to implement the Spacewire block rams with fault-tolerance

  against SEU errors.

Spacewire core

CONFIG_SPW_GRSPW1

  Select to use GRSPW1 core or GRSPW2 core.

PCI interface type

CONFIG_PCI_SIMPLE_TARGET

  The target-only PCI interface provides a simple target interface

  without fifos. It is small and robust, and is suitable to be used

  for DSU communications via PCI.

PCI interface type

CONFIG_PCI_MASTER_TARGET

  The master-target PCI interface provides a high-performance 32-bit

  PCI interface with configurable FIFOs and optional DMA channel.