OpenCores
URL https://opencores.org/ocsvn/mips_enhanced/mips_enhanced/trunk

Subversion Repositories mips_enhanced

[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [designs/] [leon3-gr-cpci-xc4v/] [Makefile] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 dimamali
include .config
2
GRLIB=../..
3
TOP=leon3mp
4
BOARD=gr-cpci-xc4v
5
include $(GRLIB)/boards/$(BOARD)/Makefile.inc
6
DEVICE=$(PART)-$(PACKAGE)$(SPEED)
7
UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
8
QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
9
EFFORT=high
10
XSTOPT=
11
ISEMAPOPT=-timing
12
VHDLSYNFILES=config.vhd leon3mp.vhd
13
VHDLSIMFILES=testbench.vhd
14
SIMTOP=testbench
15
SDCFILE=default.sdc
16
#SDCFILE=$(GRLIB)/boards/$(BOARD)/default.sdc
17
BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut
18
CLEAN=soft-clean
19
SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
20
 
21
TECHLIBS = unisim
22
LIBSKIP = core1553bbc core1553brm core1553brt gr1553 \
23
        tmtc openchip hynix cypress ihp gleichmann usbhc fmf spansion gsi
24
DIRSKIP = b1553 leon2 leon2ft leon3ft crypto satcan ddr usb ata grusbhc haps \
25
        slink ascs coremp7 ac97
26
 
27
include $(GRLIB)/bin/Makefile
28
include $(GRLIB)/software/leon3/Makefile
29
 
30
 
31
##################  project specific targets ##########################

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.