URL https://opencores.org/ocsvn/mips_enhanced/mips_enhanced/trunk

Subversion Repositories mips_enhanced

[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [designs/] [leon3-gr-cpci-xc4v/] [leon3mp.h] - Blame information for rev 2

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#include "config.h"
#if defined CONFIG_SYN_INFERRED
#define CONFIG_SYN_TECH inferred
#elif defined CONFIG_SYN_RHUMC
#define CONFIG_SYN_TECH rhumc
#elif defined CONFIG_SYN_ATC18
#define CONFIG_SYN_TECH atc18
#elif defined CONFIG_SYN_AXCEL
#define CONFIG_SYN_TECH axcel
#elif defined CONFIG_SYN_PROASICPLUS
#define CONFIG_SYN_TECH proasic
#elif defined CONFIG_SYN_PROASIC
#define CONFIG_SYN_TECH proasic
#elif defined CONFIG_SYN_PROASIC3
#define CONFIG_SYN_TECH proasic3
#elif defined CONFIG_SYN_SPARTAN2
#define CONFIG_SYN_TECH virtex
#elif defined CONFIG_SYN_VIRTEX
#define CONFIG_SYN_TECH virtex
#elif defined CONFIG_SYN_VIRTEXE
#define CONFIG_SYN_TECH virtex
#elif defined CONFIG_SYN_SPARTAN3
#define CONFIG_SYN_TECH spartan3
#elif defined CONFIG_SYN_VIRTEX2
#define CONFIG_SYN_TECH virtex2
#else
#error "unknown target technology"
#endif
 
#if defined CONFIG_SYN_INFER_RAM
#define CFG_RAM_TECH inferred
#elif defined CONFIG_MEM_RHUMC
#define CFG_RAM_TECH rhumc
#elif defined CONFIG_MEM_VIRAGE
#define CFG_RAM_TECH memvirage
#else
#define CFG_RAM_TECH CONFIG_SYN_TECH
#endif
 
#if defined CONFIG_SYN_INFER_PADS
#define CFG_PAD_TECH inferred
#else
#define CFG_PAD_TECH CONFIG_SYN_TECH
#endif
 
#if defined CONFIG_CLK_ALTDLL
#define CFG_CLK_TECH stratix
#elif defined CONFIG_CLK_HCLKBUF
#define CFG_CLK_TECH axcel
#elif defined CONFIG_CLK_CLKDLL
#define CFG_CLK_TECH virtex
#elif defined CONFIG_CLK_DCM
#define CFG_CLK_TECH virtex2
#else
#define CFG_CLK_TECH inferred
#endif
 
#ifndef CONFIG_CLK_MUL
#define CONFIG_CLK_MUL 2
#endif
 
#ifndef CONFIG_CLK_DIV
#define CONFIG_CLK_DIV 2
#endif
 
#ifndef CONFIG_PCI_CLKDLL
#define CONFIG_PCI_CLKDLL 0
#endif
 
#ifndef CONFIG_PCI_SYSCLK
#define CONFIG_PCI_SYSCLK 0
#endif
 
#ifdef CONFIG_IU_V8MULDIV
#ifdef CONFIG_IU_MUL_LATENCY_4
#define CFG_IU_V8 1
#else
#define CFG_IU_V8 2
#endif
#else
#define CFG_IU_V8 0
#endif
#ifndef CONFIG_PWD
#define CONFIG_PWD 0
#endif
 
#ifndef CONFIG_IU_MUL_MAC
#define CONFIG_IU_MUL_MAC 0
#endif
 
#ifndef CONFIG_IU_SVT
#define CONFIG_IU_SVT 0
#endif
 
#if defined CONFIG_FPU_GRFPU
#define CONFIG_FPU 1
#elif defined CONFIG_FPU_MEIKO
#define CONFIG_FPU 2
#else
#define CONFIG_FPU 0
#endif
 
#ifndef CONFIG_ICACHE_ENABLE
#define CONFIG_ICACHE_ENABLE 0
#endif
 
#if defined CONFIG_ICACHE_ASSO1
#define CFG_IU_ISETS 1
#elif defined CONFIG_ICACHE_ASSO2
#define CFG_IU_ISETS 2
#elif defined CONFIG_ICACHE_ASSO3
#define CFG_IU_ISETS 3
#elif defined CONFIG_ICACHE_ASSO4
#define CFG_IU_ISETS 4
#else
#define CFG_IU_ISETS 1
#endif
 
#if defined CONFIG_ICACHE_SZ1
#define CFG_ICACHE_SZ 1
#elif defined CONFIG_ICACHE_SZ2
#define CFG_ICACHE_SZ 2
#elif defined CONFIG_ICACHE_SZ4
#define CFG_ICACHE_SZ 4
#elif defined CONFIG_ICACHE_SZ8
#define CFG_ICACHE_SZ 8
#elif defined CONFIG_ICACHE_SZ16
#define CFG_ICACHE_SZ 16
#elif defined CONFIG_ICACHE_SZ32
#define CFG_ICACHE_SZ 32
#elif defined CONFIG_ICACHE_SZ64
#define CFG_ICACHE_SZ 64
#elif defined CONFIG_ICACHE_SZ128
#define CFG_ICACHE_SZ 128
#elif defined CONFIG_ICACHE_SZ256
#define CFG_ICACHE_SZ 256
#else
#define CFG_ICACHE_SZ 1
#endif
 
#ifdef CONFIG_ICACHE_LZ16
#define CFG_ILINE_SZ 4
#else
#define CFG_ILINE_SZ 8
#endif
 
#if defined CONFIG_ICACHE_ALGORND
#define CFG_ICACHE_ALGORND 2
#elif defined CONFIG_ICACHE_ALGOLRR
#define CFG_ICACHE_ALGORND 1
#else
#define CFG_ICACHE_ALGORND 0
#endif
 
#ifndef CONFIG_ICACHE_LOCK
#define CONFIG_ICACHE_LOCK 0
#endif
 
#ifndef CONFIG_ICACHE_LRAM
#define CONFIG_ICACHE_LRAM 0
#endif
 
#ifndef CONFIG_ICACHE_LRSTART
#define CONFIG_ICACHE_LRSTART 8E
#endif
 
#if defined CONFIG_ICACHE_LRAM_SZ2
#define CFG_ILRAM_SIZE 2
#elif defined CONFIG_ICACHE_LRAM_SZ4
#define CFG_ILRAM_SIZE 4
#elif defined CONFIG_ICACHE_LRAM_SZ8
#define CFG_ILRAM_SIZE 8
#elif defined CONFIG_ICACHE_LRAM_SZ16
#define CFG_ILRAM_SIZE 16
#elif defined CONFIG_ICACHE_LRAM_SZ32
#define CFG_ILRAM_SIZE 32
#elif defined CONFIG_ICACHE_LRAM_SZ64
#define CFG_ILRAM_SIZE 64
#elif defined CONFIG_ICACHE_LRAM_SZ128
#define CFG_ILRAM_SIZE 128
#elif defined CONFIG_ICACHE_LRAM_SZ256
#define CFG_ILRAM_SIZE 256
#else
#define CFG_ILRAM_SIZE 1
#endif
 
 
#ifndef CONFIG_DCACHE_ENABLE
#define CONFIG_DCACHE_ENABLE 0
#endif
 
#if defined CONFIG_DCACHE_ASSO1
#define CFG_IU_DSETS 1
#elif defined CONFIG_DCACHE_ASSO2
#define CFG_IU_DSETS 2
#elif defined CONFIG_DCACHE_ASSO3
#define CFG_IU_DSETS 3
#elif defined CONFIG_DCACHE_ASSO4
#define CFG_IU_DSETS 4
#else
#define CFG_IU_DSETS 1
#endif
 
#if defined CONFIG_DCACHE_SZ1
#define CFG_DCACHE_SZ 1
#elif defined CONFIG_DCACHE_SZ2
#define CFG_DCACHE_SZ 2
#elif defined CONFIG_DCACHE_SZ4
#define CFG_DCACHE_SZ 4
#elif defined CONFIG_DCACHE_SZ8
#define CFG_DCACHE_SZ 8
#elif defined CONFIG_DCACHE_SZ16
#define CFG_DCACHE_SZ 16
#elif defined CONFIG_DCACHE_SZ32
#define CFG_DCACHE_SZ 32
#elif defined CONFIG_DCACHE_SZ64
#define CFG_DCACHE_SZ 64
#elif defined CONFIG_DCACHE_SZ128
#define CFG_DCACHE_SZ 128
#elif defined CONFIG_DCACHE_SZ256
#define CFG_DCACHE_SZ 256
#else
#define CFG_DCACHE_SZ 1
#endif
 
#ifdef CONFIG_DCACHE_LZ16
#define CFG_DLINE_SZ 4
#else
#define CFG_DLINE_SZ 8
#endif
 
#if defined CONFIG_DCACHE_ALGORND
#define CFG_DCACHE_ALGORND 2
#elif defined CONFIG_DCACHE_ALGOLRR
#define CFG_DCACHE_ALGORND 1
#else
#define CFG_DCACHE_ALGORND 0
#endif
 
#ifndef CONFIG_DCACHE_LOCK
#define CONFIG_DCACHE_LOCK 0
#endif
 
#ifndef CONFIG_DCACHE_SNOOP
#define CONFIG_DCACHE_SNOOP 0
#endif
 
#ifndef CONFIG_DCACHE_LRAM
#define CONFIG_DCACHE_LRAM 0
#endif
 
#ifndef CONFIG_DCACHE_LRSTART
#define CONFIG_DCACHE_LRSTART 8F
#endif
 
#if defined CONFIG_DCACHE_LRAM_SZ2
#define CFG_DLRAM_SIZE 2
#elif defined CONFIG_DCACHE_LRAM_SZ4
#define CFG_DLRAM_SIZE 4
#elif defined CONFIG_DCACHE_LRAM_SZ8
#define CFG_DLRAM_SIZE 8
#elif defined CONFIG_DCACHE_LRAM_SZ16
#define CFG_DLRAM_SIZE 16
#elif defined CONFIG_DCACHE_LRAM_SZ32
#define CFG_DLRAM_SIZE 32
#elif defined CONFIG_DCACHE_LRAM_SZ64
#define CFG_DLRAM_SIZE 64
#elif defined CONFIG_DCACHE_LRAM_SZ128
#define CFG_DLRAM_SIZE 128
#elif defined CONFIG_DCACHE_LRAM_SZ256
#define CFG_DLRAM_SIZE 256
#else
#define CFG_DLRAM_SIZE 1
#endif
 
 
#ifdef CONFIG_MMU_ENABLE
#define CONFIG_MMUEN 1
 
#ifdef CONFIG_MMU_SPLIT
#define CONFIG_TLB_TYPE 0
#endif
#ifdef CONFIG_MMU_COMBINED
#define CONFIG_TLB_TYPE 1
#endif
 
#ifdef CONFIG_MMU_REPARRAY
#define CONFIG_TLB_REP 0
#endif
#ifdef CONFIG_MMU_REPINCREMENT
#define CONFIG_TLB_REP 1
#endif
 
#ifdef CONFIG_MMU_I2 
#define CONFIG_ITLBNUM 2
#endif
#ifdef CONFIG_MMU_I4 
#define CONFIG_ITLBNUM 4
#endif
#ifdef CONFIG_MMU_I8 
#define CONFIG_ITLBNUM 8
#endif
#ifdef CONFIG_MMU_I16 
#define CONFIG_ITLBNUM 16
#endif
#ifdef CONFIG_MMU_I32
#define CONFIG_ITLBNUM 32
#endif
 
#define CONFIG_DTLBNUM 2
#ifdef CONFIG_MMU_D2 
#undef CONFIG_DTLBNUM 
#define CONFIG_DTLBNUM 2
#endif
#ifdef CONFIG_MMU_D4 
#undef CONFIG_DTLBNUM 
#define CONFIG_DTLBNUM 4
#endif
#ifdef CONFIG_MMU_D8 
#undef CONFIG_DTLBNUM 
#define CONFIG_DTLBNUM 8
#endif
#ifdef CONFIG_MMU_D16 
#undef CONFIG_DTLBNUM 
#define CONFIG_DTLBNUM 16
#endif
#ifdef CONFIG_MMU_D32
#undef CONFIG_DTLBNUM 
#define CONFIG_DTLBNUM 32
#endif
 
#else
#define CONFIG_MMUEN 0
#define CONFIG_ITLBNUM 2
#define CONFIG_DTLBNUM 2
#define CONFIG_TLB_TYPE 1
#define CONFIG_TLB_REP 1
#endif
 
 
#ifndef CONFIG_DSU_ENABLE
#define CONFIG_DSU_ENABLE 0
#endif
 
#ifndef CONFIG_DSU_UART
#define CONFIG_DSU_UART 0
#endif
 
#ifndef CONFIG_DSU_JTAG
#define CONFIG_DSU_JTAG 0
#endif
 
#ifndef CONFIG_DSU_ETH
#define CONFIG_DSU_ETH 0
#endif
 
#ifndef CONFIG_DSU_ETH100
#define CONFIG_DSU_ETH100 0
#endif
 
#ifndef CONFIG_DSU_IPMSB
#define CONFIG_DSU_IPMSB C0A8
#endif
 
#ifndef CONFIG_DSU_IPLSB
#define CONFIG_DSU_IPLSB 0033
#endif
 
#ifndef CONFIG_DSU_ETHMSB
#define CONFIG_DSU_ETHMSB 00007A
#endif
 
#ifndef CONFIG_DSU_ETHLSB
#define CONFIG_DSU_ETHLSB CC0001
#endif
 
#ifndef CONFIG_DSU_ETHUDP
#define CONFIG_DSU_ETHUDP 8000
#endif
 
#if defined CONFIG_DSU_ETHSZ1
#define CFG_DSU_ETHB 1
#elif CONFIG_DSU_ETHSZ2
#define CFG_DSU_ETHB 2
#elif CONFIG_DSU_ETHSZ4
#define CFG_DSU_ETHB 4
#elif CONFIG_DSU_ETHSZ8
#define CFG_DSU_ETHB 8
#elif CONFIG_DSU_ETHSZ16
#define CFG_DSU_ETHB 16
#elif CONFIG_DSU_ETHSZ32
#define CFG_DSU_ETHB 32
#else
#define CFG_DSU_ETHB 1
#endif
 
#if defined CONFIG_DSU_ITRACESZ1
#define CFG_DSU_ITB 1
#elif CONFIG_DSU_ITRACESZ2
#define CFG_DSU_ITB 2
#elif CONFIG_DSU_ITRACESZ4
#define CFG_DSU_ITB 4
#elif CONFIG_DSU_ITRACESZ8
#define CFG_DSU_ITB 8
#elif CONFIG_DSU_ITRACESZ16
#define CFG_DSU_ITB 16
#else
#define CFG_DSU_ITB 0
#endif
 
#if defined CONFIG_DSU_ATRACESZ1
#define CFG_DSU_ATB 1
#elif CONFIG_DSU_ATRACESZ2
#define CFG_DSU_ATB 2
#elif CONFIG_DSU_ATRACESZ4
#define CFG_DSU_ATB 4
#elif CONFIG_DSU_ATRACESZ8
#define CFG_DSU_ATB 8
#elif CONFIG_DSU_ATRACESZ16
#define CFG_DSU_ATB 16
#else
#define CFG_DSU_ATB 0
#endif
 
#ifndef CONFIG_AHB_SPLIT
#define CONFIG_AHB_SPLIT 0
#endif
 
#ifndef CONFIG_AHB_RROBIN
#define CONFIG_AHB_RROBIN 0
#endif
 
#ifndef CONFIG_AHB_IOADDR
#define CONFIG_AHB_IOADDR FFF
#endif
 
#ifndef CONFIG_APB_HADDR
#define CONFIG_APB_HADDR 800
#endif
 
#if defined CONFIG_MCTRL_SMALL
#define CFG_MCTRL_TYPE 1
#ifdef CONFIG_MCTRL_SDRAM
#define CONFIG_MCTRL_SDRAM_SEPBUS 1
#endif
#elif defined CONFIG_MCTRL_LEON2
#define CFG_MCTRL_TYPE 2
#else
#define CFG_MCTRL_TYPE 0
#ifdef CONFIG_MCTRL_SDRAM
#define CONFIG_MCTRL_SDRAM_SEPBUS 1
#endif
#endif
 
#ifndef CONFIG_MCTRL_PROMWS
#define CONFIG_MCTRL_PROMWS 0
#endif
 
#ifndef CONFIG_MCTRL_RAMWS
#define CONFIG_MCTRL_RAMWS 0
#endif
 
#ifndef CONFIG_MCTRL_RMW
#define CONFIG_MCTRL_RMW 0
#endif
 
#ifndef CONFIG_MCTRL_SDRAM
#define CONFIG_MCTRL_SDRAM 0
#endif
 
#ifndef CONFIG_MCTRL_SDRAM_SEPBUS
#define CONFIG_MCTRL_SDRAM_SEPBUS 0
#endif
 
#ifndef CONFIG_MCTRL_SDRAM_INVCLK
#define CONFIG_MCTRL_SDRAM_INVCLK 0
#endif
 
#ifndef CONFIG_MCTRL_SDRAM_BUS64
#define CONFIG_MCTRL_SDRAM_BUS64 0
#endif
 
#ifndef CONFIG_AHBROM_ENABLE
#define CONFIG_AHBROM_ENABLE 0
#endif
 
#ifndef CONFIG_AHBROM_START
#define CONFIG_AHBROM_START 000
#endif
 
#ifndef CONFIG_AHBROM_PIPE
#define CONFIG_AHBROM_PIPE 0
#endif
 
#if (CONFIG_AHBROM_START == 0) && (CONFIG_AHBROM_ENABLE == 1)
#define CONFIG_ROM_START 100
#else
#define CONFIG_ROM_START 000
#endif
 
#ifndef CONFIG_AHBRAM_ENABLE
#define CONFIG_AHBRAM_ENABLE 0
#endif
 
#ifndef CONFIG_AHBRAM_START
#define CONFIG_AHBRAM_START A00
#endif
 
#if defined CONFIG_AHBRAM_SZ1
#define CFG_AHBRAMSZ 1
#elif CONFIG_AHBRAM_SZ2
#define CFG_AHBRAMSZ 2
#elif CONFIG_AHBRAM_SZ4
#define CFG_AHBRAMSZ 4
#elif CONFIG_AHBRAM_SZ8
#define CFG_AHBRAMSZ 8
#elif CONFIG_AHBRAM_SZ16
#define CFG_AHBRAMSZ 16
#elif CONFIG_AHBRAM_SZ32
#define CFG_AHBRAMSZ 32
#elif CONFIG_AHBRAM_SZ64
#define CFG_AHBRAMSZ 64
#else
#define CFG_AHBRAMSZ 1
#endif
 
#ifndef CONFIG_AHBRAM_START
#define CONFIG_AHBRAM_START 0
#endif
 
#ifndef CONFIG_ETH_ENABLE
#define CONFIG_ETH_ENABLE 0
#endif
 
#ifndef CONFIG_ETH_START
#define CONFIG_ETH_START B00
#endif
 
#if defined CONFIG_PCI_SIMPLE_TARGET
#define CFG_PCITYPE 1
#elif defined CONFIG_PCI_MASTER_TARGET
#define CFG_PCITYPE 2
#elif defined CONFIG_PCI_MASTER_TARGET_DMA
#define CFG_PCITYPE 3
#else
#define CFG_PCITYPE 0
#endif
 
#ifndef CONFIG_PCI_VENDORID
#define CONFIG_PCI_VENDORID 0
#endif
 
#ifndef CONFIG_PCI_DEVICEID
#define CONFIG_PCI_DEVICEID 0
#endif
 
#ifndef CONFIG_PCI_REVID
#define CONFIG_PCI_REVID 0
#endif
 
#if defined CONFIG_PCI_FIFO16
#define CFG_PCIFIFO 16
#elif defined CONFIG_PCI_FIFO32
#define CFG_PCIFIFO 32
#elif defined CONFIG_PCI_FIFO64
#define CFG_PCIFIFO 64
#elif defined CONFIG_PCI_FIFO128
#define CFG_PCIFIFO 128
#elif defined CONFIG_PCI_FIFO256
#define CFG_PCIFIFO 256
#else
#define CFG_PCIFIFO 8
#endif
 
#ifndef CONFIG_PCI_ARBITER_APB
#define CONFIG_PCI_ARBITER_APB 0
#endif
 
#ifndef CONFIG_PCI_ARBITER
#define CONFIG_PCI_ARBITER 0
#endif
 
#ifndef CONFIG_PCI_TRACE
#define CONFIG_PCI_TRACE 0
#endif
 
#if defined CONFIG_PCI_TRACE512
#define CFG_PCI_TRACEBUF 512
#elif defined CONFIG_PCI_TRACE1024
#define CFG_PCI_TRACEBUF 1024
#elif defined CONFIG_PCI_TRACE2048
#define CFG_PCI_TRACEBUF 2048
#elif defined CONFIG_PCI_TRACE4096
#define CFG_PCI_TRACEBUF 4096
#else
#define CFG_PCI_TRACEBUF 256
#endif
 
#ifndef CONFIG_UART1_ENABLE
#define CONFIG_UART1_ENABLE 0
#endif
 
#if defined CONFIG_UA1_FIFO1
#define CFG_UA1_FIFO 1
#elif defined CONFIG_UA1_FIFO2
#define CFG_UA1_FIFO 2
#elif defined CONFIG_UA1_FIFO4
#define CFG_UA1_FIFO 4
#elif defined CONFIG_UA1_FIFO8
#define CFG_UA1_FIFO 8
#elif defined CONFIG_UA1_FIFO16
#define CFG_UA1_FIFO 16
#elif defined CONFIG_UA1_FIFO32
#define CFG_UA1_FIFO 32
#else
#define CFG_UA1_FIFO 1
#endif
 
#ifndef CONFIG_UART2_ENABLE
#define CONFIG_UART2_ENABLE 0
#endif
 
#if defined CONFIG_UA2_FIFO1
#define CFG_UA2_FIFO 1
#elif defined CONFIG_UA2_FIFO2
#define CFG_UA2_FIFO 2
#elif defined CONFIG_UA2_FIFO4
#define CFG_UA2_FIFO 4
#elif defined CONFIG_UA2_FIFO8
#define CFG_UA2_FIFO 8
#elif defined CONFIG_UA2_FIFO16
#define CFG_UA2_FIFO 16
#elif defined CONFIG_UA2_FIFO32
#define CFG_UA2_FIFO 32
#else
#define CFG_UA2_FIFO 1
#endif
 
#ifndef CONFIG_IRQ3_ENABLE
#define CONFIG_IRQ3_ENABLE 0
#endif
 
#ifndef CONFIG_GPT_ENABLE
#define CONFIG_GPT_ENABLE 0
#endif
 
#ifndef CONFIG_GPT_NTIM
#define CONFIG_GPT_NTIM 1
#endif
 
#ifndef CONFIG_GPT_SW
#define CONFIG_GPT_SW 8
#endif
 
#ifndef CONFIG_GPT_TW
#define CONFIG_GPT_TW 8
#endif
 
#ifndef CONFIG_GPT_IRQ
#define CONFIG_GPT_IRQ 8
#endif
 
#ifndef CONFIG_GPT_SEPIRQ
#define CONFIG_GPT_SEPIRQ 0
#endif
 
#ifndef CONFIG_PCI_RESETALL
#define CONFIG_PCI_RESETALL 0
#endif
 
#ifndef CONFIG_IU_DISAS
#define CONFIG_IU_DISAS 0
#endif
 
#ifndef CONFIG_CAN_ENABLE
#define CONFIG_CAN_ENABLE 0
#endif
 
#ifndef CONFIG_CANIO
#define CONFIG_CANIO 0
#endif
 
#ifndef CONFIG_CANIRQ
#define CONFIG_CANIRQ 0
#endif
 
#ifndef CONFIG_CANLOOP
#define CONFIG_CANLOOP 0
#endif
 
#ifndef CONFIG_DEBUG_UART
#define CONFIG_DEBUG_UART 0
#endif
 
#ifdef CONFIG_DEBUG_PC32
#define CFG_DEBUG_PC32 0 
#else
#define CFG_DEBUG_PC32 2
#endif

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Subversion Repositories mips_enhanced

[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [designs/] [leon3-gr-cpci-xc4v/] [leon3mp.h] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	dimamali	`#include "config.h"`
2			`#if defined CONFIG_SYN_INFERRED`
3			`#define CONFIG_SYN_TECH inferred`
4			`#elif defined CONFIG_SYN_RHUMC`
5			`#define CONFIG_SYN_TECH rhumc`
6			`#elif defined CONFIG_SYN_ATC18`
7			`#define CONFIG_SYN_TECH atc18`
8			`#elif defined CONFIG_SYN_AXCEL`
9			`#define CONFIG_SYN_TECH axcel`
10			`#elif defined CONFIG_SYN_PROASICPLUS`
11			`#define CONFIG_SYN_TECH proasic`
12			`#elif defined CONFIG_SYN_PROASIC`
13			`#define CONFIG_SYN_TECH proasic`
14			`#elif defined CONFIG_SYN_PROASIC3`
15			`#define CONFIG_SYN_TECH proasic3`
16			`#elif defined CONFIG_SYN_SPARTAN2`
17			`#define CONFIG_SYN_TECH virtex`
18			`#elif defined CONFIG_SYN_VIRTEX`
19			`#define CONFIG_SYN_TECH virtex`
20			`#elif defined CONFIG_SYN_VIRTEXE`
21			`#define CONFIG_SYN_TECH virtex`
22			`#elif defined CONFIG_SYN_SPARTAN3`
23			`#define CONFIG_SYN_TECH spartan3`
24			`#elif defined CONFIG_SYN_VIRTEX2`
25			`#define CONFIG_SYN_TECH virtex2`
26			`#else`
27			`#error "unknown target technology"`
28			`#endif`
29
30			`#if defined CONFIG_SYN_INFER_RAM`
31			`#define CFG_RAM_TECH inferred`
32			`#elif defined CONFIG_MEM_RHUMC`
33			`#define CFG_RAM_TECH rhumc`
34			`#elif defined CONFIG_MEM_VIRAGE`
35			`#define CFG_RAM_TECH memvirage`
36			`#else`
37			`#define CFG_RAM_TECH CONFIG_SYN_TECH`
38			`#endif`
39
40			`#if defined CONFIG_SYN_INFER_PADS`
41			`#define CFG_PAD_TECH inferred`
42			`#else`
43			`#define CFG_PAD_TECH CONFIG_SYN_TECH`
44			`#endif`
45
46			`#if defined CONFIG_CLK_ALTDLL`
47			`#define CFG_CLK_TECH stratix`
48			`#elif defined CONFIG_CLK_HCLKBUF`
49			`#define CFG_CLK_TECH axcel`
50			`#elif defined CONFIG_CLK_CLKDLL`
51			`#define CFG_CLK_TECH virtex`
52			`#elif defined CONFIG_CLK_DCM`
53			`#define CFG_CLK_TECH virtex2`
54			`#else`
55			`#define CFG_CLK_TECH inferred`
56			`#endif`
57
58			`#ifndef CONFIG_CLK_MUL`
59			`#define CONFIG_CLK_MUL 2`
60			`#endif`
61
62			`#ifndef CONFIG_CLK_DIV`
63			`#define CONFIG_CLK_DIV 2`
64			`#endif`
65
66			`#ifndef CONFIG_PCI_CLKDLL`
67			`#define CONFIG_PCI_CLKDLL 0`
68			`#endif`
69
70			`#ifndef CONFIG_PCI_SYSCLK`
71			`#define CONFIG_PCI_SYSCLK 0`
72			`#endif`
73
74			`#ifdef CONFIG_IU_V8MULDIV`
75			`#ifdef CONFIG_IU_MUL_LATENCY_4`
76			`#define CFG_IU_V8 1`
77			`#else`
78			`#define CFG_IU_V8 2`
79			`#endif`
80			`#else`
81			`#define CFG_IU_V8 0`
82			`#endif`
83			`#ifndef CONFIG_PWD`
84			`#define CONFIG_PWD 0`
85			`#endif`
86
87			`#ifndef CONFIG_IU_MUL_MAC`
88			`#define CONFIG_IU_MUL_MAC 0`
89			`#endif`
90
91			`#ifndef CONFIG_IU_SVT`
92			`#define CONFIG_IU_SVT 0`
93			`#endif`
94
95			`#if defined CONFIG_FPU_GRFPU`
96			`#define CONFIG_FPU 1`
97			`#elif defined CONFIG_FPU_MEIKO`
98			`#define CONFIG_FPU 2`
99			`#else`
100			`#define CONFIG_FPU 0`
101			`#endif`
102
103			`#ifndef CONFIG_ICACHE_ENABLE`
104			`#define CONFIG_ICACHE_ENABLE 0`
105			`#endif`
106
107			`#if defined CONFIG_ICACHE_ASSO1`
108			`#define CFG_IU_ISETS 1`
109			`#elif defined CONFIG_ICACHE_ASSO2`
110			`#define CFG_IU_ISETS 2`
111			`#elif defined CONFIG_ICACHE_ASSO3`
112			`#define CFG_IU_ISETS 3`
113			`#elif defined CONFIG_ICACHE_ASSO4`
114			`#define CFG_IU_ISETS 4`
115			`#else`
116			`#define CFG_IU_ISETS 1`
117			`#endif`
118
119			`#if defined CONFIG_ICACHE_SZ1`
120			`#define CFG_ICACHE_SZ 1`
121			`#elif defined CONFIG_ICACHE_SZ2`
122			`#define CFG_ICACHE_SZ 2`
123			`#elif defined CONFIG_ICACHE_SZ4`
124			`#define CFG_ICACHE_SZ 4`
125			`#elif defined CONFIG_ICACHE_SZ8`
126			`#define CFG_ICACHE_SZ 8`
127			`#elif defined CONFIG_ICACHE_SZ16`
128			`#define CFG_ICACHE_SZ 16`
129			`#elif defined CONFIG_ICACHE_SZ32`
130			`#define CFG_ICACHE_SZ 32`
131			`#elif defined CONFIG_ICACHE_SZ64`
132			`#define CFG_ICACHE_SZ 64`
133			`#elif defined CONFIG_ICACHE_SZ128`
134			`#define CFG_ICACHE_SZ 128`
135			`#elif defined CONFIG_ICACHE_SZ256`
136			`#define CFG_ICACHE_SZ 256`
137			`#else`
138			`#define CFG_ICACHE_SZ 1`
139			`#endif`
140
141			`#ifdef CONFIG_ICACHE_LZ16`
142			`#define CFG_ILINE_SZ 4`
143			`#else`
144			`#define CFG_ILINE_SZ 8`
145			`#endif`
146
147			`#if defined CONFIG_ICACHE_ALGORND`
148			`#define CFG_ICACHE_ALGORND 2`
149			`#elif defined CONFIG_ICACHE_ALGOLRR`
150			`#define CFG_ICACHE_ALGORND 1`
151			`#else`
152			`#define CFG_ICACHE_ALGORND 0`
153			`#endif`
154
155			`#ifndef CONFIG_ICACHE_LOCK`
156			`#define CONFIG_ICACHE_LOCK 0`
157			`#endif`
158
159			`#ifndef CONFIG_ICACHE_LRAM`
160			`#define CONFIG_ICACHE_LRAM 0`
161			`#endif`
162
163			`#ifndef CONFIG_ICACHE_LRSTART`
164			`#define CONFIG_ICACHE_LRSTART 8E`
165			`#endif`
166
167			`#if defined CONFIG_ICACHE_LRAM_SZ2`
168			`#define CFG_ILRAM_SIZE 2`
169			`#elif defined CONFIG_ICACHE_LRAM_SZ4`
170			`#define CFG_ILRAM_SIZE 4`
171			`#elif defined CONFIG_ICACHE_LRAM_SZ8`
172			`#define CFG_ILRAM_SIZE 8`
173			`#elif defined CONFIG_ICACHE_LRAM_SZ16`
174			`#define CFG_ILRAM_SIZE 16`
175			`#elif defined CONFIG_ICACHE_LRAM_SZ32`
176			`#define CFG_ILRAM_SIZE 32`
177			`#elif defined CONFIG_ICACHE_LRAM_SZ64`
178			`#define CFG_ILRAM_SIZE 64`
179			`#elif defined CONFIG_ICACHE_LRAM_SZ128`
180			`#define CFG_ILRAM_SIZE 128`
181			`#elif defined CONFIG_ICACHE_LRAM_SZ256`
182			`#define CFG_ILRAM_SIZE 256`
183			`#else`
184			`#define CFG_ILRAM_SIZE 1`
185			`#endif`
186
187
188			`#ifndef CONFIG_DCACHE_ENABLE`
189			`#define CONFIG_DCACHE_ENABLE 0`
190			`#endif`
191
192			`#if defined CONFIG_DCACHE_ASSO1`
193			`#define CFG_IU_DSETS 1`
194			`#elif defined CONFIG_DCACHE_ASSO2`
195			`#define CFG_IU_DSETS 2`
196			`#elif defined CONFIG_DCACHE_ASSO3`
197			`#define CFG_IU_DSETS 3`
198			`#elif defined CONFIG_DCACHE_ASSO4`
199			`#define CFG_IU_DSETS 4`
200			`#else`
201			`#define CFG_IU_DSETS 1`
202			`#endif`
203
204			`#if defined CONFIG_DCACHE_SZ1`
205			`#define CFG_DCACHE_SZ 1`
206			`#elif defined CONFIG_DCACHE_SZ2`
207			`#define CFG_DCACHE_SZ 2`
208			`#elif defined CONFIG_DCACHE_SZ4`
209			`#define CFG_DCACHE_SZ 4`
210			`#elif defined CONFIG_DCACHE_SZ8`
211			`#define CFG_DCACHE_SZ 8`
212			`#elif defined CONFIG_DCACHE_SZ16`
213			`#define CFG_DCACHE_SZ 16`
214			`#elif defined CONFIG_DCACHE_SZ32`
215			`#define CFG_DCACHE_SZ 32`
216			`#elif defined CONFIG_DCACHE_SZ64`
217			`#define CFG_DCACHE_SZ 64`
218			`#elif defined CONFIG_DCACHE_SZ128`
219			`#define CFG_DCACHE_SZ 128`
220			`#elif defined CONFIG_DCACHE_SZ256`
221			`#define CFG_DCACHE_SZ 256`
222			`#else`
223			`#define CFG_DCACHE_SZ 1`
224			`#endif`
225
226			`#ifdef CONFIG_DCACHE_LZ16`
227			`#define CFG_DLINE_SZ 4`
228			`#else`
229			`#define CFG_DLINE_SZ 8`
230			`#endif`
231
232			`#if defined CONFIG_DCACHE_ALGORND`
233			`#define CFG_DCACHE_ALGORND 2`
234			`#elif defined CONFIG_DCACHE_ALGOLRR`
235			`#define CFG_DCACHE_ALGORND 1`
236			`#else`
237			`#define CFG_DCACHE_ALGORND 0`
238			`#endif`
239
240			`#ifndef CONFIG_DCACHE_LOCK`
241			`#define CONFIG_DCACHE_LOCK 0`
242			`#endif`
243
244			`#ifndef CONFIG_DCACHE_SNOOP`
245			`#define CONFIG_DCACHE_SNOOP 0`
246			`#endif`
247
248			`#ifndef CONFIG_DCACHE_LRAM`
249			`#define CONFIG_DCACHE_LRAM 0`
250			`#endif`
251
252			`#ifndef CONFIG_DCACHE_LRSTART`
253			`#define CONFIG_DCACHE_LRSTART 8F`
254			`#endif`
255
256			`#if defined CONFIG_DCACHE_LRAM_SZ2`
257			`#define CFG_DLRAM_SIZE 2`
258			`#elif defined CONFIG_DCACHE_LRAM_SZ4`
259			`#define CFG_DLRAM_SIZE 4`
260			`#elif defined CONFIG_DCACHE_LRAM_SZ8`
261			`#define CFG_DLRAM_SIZE 8`
262			`#elif defined CONFIG_DCACHE_LRAM_SZ16`
263			`#define CFG_DLRAM_SIZE 16`
264			`#elif defined CONFIG_DCACHE_LRAM_SZ32`
265			`#define CFG_DLRAM_SIZE 32`
266			`#elif defined CONFIG_DCACHE_LRAM_SZ64`
267			`#define CFG_DLRAM_SIZE 64`
268			`#elif defined CONFIG_DCACHE_LRAM_SZ128`
269			`#define CFG_DLRAM_SIZE 128`
270			`#elif defined CONFIG_DCACHE_LRAM_SZ256`
271			`#define CFG_DLRAM_SIZE 256`
272			`#else`
273			`#define CFG_DLRAM_SIZE 1`
274			`#endif`
275
276
277			`#ifdef CONFIG_MMU_ENABLE`
278			`#define CONFIG_MMUEN 1`
279
280			`#ifdef CONFIG_MMU_SPLIT`
281			`#define CONFIG_TLB_TYPE 0`
282			`#endif`
283			`#ifdef CONFIG_MMU_COMBINED`
284			`#define CONFIG_TLB_TYPE 1`
285			`#endif`
286
287			`#ifdef CONFIG_MMU_REPARRAY`
288			`#define CONFIG_TLB_REP 0`
289			`#endif`
290			`#ifdef CONFIG_MMU_REPINCREMENT`
291			`#define CONFIG_TLB_REP 1`
292			`#endif`
293
294			`#ifdef CONFIG_MMU_I2`
295			`#define CONFIG_ITLBNUM 2`
296			`#endif`
297			`#ifdef CONFIG_MMU_I4`
298			`#define CONFIG_ITLBNUM 4`
299			`#endif`
300			`#ifdef CONFIG_MMU_I8`
301			`#define CONFIG_ITLBNUM 8`
302			`#endif`
303			`#ifdef CONFIG_MMU_I16`
304			`#define CONFIG_ITLBNUM 16`
305			`#endif`
306			`#ifdef CONFIG_MMU_I32`
307			`#define CONFIG_ITLBNUM 32`
308			`#endif`
309
310			`#define CONFIG_DTLBNUM 2`
311			`#ifdef CONFIG_MMU_D2`
312			`#undef CONFIG_DTLBNUM`
313			`#define CONFIG_DTLBNUM 2`
314			`#endif`
315			`#ifdef CONFIG_MMU_D4`
316			`#undef CONFIG_DTLBNUM`
317			`#define CONFIG_DTLBNUM 4`
318			`#endif`
319			`#ifdef CONFIG_MMU_D8`
320			`#undef CONFIG_DTLBNUM`
321			`#define CONFIG_DTLBNUM 8`
322			`#endif`
323			`#ifdef CONFIG_MMU_D16`
324			`#undef CONFIG_DTLBNUM`
325			`#define CONFIG_DTLBNUM 16`
326			`#endif`
327			`#ifdef CONFIG_MMU_D32`
328			`#undef CONFIG_DTLBNUM`
329			`#define CONFIG_DTLBNUM 32`
330			`#endif`
331
332			`#else`
333			`#define CONFIG_MMUEN 0`
334			`#define CONFIG_ITLBNUM 2`
335			`#define CONFIG_DTLBNUM 2`
336			`#define CONFIG_TLB_TYPE 1`
337			`#define CONFIG_TLB_REP 1`
338			`#endif`
339
340
341			`#ifndef CONFIG_DSU_ENABLE`
342			`#define CONFIG_DSU_ENABLE 0`
343			`#endif`
344
345			`#ifndef CONFIG_DSU_UART`
346			`#define CONFIG_DSU_UART 0`
347			`#endif`
348
349			`#ifndef CONFIG_DSU_JTAG`
350			`#define CONFIG_DSU_JTAG 0`
351			`#endif`
352
353			`#ifndef CONFIG_DSU_ETH`
354			`#define CONFIG_DSU_ETH 0`
355			`#endif`
356
357			`#ifndef CONFIG_DSU_ETH100`
358			`#define CONFIG_DSU_ETH100 0`
359			`#endif`
360
361			`#ifndef CONFIG_DSU_IPMSB`
362			`#define CONFIG_DSU_IPMSB C0A8`
363			`#endif`
364
365			`#ifndef CONFIG_DSU_IPLSB`
366			`#define CONFIG_DSU_IPLSB 0033`
367			`#endif`
368
369			`#ifndef CONFIG_DSU_ETHMSB`
370			`#define CONFIG_DSU_ETHMSB 00007A`
371			`#endif`
372
373			`#ifndef CONFIG_DSU_ETHLSB`
374			`#define CONFIG_DSU_ETHLSB CC0001`
375			`#endif`
376
377			`#ifndef CONFIG_DSU_ETHUDP`
378			`#define CONFIG_DSU_ETHUDP 8000`
379			`#endif`
380
381			`#if defined CONFIG_DSU_ETHSZ1`
382			`#define CFG_DSU_ETHB 1`
383			`#elif CONFIG_DSU_ETHSZ2`
384			`#define CFG_DSU_ETHB 2`
385			`#elif CONFIG_DSU_ETHSZ4`
386			`#define CFG_DSU_ETHB 4`
387			`#elif CONFIG_DSU_ETHSZ8`
388			`#define CFG_DSU_ETHB 8`
389			`#elif CONFIG_DSU_ETHSZ16`
390			`#define CFG_DSU_ETHB 16`
391			`#elif CONFIG_DSU_ETHSZ32`
392			`#define CFG_DSU_ETHB 32`
393			`#else`
394			`#define CFG_DSU_ETHB 1`
395			`#endif`
396
397			`#if defined CONFIG_DSU_ITRACESZ1`
398			`#define CFG_DSU_ITB 1`
399			`#elif CONFIG_DSU_ITRACESZ2`
400			`#define CFG_DSU_ITB 2`
401			`#elif CONFIG_DSU_ITRACESZ4`
402			`#define CFG_DSU_ITB 4`
403			`#elif CONFIG_DSU_ITRACESZ8`
404			`#define CFG_DSU_ITB 8`
405			`#elif CONFIG_DSU_ITRACESZ16`
406			`#define CFG_DSU_ITB 16`
407			`#else`
408			`#define CFG_DSU_ITB 0`
409			`#endif`
410
411			`#if defined CONFIG_DSU_ATRACESZ1`
412			`#define CFG_DSU_ATB 1`
413			`#elif CONFIG_DSU_ATRACESZ2`
414			`#define CFG_DSU_ATB 2`
415			`#elif CONFIG_DSU_ATRACESZ4`
416			`#define CFG_DSU_ATB 4`
417			`#elif CONFIG_DSU_ATRACESZ8`
418			`#define CFG_DSU_ATB 8`
419			`#elif CONFIG_DSU_ATRACESZ16`
420			`#define CFG_DSU_ATB 16`
421			`#else`
422			`#define CFG_DSU_ATB 0`
423			`#endif`
424
425			`#ifndef CONFIG_AHB_SPLIT`
426			`#define CONFIG_AHB_SPLIT 0`
427			`#endif`
428
429			`#ifndef CONFIG_AHB_RROBIN`
430			`#define CONFIG_AHB_RROBIN 0`
431			`#endif`
432
433			`#ifndef CONFIG_AHB_IOADDR`
434			`#define CONFIG_AHB_IOADDR FFF`
435			`#endif`
436
437			`#ifndef CONFIG_APB_HADDR`
438			`#define CONFIG_APB_HADDR 800`
439			`#endif`
440
441			`#if defined CONFIG_MCTRL_SMALL`
442			`#define CFG_MCTRL_TYPE 1`
443			`#ifdef CONFIG_MCTRL_SDRAM`
444			`#define CONFIG_MCTRL_SDRAM_SEPBUS 1`
445			`#endif`
446			`#elif defined CONFIG_MCTRL_LEON2`
447			`#define CFG_MCTRL_TYPE 2`
448			`#else`
449			`#define CFG_MCTRL_TYPE 0`
450			`#ifdef CONFIG_MCTRL_SDRAM`
451			`#define CONFIG_MCTRL_SDRAM_SEPBUS 1`
452			`#endif`
453			`#endif`
454
455			`#ifndef CONFIG_MCTRL_PROMWS`
456			`#define CONFIG_MCTRL_PROMWS 0`
457			`#endif`
458
459			`#ifndef CONFIG_MCTRL_RAMWS`
460			`#define CONFIG_MCTRL_RAMWS 0`
461			`#endif`
462
463			`#ifndef CONFIG_MCTRL_RMW`
464			`#define CONFIG_MCTRL_RMW 0`
465			`#endif`
466
467			`#ifndef CONFIG_MCTRL_SDRAM`
468			`#define CONFIG_MCTRL_SDRAM 0`
469			`#endif`
470
471			`#ifndef CONFIG_MCTRL_SDRAM_SEPBUS`
472			`#define CONFIG_MCTRL_SDRAM_SEPBUS 0`
473			`#endif`
474
475			`#ifndef CONFIG_MCTRL_SDRAM_INVCLK`
476			`#define CONFIG_MCTRL_SDRAM_INVCLK 0`
477			`#endif`
478
479			`#ifndef CONFIG_MCTRL_SDRAM_BUS64`
480			`#define CONFIG_MCTRL_SDRAM_BUS64 0`
481			`#endif`
482
483			`#ifndef CONFIG_AHBROM_ENABLE`
484			`#define CONFIG_AHBROM_ENABLE 0`
485			`#endif`
486
487			`#ifndef CONFIG_AHBROM_START`
488			`#define CONFIG_AHBROM_START 000`
489			`#endif`
490
491			`#ifndef CONFIG_AHBROM_PIPE`
492			`#define CONFIG_AHBROM_PIPE 0`
493			`#endif`
494
495			`#if (CONFIG_AHBROM_START == 0) && (CONFIG_AHBROM_ENABLE == 1)`
496			`#define CONFIG_ROM_START 100`
497			`#else`
498			`#define CONFIG_ROM_START 000`
499			`#endif`
500
501			`#ifndef CONFIG_AHBRAM_ENABLE`
502			`#define CONFIG_AHBRAM_ENABLE 0`
503			`#endif`
504
505			`#ifndef CONFIG_AHBRAM_START`
506			`#define CONFIG_AHBRAM_START A00`
507			`#endif`
508
509			`#if defined CONFIG_AHBRAM_SZ1`
510			`#define CFG_AHBRAMSZ 1`
511			`#elif CONFIG_AHBRAM_SZ2`
512			`#define CFG_AHBRAMSZ 2`
513			`#elif CONFIG_AHBRAM_SZ4`
514			`#define CFG_AHBRAMSZ 4`
515			`#elif CONFIG_AHBRAM_SZ8`
516			`#define CFG_AHBRAMSZ 8`
517			`#elif CONFIG_AHBRAM_SZ16`
518			`#define CFG_AHBRAMSZ 16`
519			`#elif CONFIG_AHBRAM_SZ32`
520			`#define CFG_AHBRAMSZ 32`
521			`#elif CONFIG_AHBRAM_SZ64`
522			`#define CFG_AHBRAMSZ 64`
523			`#else`
524			`#define CFG_AHBRAMSZ 1`
525			`#endif`
526
527			`#ifndef CONFIG_AHBRAM_START`
528			`#define CONFIG_AHBRAM_START 0`
529			`#endif`
530
531			`#ifndef CONFIG_ETH_ENABLE`
532			`#define CONFIG_ETH_ENABLE 0`
533			`#endif`
534
535			`#ifndef CONFIG_ETH_START`
536			`#define CONFIG_ETH_START B00`
537			`#endif`
538
539			`#if defined CONFIG_PCI_SIMPLE_TARGET`
540			`#define CFG_PCITYPE 1`
541			`#elif defined CONFIG_PCI_MASTER_TARGET`
542			`#define CFG_PCITYPE 2`
543			`#elif defined CONFIG_PCI_MASTER_TARGET_DMA`
544			`#define CFG_PCITYPE 3`
545			`#else`
546			`#define CFG_PCITYPE 0`
547			`#endif`
548
549			`#ifndef CONFIG_PCI_VENDORID`
550			`#define CONFIG_PCI_VENDORID 0`
551			`#endif`
552
553			`#ifndef CONFIG_PCI_DEVICEID`
554			`#define CONFIG_PCI_DEVICEID 0`
555			`#endif`
556
557			`#ifndef CONFIG_PCI_REVID`
558			`#define CONFIG_PCI_REVID 0`
559			`#endif`
560
561			`#if defined CONFIG_PCI_FIFO16`
562			`#define CFG_PCIFIFO 16`
563			`#elif defined CONFIG_PCI_FIFO32`
564			`#define CFG_PCIFIFO 32`
565			`#elif defined CONFIG_PCI_FIFO64`
566			`#define CFG_PCIFIFO 64`
567			`#elif defined CONFIG_PCI_FIFO128`
568			`#define CFG_PCIFIFO 128`
569			`#elif defined CONFIG_PCI_FIFO256`
570			`#define CFG_PCIFIFO 256`
571			`#else`
572			`#define CFG_PCIFIFO 8`
573			`#endif`
574
575			`#ifndef CONFIG_PCI_ARBITER_APB`
576			`#define CONFIG_PCI_ARBITER_APB 0`
577			`#endif`
578
579			`#ifndef CONFIG_PCI_ARBITER`
580			`#define CONFIG_PCI_ARBITER 0`
581			`#endif`
582
583			`#ifndef CONFIG_PCI_TRACE`
584			`#define CONFIG_PCI_TRACE 0`
585			`#endif`
586
587			`#if defined CONFIG_PCI_TRACE512`
588			`#define CFG_PCI_TRACEBUF 512`
589			`#elif defined CONFIG_PCI_TRACE1024`
590			`#define CFG_PCI_TRACEBUF 1024`
591			`#elif defined CONFIG_PCI_TRACE2048`
592			`#define CFG_PCI_TRACEBUF 2048`
593			`#elif defined CONFIG_PCI_TRACE4096`
594			`#define CFG_PCI_TRACEBUF 4096`
595			`#else`
596			`#define CFG_PCI_TRACEBUF 256`
597			`#endif`
598
599			`#ifndef CONFIG_UART1_ENABLE`
600			`#define CONFIG_UART1_ENABLE 0`
601			`#endif`
602
603			`#if defined CONFIG_UA1_FIFO1`
604			`#define CFG_UA1_FIFO 1`
605			`#elif defined CONFIG_UA1_FIFO2`
606			`#define CFG_UA1_FIFO 2`
607			`#elif defined CONFIG_UA1_FIFO4`
608			`#define CFG_UA1_FIFO 4`
609			`#elif defined CONFIG_UA1_FIFO8`
610			`#define CFG_UA1_FIFO 8`
611			`#elif defined CONFIG_UA1_FIFO16`
612			`#define CFG_UA1_FIFO 16`
613			`#elif defined CONFIG_UA1_FIFO32`
614			`#define CFG_UA1_FIFO 32`
615			`#else`
616			`#define CFG_UA1_FIFO 1`
617			`#endif`
618
619			`#ifndef CONFIG_UART2_ENABLE`
620			`#define CONFIG_UART2_ENABLE 0`
621			`#endif`
622
623			`#if defined CONFIG_UA2_FIFO1`
624			`#define CFG_UA2_FIFO 1`
625			`#elif defined CONFIG_UA2_FIFO2`
626			`#define CFG_UA2_FIFO 2`
627			`#elif defined CONFIG_UA2_FIFO4`
628			`#define CFG_UA2_FIFO 4`
629			`#elif defined CONFIG_UA2_FIFO8`
630			`#define CFG_UA2_FIFO 8`
631			`#elif defined CONFIG_UA2_FIFO16`
632			`#define CFG_UA2_FIFO 16`
633			`#elif defined CONFIG_UA2_FIFO32`
634			`#define CFG_UA2_FIFO 32`
635			`#else`
636			`#define CFG_UA2_FIFO 1`
637			`#endif`
638
639			`#ifndef CONFIG_IRQ3_ENABLE`
640			`#define CONFIG_IRQ3_ENABLE 0`
641			`#endif`
642
643			`#ifndef CONFIG_GPT_ENABLE`
644			`#define CONFIG_GPT_ENABLE 0`
645			`#endif`
646
647			`#ifndef CONFIG_GPT_NTIM`
648			`#define CONFIG_GPT_NTIM 1`
649			`#endif`
650
651			`#ifndef CONFIG_GPT_SW`
652			`#define CONFIG_GPT_SW 8`
653			`#endif`
654
655			`#ifndef CONFIG_GPT_TW`
656			`#define CONFIG_GPT_TW 8`
657			`#endif`
658
659			`#ifndef CONFIG_GPT_IRQ`
660			`#define CONFIG_GPT_IRQ 8`
661			`#endif`
662
663			`#ifndef CONFIG_GPT_SEPIRQ`
664			`#define CONFIG_GPT_SEPIRQ 0`
665			`#endif`
666
667			`#ifndef CONFIG_PCI_RESETALL`
668			`#define CONFIG_PCI_RESETALL 0`
669			`#endif`
670
671			`#ifndef CONFIG_IU_DISAS`
672			`#define CONFIG_IU_DISAS 0`
673			`#endif`
674
675			`#ifndef CONFIG_CAN_ENABLE`
676			`#define CONFIG_CAN_ENABLE 0`
677			`#endif`
678
679			`#ifndef CONFIG_CANIO`
680			`#define CONFIG_CANIO 0`
681			`#endif`
682
683			`#ifndef CONFIG_CANIRQ`
684			`#define CONFIG_CANIRQ 0`
685			`#endif`
686
687			`#ifndef CONFIG_CANLOOP`
688			`#define CONFIG_CANLOOP 0`
689			`#endif`
690
691			`#ifndef CONFIG_DEBUG_UART`
692			`#define CONFIG_DEBUG_UART 0`
693			`#endif`
694
695			`#ifdef CONFIG_DEBUG_PC32`
696			`#define CFG_DEBUG_PC32 0`
697			`#else`
698			`#define CFG_DEBUG_PC32 2`
699			`#endif`