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trailer
<<
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0
%%EOF
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/Title (16.1 Introduction)
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/Title (16.8 Instantiation)
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9921 0 obj
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/Title (16.7 Library dependencies)
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/Title (16.6 Signal descriptions)
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9923 0 obj
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/Title (16.5 Configuration options)
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/Title (16.4 Vendor and device identifiers)
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/Title (16.3 Registers)
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/Title (16.2 Operation)
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endobj
9927 0 obj
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/Title (16.3.1 VGA Data Register)
/Dest (G13.1082773)
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/Next 9929 0 R
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endobj
9928 0 obj
<<
/Title (16.3.3 VGA Foreground Color)
/Dest (G13.1082944)
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9929 0 obj
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/Title (16.3.2 VGA Background Color)
/Dest (G13.1082858)
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endobj
9930 0 obj
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/Title (14 GRGPIO - General Purpose I/O Port)
/Dest (G11.966345)
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/Count -9
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/Title (15.1 Introduction)
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endobj
9932 0 obj
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/Title (15.12 Keyboard commands)
/Dest (G12.1082205)
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endobj
9933 0 obj
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/Title (15.11 Keboard scan codes)
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/Title (15.10 Instantiation)
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/Title (15.9 Library dependencies)
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/Title (15.8 Signal descriptions)
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/Title (15.7 Configuration options)
/Dest (G12.1084817)
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/Title (15.6 Vendor and device identifiers)
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/Title (15.5 Registers)
/Dest (G12.1079763)
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/Count -4
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endobj
9940 0 obj
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/Title (15.4 Clock generation)
/Dest (G12.1083662)
/Parent 9918 0 R
/Prev 9945 0 R
/Next 9939 0 R
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endobj
9941 0 obj
<<
/Title (15.5.1 PS/2 Data Register)
/Dest (G12.1080697)
/Parent 9939 0 R
/Next 9944 0 R
>>
endobj
9942 0 obj
<<
/Title (15.5.4 PS/2 Timer Reload Register)
/Dest (G12.1083476)
/Parent 9939 0 R
/Prev 9943 0 R
>>
endobj
9943 0 obj
<<
/Title (15.5.3 PS/2 Control Register)
/Dest (G12.1079765)
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/Next 9942 0 R
>>
endobj
9944 0 obj
<<
/Title (15.5.2 PS/2 Status Register)
/Dest (G12.1080557)
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endobj
9945 0 obj
<<
/Title (15.3 Transmitter operations)
/Dest (G12.1079978)
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endobj
9946 0 obj
<<
/Title (15.2 Receiver operation)
/Dest (G12.1078909)
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/Prev 9931 0 R
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>>
endobj
9947 0 obj
<<
/Title (13 GPTIMER - General Purpose Timer Unit)
/Dest (G10.1016816)
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/Count -8
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9948 0 obj
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/Title (14.1 Overview)
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9949 0 obj
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/Title (14.9 Instantiation)
/Dest (G11.1041089)
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9950 0 obj
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/Title (14.8 Component declaration)
/Dest (G11.1041063)
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9951 0 obj
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/Title (14.7 Library dependencies)
/Dest (G11.1041024)
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9952 0 obj
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/Title (14.6 Signal descriptions)
/Dest (G11.1040652)
/Parent 9930 0 R
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endobj
9953 0 obj
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/Title (14.5 Configuration options)
/Dest (G11.1040581)
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endobj
9954 0 obj
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/Title (14.4 Vendor and device identifiers)
/Dest (G11.1040579)
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9955 0 obj
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/Title (14.3 Registers)
/Dest (G11.1040443)
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/Next 9954 0 R
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endobj
9956 0 obj
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/Title (14.2 Operation)
/Dest (G11.1040440)
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endobj
9957 0 obj
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/Title (12 APBUART - AMBA APB UART Serial Interface)
/Dest (G9.966345)
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/Count -9
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9958 0 obj
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/Title (13.1 Overview)
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/Next 9965 0 R
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9959 0 obj
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/Title (13.8 Instantiation)
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9960 0 obj
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/Title (13.7 Library dependencies)
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9961 0 obj
<<
/Title (13.6 Signal descriptions)
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9962 0 obj
<<
/Title (13.5 Configuration options)
/Dest (G10.1055730)
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9963 0 obj
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/Title (13.4 Vendor and device identifiers)
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9964 0 obj
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/Title (13.3 Registers)
/Dest (G10.1055530)
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9965 0 obj
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/Title (13.2 Operation)
/Dest (G10.1055523)
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endobj
9966 0 obj
<<
/Title (11 AHBSTAT - AHB Status Registers)
/Dest (G8.966345)
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/Count -8
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9967 0 obj
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/Title (12.1 Overview)
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9968 0 obj
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/Title (12.9 Instantiation)
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9969 0 obj
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/Title (12.8 Library dependencies)
/Dest (G9.1090134)
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9970 0 obj
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/Title (12.7 Signal descriptions)
/Dest (G9.1090003)
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9971 0 obj
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/Title (12.6 Configuration options)
/Dest (G9.1089916)
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endobj
9972 0 obj
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/Title (12.5 Vendor and device identifiers)
/Dest (G9.1089914)
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9973 0 obj
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/Title (12.4 Registers)
/Dest (G9.1089736)
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/Count -4
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endobj
9974 0 obj
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/Title (12.3 Baud-rate generation)
/Dest (G9.1089729)
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/Count -2
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endobj
9975 0 obj
<<
/Title (12.4.1 UART Data Register)
/Dest (G9.1089777)
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/Next 9978 0 R
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endobj
9976 0 obj
<<
/Title (12.4.4 UART Scaler Register)
/Dest (G9.1089913)
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endobj
9977 0 obj
<<
/Title (12.4.3 UART Control Register)
/Dest (G9.1089887)
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endobj
9978 0 obj
<<
/Title (12.4.2 UART Status Register)
/Dest (G9.1089831)
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endobj
9979 0 obj
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/Title (12.2 Operation)
/Dest (G9.1089639)
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/Count -2
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9980 0 obj
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/Title (12.3.1 Loop back mode)
/Dest (G9.1089731)
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endobj
9981 0 obj
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/Title (12.3.2 Interrupt generation)
/Dest (G9.1089733)
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9982 0 obj
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/Title (12.2.1 Transmitter operation)
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/Title (12.2.2 Receiver operation)
/Dest (G9.1089724)
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endobj
9984 0 obj
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/Title (10 MCTRL - Combined PROM/IO/SRAM/SDRAM Memory Controller)
/Dest (G7.966345)
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/Count -18
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9985 0 obj
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/Title (11.1 Overview)
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9986 0 obj
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/Title (11.8 Instantiation)
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9987 0 obj
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/Title (11.7 Library dependencies)
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9988 0 obj
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/Title (11.6 Signal descriptions)
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9989 0 obj
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/Title (11.5 Configuration options)
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/Title (11.4 Vendor and device identifiers)
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/Title (11.3 Registers)
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/Title (11.2 Operation)
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/Title (9 IRQMP - Multiprocessor Interrupt Controller)
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/Title (10.1 Overview)
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endobj
9995 0 obj
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/Title (10.18 Instantiation)
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endobj
9996 0 obj
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/Title (10.17 Library dependencies)
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endobj
9997 0 obj
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/Title (10.16 Signal descriptions)
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endobj
9998 0 obj
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/Title (10.15 Configuration options)
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endobj
9999 0 obj
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/Title (10.14 Vendor and device identifiers)
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/Title (10.13 Registers)
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/Count -3
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endobj
10001 0 obj
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/Title (10.12 Attaching an external DRAM controller)
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10002 0 obj
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/Title (10.13.1 Memory configuration register 1 \(MCFG1\))
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10003 0 obj
<<
/Title (10.13.3 Memory configuration register 3 \(MCFG3\))
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10004 0 obj
<<
/Title (10.13.2 Memory configuration register 2 \(MCFG2\))
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endobj
10005 0 obj
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/Title (10.11 Access errors)
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endobj
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/Title (10.10 Using bus ready signalling)
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/Title (10.9 Refresh)
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/Count -6
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/Title (10.8 SDRAM access)
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/Count -4
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/Title (10.9.1 SDRAM commands)
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/Title (10.9.6 Clocking)
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/Title (10.9.4 Address bus connection)
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/Title (10.9.3 Write cycles)
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/Title (10.9.2 Read cycles)
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/Title (10.7 8- and 16-bit I/O access)
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10016 0 obj
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10017 0 obj
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/Title (10.8.3 Initialisation)
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10020 0 obj
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/Title (10.6 Burst cycles)
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endobj
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/Title (10.5 8-bit and 16-bit PROM and SRAM access)
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10022 0 obj
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10023 0 obj
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/Title (10.3 Memory mapped I/O)
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10024 0 obj
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/Title (10.2 PROM access)
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endobj
10025 0 obj
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/Title (8 DSU3 - LEON3 Hardware Debug Support Unit)
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/Count -12
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10027 0 obj
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/Title (9.6 Signal descriptions)
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/Title (9.5 Configuration options)
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10031 0 obj
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/Title (9.3 Registers)
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/Count -7
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endobj
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/Title (9.2 Operation)
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endobj
10034 0 obj
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/Title (9.3.1 Interrupt level register)
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endobj
10035 0 obj
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/Title (9.3.7 Processor interrupt force register \(NCPU > 0\))
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endobj
10036 0 obj
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/Title (9.3.6 Processor interrupt mask register)
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endobj
10037 0 obj
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/Title (9.3.5 Multiprocessor status register)
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endobj
10038 0 obj
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/Title (9.3.4 Interrupt clear register)
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endobj
10039 0 obj
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/Title (9.3.3 Interrupt force register \(NCPU = 0\))
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10040 0 obj
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/Title (9.3.2 Interrupt pending register)
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endobj
10041 0 obj
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/Title (9.2.1 Interrupt prioritization)
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endobj
10042 0 obj
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/Title (9.2.2 Processor status monitoring)
/Dest (G6.1134557)
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endobj
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/Title (7 GRFPC - GRFPU Control Unit)
/Dest (G4.1007208)
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/Count -3
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/Title (8.1 Overview)
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/Title (8.12 Instantiation)
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/Title (8.11 Component declaration)
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/Title (8.10 Library dependencies)
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/Next 10046 0 R
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/Title (8.9 Signal descriptions)
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/Next 10047 0 R
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/Title (8.8 Configuration options)
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/Title (8.7 Vendor and device identifiers)
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/Title (8.6 DSU registers)
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/Count -10
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endobj
10052 0 obj
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/Title (8.5 DSU memory map)
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/Next 10051 0 R
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10053 0 obj
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/Title (8.6.1 DSU control register)
/Dest (G5.1065835)
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/Next 10062 0 R
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endobj
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/Title (8.6.10 Instruction trace control register)
/Dest (G5.1066110)
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/Prev 10055 0 R
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endobj
10055 0 obj
<<
/Title (8.6.9 AHB trace buffer breakpoint registers)
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/Next 10054 0 R
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endobj
10056 0 obj
<<
/Title (8.6.8 AHB trace buffer index register)
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10057 0 obj
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/Title (8.6.7 AHB Trace buffer control register)
/Dest (G5.1066035)
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10058 0 obj
<<
/Title (8.6.6 DSU ASI register)
/Dest (G5.1066019)
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10059 0 obj
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/Title (8.6.5 Trace buffer time tag counter)
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/Next 10058 0 R
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10060 0 obj
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/Title (8.6.4 DSU trap register)
/Dest (G5.1065978)
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endobj
10061 0 obj
<<
/Title (8.6.3 DSU Debug Mode Mask Register)
/Dest (G5.1065938)
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/Next 10060 0 R
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endobj
10062 0 obj
<<
/Title (8.6.2 DSU Break and Single Step register)
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10063 0 obj
<<
/Title (8.4 Instruction trace buffer)
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/Title (8.3 AHB Trace Buffer)
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/Next 10063 0 R
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10065 0 obj
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/Title (8.2 Operation)
/Dest (G5.1065500)
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/Prev 10044 0 R
/Next 10064 0 R
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endobj
10066 0 obj
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/Title (6 GRFPU - High-performance IEEE-754 Floating-point unit)
/Dest (G4.998206)
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/Next 10043 0 R
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/Count -4
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10067 0 obj
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/Title (7.1 Floating-Point register file)
/Dest (G4.1002404)
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10068 0 obj
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/Title (7.3 Floating-Point Exceptions and Floating-Point Deferred-Queue)
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/Parent 10043 0 R
/Prev 10069 0 R
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10069 0 obj
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/Title (7.2 Floating-Point State Register \(FSR\))
/Dest (G4.1002410)
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/Next 10068 0 R
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endobj
10070 0 obj
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/Title (5 LEON3 - High-performance SPARC V8 32-bit Processor)
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/Next 10066 0 R
/First 10083 0 R
/Last 10084 0 R
/Count -13
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10071 0 obj
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/Title (6.1 Overview)
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/Next 10074 0 R
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/Title (6.4 Timing)
/Dest (G4.1002164)
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/Prev 10073 0 R
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/Title (6.3 Signal descriptions)
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/Next 10072 0 R
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/Title (6.2 Functional description)
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/Next 10073 0 R
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/Count -7
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endobj
10075 0 obj
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/Title (6.2.1 Floating-point number formats)
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/Parent 10074 0 R
/Next 10081 0 R
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10076 0 obj
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/Title (6.2.7 NaNs)
/Dest (G4.999330)
/Parent 10074 0 R
/Prev 10077 0 R
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endobj
10077 0 obj
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/Title (6.2.6 Non-standard Mode)
/Dest (G4.998616)
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/Next 10076 0 R
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10078 0 obj
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/Title (6.2.5 Denormalized numbers)
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/Next 10077 0 R
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10079 0 obj
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/Title (6.2.4 Rounding)
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/Title (6.2.3 Exceptions)
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10081 0 obj
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/Title (6.2.2 FP operations)
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/Next 10080 0 R
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/Title (4 Software development)
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/Count -4
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/Title (5.1 Overview)
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/Count -10
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10084 0 obj
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/Title (5.13 Component declaration)
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/Title (5.12 Library dependencies)
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/Title (5.11 Signal descriptions)
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/Title (5.10 Configuration options)
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/Title (5.9 Synthesis and hardware)
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/Count -3
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/Title (5.9.1 Area and timing)
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/Title (5.9.3 Double clocking)
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10092 0 obj
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/Title (5.7 Floating-point unit and custom co-processor interface)
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/Count -4
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/Title (5.7.1 Gaisler Research\220s floating-point unit \(GRFPU\))
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/Title (5.7.4 Generic co-processor)
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10097 0 obj
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/Title (5.7.3 The Meiko FPU)
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10098 0 obj
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/Title (5.7.2 GRFPU-Lite)
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/Title (5.5 Additional cache functionality)
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/Count -8
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10100 0 obj
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/Title (5.6.1 ASI mappings)
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10101 0 obj
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10102 0 obj
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/Title (5.6.3 MMU registers)
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10103 0 obj
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/Title (5.6.2 Cache operation)
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/Title (5.4 Data cache)
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/Title (5.5.1 Cache flushing)
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/Title (5.5.8 Software consideration)
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/Title (5.5.5 Local scratch pad ram)
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/Title (5.5.3 Cache line locking)
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/Title (5.3 Instruction cache)
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10114 0 obj
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10115 0 obj
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10116 0 obj
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/Title (5.2 LEON3 integer unit)
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/Count -16
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/Title (5.2.1 Overview)
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10121 0 obj
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/Title (5.2.16 Cache sub-system)
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/Title (5.2.14 Processor reset operation)
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/Title (5.2.13 Power-down)
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/Title (5.2.12 Address space identifiers \(ASI\))
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/Title (5.2.11 Single vector trapping \(SVT\))
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/Title (5.2.9 Processor configuration register)
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/Title (5.2.3 SPARC Implementor\220s ID)
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10138 0 obj
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/Title (3 Simulation and synthesis)
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/Count -7
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/Title (4.4 RTEMS spacewire driver and demo program)
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/Title (4.3 Flash PROM programming)
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/Title (2.15 GRLIB IP Cores)
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