URL https://opencores.org/ocsvn/mips_enhanced/mips_enhanced/trunk

Subversion Repositories mips_enhanced

[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [designs/] [leon3-gr-xc3s-1500/] [modelsim/] [gaisler/] [dmem_ctl_reg/] [_primary.vhd] - Blame information for rev 2

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library verilog;
use verilog.vl_types.all;
entity dmem_ctl_reg is
    port(
        dmem_ctl_i      : in     vl_logic_vector(4 downto 0);
        dmem_ctl_o      : out    vl_logic_vector(4 downto 0);
        clk             : in     vl_logic;
        hold            : in     vl_logic
    );
end dmem_ctl_reg;

Line No.	Rev	Author	Line
1	2	dimamali	`library verilog;`
2			`use verilog.vl_types.all;`
3			`entity dmem_ctl_reg is`
4			`port(`
5			`dmem_ctl_i : in vl_logic_vector(4 downto 0);`
6			`dmem_ctl_o : out vl_logic_vector(4 downto 0);`
7			`clk : in vl_logic;`
8			`hold : in vl_logic`
9			`);`
10			`end dmem_ctl_reg;`

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Subversion Repositories mips_enhanced

[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [designs/] [leon3-gr-xc3s-1500/] [modelsim/] [gaisler/] [dmem_ctl_reg/] [_primary.vhd] - Blame information for rev 2