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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [designs/] [leon3-gr-xc3s-1500/] [modelsim/] [opencores/] [ac97_rf/] [_primary.vhd] - Blame information for rev 2

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Line No. Rev Author Line
1 2 dimamali
library verilog;
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use verilog.vl_types.all;
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entity ac97_rf is
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    port(
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        clk             : in     vl_logic;
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        rst             : in     vl_logic;
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        adr             : in     vl_logic_vector(3 downto 0);
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        rf_dout         : out    vl_logic_vector(31 downto 0);
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        rf_din          : in     vl_logic_vector(31 downto 0);
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        rf_we           : in     vl_logic;
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        rf_re           : in     vl_logic;
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        int             : out    vl_logic;
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        ac97_rst_force  : out    vl_logic;
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        resume_req      : out    vl_logic;
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        suspended       : in     vl_logic;
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        crac_we         : out    vl_logic;
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        crac_din        : in     vl_logic_vector(15 downto 0);
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        crac_out        : out    vl_logic_vector(31 downto 0);
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        crac_rd_done    : in     vl_logic;
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        crac_wr_done    : in     vl_logic;
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        oc0_cfg         : out    vl_logic_vector(7 downto 0);
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        oc1_cfg         : out    vl_logic_vector(7 downto 0);
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        oc2_cfg         : out    vl_logic_vector(7 downto 0);
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        oc3_cfg         : out    vl_logic_vector(7 downto 0);
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        oc4_cfg         : out    vl_logic_vector(7 downto 0);
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        oc5_cfg         : out    vl_logic_vector(7 downto 0);
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        ic0_cfg         : out    vl_logic_vector(7 downto 0);
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        ic1_cfg         : out    vl_logic_vector(7 downto 0);
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        ic2_cfg         : out    vl_logic_vector(7 downto 0);
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        oc0_int_set     : in     vl_logic_vector(2 downto 0);
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        oc1_int_set     : in     vl_logic_vector(2 downto 0);
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        oc2_int_set     : in     vl_logic_vector(2 downto 0);
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        oc3_int_set     : in     vl_logic_vector(2 downto 0);
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        oc4_int_set     : in     vl_logic_vector(2 downto 0);
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        oc5_int_set     : in     vl_logic_vector(2 downto 0);
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        ic0_int_set     : in     vl_logic_vector(2 downto 0);
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        ic1_int_set     : in     vl_logic_vector(2 downto 0);
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        ic2_int_set     : in     vl_logic_vector(2 downto 0)
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    );
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end ac97_rf;

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