Subversion Repositories mips_enhanced

[Library]

grlib = modelsim/grlib

unisim = modelsim/unisim

dw02 = modelsim/dw02

synplify = modelsim/synplify

techmap = modelsim/techmap

spw = modelsim/spw

eth = modelsim/eth

opencores = modelsim/opencores

gaisler = modelsim/gaisler

esa = modelsim/esa

micron = modelsim/micron

work = modelsim/work

std = $MODEL_TECH/../std

ieee = $MODEL_TECH/../ieee

vital2000 = $MODEL_TECH/../vital2000

verilog = $MODEL_TECH/../verilog

arithmetic = $MODEL_TECH/../arithmetic

mgc_portable = $MODEL_TECH/../mgc_portable

std_developerskit = $MODEL_TECH/../std_developerskit

synopsys = $MODEL_TECH/../synopsys

[vcom]

; Turn on VHDL-1993 as the default. Normally is off.

VHDL93 = 1

; Show source line containing error. Default is off.

Show_source = 1

; Turn off unbound-component warnings. Default is on.

Show_Warning1 = 0

; Turn off process-without-a-wait-statement warnings. Default is on.

; Show_Warning2 = 0

; Turn off null-range warnings. Default is on.

; Show_Warning3 = 0

; Turn off no-space-in-time-literal warnings. Default is on.

; Show_Warning4 = 0

; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.

Show_Warning5 = 0

; Turn off optimization for IEEE std_logic_1164 package. Default is on.

; Optimize_1164 = 0

; Turn on resolving of ambiguous function overloading in favor of the

; "explicit" function declaration (not the one automatically created by

; the compiler for each type declaration). Default is off.

; Explicit = 1

; Turn off VITAL compliance checking. Default is checking on.

; NoVitalCheck = 1

; Ignore VITAL compliance checking errors. Default is to not ignore.

; IgnoreVitalErrors = 1

; Turn off VITAL compliance checking warnings. Default is to show warnings.

; Show_VitalChecksWarnings = false

; Turn off acceleration of the VITAL packages. Default is to accelerate.

; NoVital = 1

; Turn off inclusion of debugging info within design units. Default is to include.

; NoDebug = 1

; Turn off "loading..." messages. Default is messages on.

Quiet = 1

; Turn on some limited synthesis rule compliance checking. Checks only:

;       -- signals used (read) by a process must be in the sensitivity list

; CheckSynthesis = 1

[vlog]

; Turn off inclusion of debugging info within design units. Default is to include.

; NoDebug = 1

; Turn off "loading..." messages. Default is messages on.

Quiet = 1

; Turn on Verilog hazard checking (order-dependent accessing of global vars).

; Default is off.

; Hazard = 1

; Turn on converting regular Verilog identifiers to uppercase. Allows case

; insensitivity for module names. Default is no conversion.

; UpCase = 1

[vsim]

; vopt flow

; Set to turn on automatic optimization of a design.

; Default is off (pre-6.0 flow without vopt).

VoptFlow = 0

; Simulator resolution

; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.

Resolution = 1ps

; User time unit for run commands

; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the

; unit specified for Resolution. For example, if Resolution is 100ps,

; then UserTimeUnit defaults to ps.

UserTimeUnit = ns

; Default run length

RunLength = 100

; Maximum iterations that can be run without advancing simulation time

IterationLimit = 5000

; Directive to license manager:

; vhdl          Immediately reserve a VHDL license

; vlog          Immediately reserve a Verilog license

; plus          Immediately reserve a VHDL and Verilog license

; nomgc         Do not look for Mentor Graphics Licenses

; nomti         Do not look for Model Technology Licenses

; noqueue       Do not wait in the license queue when a license isn't available

; License = plus

; Stop the simulator after an assertion message

; 0 = Note  1 = Warning  2 = Error  3 = Failure  4 = Fatal

BreakOnAssertion = 3

; Assertion Message Format

; %S - Severity Level

; %R - Report Message

; %T - Time of assertion

; %D - Delta

; %I - Instance or Region pathname (if available)

; %% - print '%' character

; AssertionFormat = "** %S: %R\n   Time: %T  Iteration: %D%I\n"

; Default radix for all windows and commands...

; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned

DefaultRadix = symbolic

; VSIM Startup command

; Startup = do startup.do

; File for saving command transcript

TranscriptFile = transcript

; Specify whether paths in simulator commands should be described

; in VHDL or Verilog format. For VHDL, PathSeparator = /

; for Verilog, PathSeparator = .

PathSeparator = /

; Disable assertion messages

; IgnoreNote = 1

; IgnoreWarning = 1

; IgnoreError = 1

; IgnoreFailure = 1

; Default force kind. May be freeze, drive, or deposit

; or in other terms, fixed, wired or charged.

; DefaultForceKind = freeze

; If zero, open files when elaborated

; else open files on first read or write

; DelayFileOpen = 0

; Control VHDL files opened for write

;   0 = Buffered, 1 = Unbuffered

UnbufferedOutput = 0

; This controls the number of characters of a signal name

; shown in the waveform window and the postscript plot.

; The default value or a value of zero tells VSIM to display

; the full name.

; WaveSignalNameWidth = 10

; Turn off warnings from the std_logic_arith, std_logic_unsigned

; and std_logic_signed packages.

; StdArithNoWarnings = 1

; Turn off warnings from the IEEE numeric_std and numeric_bit

; packages.

; NumericStdNoWarnings = 1

; Control the format of a generate statement label. Don't quote it.

; GenerateFormat = %s__%d

; Specify whether checkpoint files should be compressed.

; The default is to be compressed.

; CheckpointCompressMode = 0

; List of dynamically loaded objects for Verilog PLI applications

; Veriuser = veriuser.sl

[lmc]

; ModelSim's interface to Logic Modeling's SmartModel SWIFT software

libsm = $MODEL_TECH/libsm.sl

; ModelSim's interface to Logic Modeling's SmartModel SWIFT software (Windows NT)

; libsm = $MODEL_TECH/libsm.dll

;  Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700)

; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl

;  Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000)

; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o

;  Logic Modeling's SmartModel SWIFT software (Sun4 Solaris)

; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so

;  Logic Modeling's SmartModel SWIFT software (Sun4 SunOS)

;       do setenv LD_LIBRARY_PATH $LMC_HOME/lib/sun4SunOS.lib

;       and run "vsim.swift".

;  Logic Modeling's SmartModel SWIFT software (Windows NT)

; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll

; ModelSim's interface to Logic Modeling's hardware modeler SFI software

libhm = $MODEL_TECH/libhm.sl

; ModelSim's interface to Logic Modeling's hardware modeler SFI software (Windows NT)

; libhm = $MODEL_TECH/libhm.dll

;  Logic Modeling's hardware modeler SFI software (HP 9000 Series 700)

; libsfi = /lib/hp700/libsfi.sl

;  Logic Modeling's hardware modeler SFI software (IBM RISC System/6000)

; libsfi = /lib/rs6000/libsfi.a

;  Logic Modeling's hardware modeler SFI software (Sun4 Solaris)

; libsfi = /lib/sun4.solaris/libsfi.so

;  Logic Modeling's hardware modeler SFI software (Sun4 SunOS)

; libsfi = /lib/sun4.sunos/libsfi.so

;  Logic Modeling's hardware modeler SFI software (Window NT)

; libsfi = /lib/pcnt/lm_sfi.dll