Subversion Repositories mips_enhanced

# //  ModelSim SE 6.3f Feb 28 2008

# //

# //  Copyright 1991-2008 Mentor Graphics Corporation

# //              All Rights Reserved.

# //

# //  THIS WORK CONTAINS TRADE SECRET AND

# //  PROPRIETARY INFORMATION WHICH IS THE PROPERTY

# //  OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS

# //  AND IS SUBJECT TO LICENSE TERMS.

# //

# OpenFile testbench.mpf

# Loading project testbench

do modelsim.do

# vsim -quiet work.testbench

# ** Warning: (vsim-3017) C:/grlib-gpl-1.0.19-b3188/lib/gaisler/vlog/RF_stage1.v(199): [TFMPC] - Too few port connections. Expected 4, found 3.

#         Region: /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iRF_stage/jack2

# ** Warning: (vsim-3722) C:/grlib-gpl-1.0.19-b3188/lib/gaisler/vlog/RF_stage1.v(199): [TFMPC] - Missing connection for port 'rd_o'.

# ** Warning: (vsim-3017) C:/grlib-gpl-1.0.19-b3188/lib/gaisler/vlog/EXEC_stage.v(167): [TFMPC] - Too few port connections. Expected 7, found 6.

#         Region: /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iexec_stage/MIPS_alu/muldiv_ff

# ** Warning: (vsim-3722) C:/grlib-gpl-1.0.19-b3188/lib/gaisler/vlog/EXEC_stage.v(167): [TFMPC] - Missing connection for port 'rdy'.

# ** Warning: (vsim-3017) C:/grlib-gpl-1.0.19-b3188/lib/gaisler/vlog/decode_pipe1.v(1982): [TFMPC] - Too few port connections. Expected 20, found 18.

#         Region: /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/decoder_pipe/idecoder

# ** Warning: (vsim-3722) C:/grlib-gpl-1.0.19-b3188/lib/gaisler/vlog/decode_pipe1.v(1982): [TFMPC] - Missing connection for port 'read_rs'.

# ** Warning: (vsim-3722) C:/grlib-gpl-1.0.19-b3188/lib/gaisler/vlog/decode_pipe1.v(1982): [TFMPC] - Missing connection for port 'read_rt'.

# .main_pane.mdi.interior.cs.vm.paneset.cli_2.wf.clip.cs.pw.wf

# LEON3 GR-XC3S-1500 Demonstration design

# GRLIB Version 1.0.19, build 3188

# Target technology: spartan3  ,  memory library: spartan3

# ahbctrl: AHB arbiter/multiplexer rev 1

# ahbctrl: Common I/O area disabled

# ahbctrl: AHB masters: 3, AHB slaves: 8

# ahbctrl: Configuration area at 0xfffff000, 4 kbyte

# ahbctrl: mst0: Gaisler Research        Leon3 SPARC V8 Processor

# ahbctrl: mst1: Gaisler Research        AHB Debug UART

# ahbctrl: mst2: Gaisler Research        JTAG Debug Link

# ahbctrl: slv0: European Space Agency   Leon2 Memory Controller

# ahbctrl:       memory at 0x00000000, size 512 Mbyte, cacheable, prefetch

# ahbctrl:       memory at 0x20000000, size 512 Mbyte

# ahbctrl:       memory at 0x40000000, size 1024 Mbyte, cacheable, prefetch

# ahbctrl: slv1: Gaisler Research        AHB/APB Bridge

# ahbctrl:       memory at 0x80000000, size 1 Mbyte

# apbctrl: APB Bridge at 0x80000000 rev 1

# apbctrl: slv0: European Space Agency   Leon2 Memory Controller

# apbctrl:       I/O ports at 0x80000000, size 256 byte

# apbctrl: slv1: Gaisler Research        Generic UART

# apbctrl:       I/O ports at 0x80000100, size 256 byte

# apbctrl: slv2: Gaisler Research        Multi-processor Interrupt Ctrl.

# apbctrl:       I/O ports at 0x80000200, size 256 byte

# apbctrl: slv7: Gaisler Research        AHB Debug UART

# apbctrl:       I/O ports at 0x80000700, size 256 byte

# irqmp: Multi-processor Interrupt Controller rev 3, #cpu 1, eirq 0

# apbuart1: Generic UART rev 1, fifo 4, irq 2

# ahbjtag AHB Debug JTAG rev 0

# ahbuart7: AHB Debug UART rev 0

# leon3_0: LEON3 SPARC V8 processor rev 0

# leon3_0: icache 1*4 kbyte, dcache 4*4 kbyte

# clkgen_spartan3e: spartan3/e sdram/pci clock generator, version 1

# clkgen_spartan3e: Frequency 50000 KHz, DCM divisor 4/5

# ** Failure: *** IU in error mode, simulation halted ***

#    Time: 5 ms  Iteration: 0  Process: /testbench/iuerr File: C:/grlib-gpl-1.0.19-b3188/designs/leon3-gr-xc3s-1500/testbench.vhd

# Break in Process iuerr at C:/grlib-gpl-1.0.19-b3188/designs/leon3-gr-xc3s-1500/testbench.vhd line 362

# Simulation Breakpoint: Break in Process iuerr at C:/grlib-gpl-1.0.19-b3188/designs/leon3-gr-xc3s-1500/testbench.vhd line 362

# MACRO ./modelsim.do PAUSED at line 13

# Compile of decode_pipe1.v was successful.

# Compile of ulit.v was successful.

do modelsim.do

# vsim -quiet work.testbench

# ** Warning: (vsim-3017) C:/grlib-gpl-1.0.19-b3188/lib/gaisler/vlog/RF_stage1.v(199): [TFMPC] - Too few port connections. Expected 4, found 3.

#         Region: /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iRF_stage/jack2

# ** Warning: (vsim-3722) C:/grlib-gpl-1.0.19-b3188/lib/gaisler/vlog/RF_stage1.v(199): [TFMPC] - Missing connection for port 'rd_o'.

# ** Warning: (vsim-3017) C:/grlib-gpl-1.0.19-b3188/lib/gaisler/vlog/EXEC_stage.v(167): [TFMPC] - Too few port connections. Expected 7, found 6.

#         Region: /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iexec_stage/MIPS_alu/muldiv_ff

# ** Warning: (vsim-3722) C:/grlib-gpl-1.0.19-b3188/lib/gaisler/vlog/EXEC_stage.v(167): [TFMPC] - Missing connection for port 'rdy'.

# ** Warning: (vsim-3017) C:/grlib-gpl-1.0.19-b3188/lib/gaisler/vlog/decode_pipe1.v(1982): [TFMPC] - Too few port connections. Expected 20, found 18.

#         Region: /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/decoder_pipe/idecoder

# ** Warning: (vsim-3722) C:/grlib-gpl-1.0.19-b3188/lib/gaisler/vlog/decode_pipe1.v(1982): [TFMPC] - Missing connection for port 'read_rs'.

# ** Warning: (vsim-3722) C:/grlib-gpl-1.0.19-b3188/lib/gaisler/vlog/decode_pipe1.v(1982): [TFMPC] - Missing connection for port 'read_rt'.

# .main_pane.mdi.interior.cs.vm.paneset.cli_2.wf.clip.cs.pw.wf

# LEON3 GR-XC3S-1500 Demonstration design

# GRLIB Version 1.0.19, build 3188

# Target technology: spartan3  ,  memory library: spartan3

# ahbctrl: AHB arbiter/multiplexer rev 1

# ahbctrl: Common I/O area disabled

# ahbctrl: AHB masters: 3, AHB slaves: 8

# ahbctrl: Configuration area at 0xfffff000, 4 kbyte

# ahbctrl: mst0: Gaisler Research        Leon3 SPARC V8 Processor

# ahbctrl: mst1: Gaisler Research        AHB Debug UART

# ahbctrl: mst2: Gaisler Research        JTAG Debug Link

# ahbctrl: slv0: European Space Agency   Leon2 Memory Controller

# ahbctrl:       memory at 0x00000000, size 512 Mbyte, cacheable, prefetch

# ahbctrl:       memory at 0x20000000, size 512 Mbyte

# ahbctrl:       memory at 0x40000000, size 1024 Mbyte, cacheable, prefetch

# ahbctrl: slv1: Gaisler Research        AHB/APB Bridge

# ahbctrl:       memory at 0x80000000, size 1 Mbyte

# apbctrl: APB Bridge at 0x80000000 rev 1

# apbctrl: slv0: European Space Agency   Leon2 Memory Controller

# apbctrl:       I/O ports at 0x80000000, size 256 byte

# apbctrl: slv1: Gaisler Research        Generic UART

# apbctrl:       I/O ports at 0x80000100, size 256 byte

# apbctrl: slv2: Gaisler Research        Multi-processor Interrupt Ctrl.

# apbctrl:       I/O ports at 0x80000200, size 256 byte

# apbctrl: slv7: Gaisler Research        AHB Debug UART

# apbctrl:       I/O ports at 0x80000700, size 256 byte

# irqmp: Multi-processor Interrupt Controller rev 3, #cpu 1, eirq 0

# apbuart1: Generic UART rev 1, fifo 4, irq 2

# ahbjtag AHB Debug JTAG rev 0

# ahbuart7: AHB Debug UART rev 0

# leon3_0: LEON3 SPARC V8 processor rev 0

# leon3_0: icache 1*4 kbyte, dcache 4*4 kbyte

# clkgen_spartan3e: spartan3/e sdram/pci clock generator, version 1

# clkgen_spartan3e: Frequency 50000 KHz, DCM divisor 4/5

# ** Failure: *** IU in error mode, simulation halted ***

#    Time: 5 ms  Iteration: 0  Process: /testbench/iuerr File: C:/grlib-gpl-1.0.19-b3188/designs/leon3-gr-xc3s-1500/testbench.vhd

# Break in Process iuerr at C:/grlib-gpl-1.0.19-b3188/designs/leon3-gr-xc3s-1500/testbench.vhd line 362

# Simulation Breakpoint: Break in Process iuerr at C:/grlib-gpl-1.0.19-b3188/designs/leon3-gr-xc3s-1500/testbench.vhd line 362

# MACRO ./modelsim.do PAUSED at line 13

# Compile of core1.v was successful.

do modelsim.do

# vsim -quiet work.testbench

# ** Warning: (vsim-3017) C:/grlib-gpl-1.0.19-b3188/lib/gaisler/vlog/RF_stage1.v(199): [TFMPC] - Too few port connections. Expected 4, found 3.

#         Region: /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iRF_stage/jack2

# ** Warning: (vsim-3722) C:/grlib-gpl-1.0.19-b3188/lib/gaisler/vlog/RF_stage1.v(199): [TFMPC] - Missing connection for port 'rd_o'.

# ** Warning: (vsim-3017) C:/grlib-gpl-1.0.19-b3188/lib/gaisler/vlog/EXEC_stage.v(167): [TFMPC] - Too few port connections. Expected 7, found 6.

#         Region: /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iexec_stage/MIPS_alu/muldiv_ff

# ** Warning: (vsim-3722) C:/grlib-gpl-1.0.19-b3188/lib/gaisler/vlog/EXEC_stage.v(167): [TFMPC] - Missing connection for port 'rdy'.

# ** Warning: (vsim-3017) C:/grlib-gpl-1.0.19-b3188/lib/gaisler/vlog/decode_pipe1.v(1982): [TFMPC] - Too few port connections. Expected 20, found 18.

#         Region: /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/decoder_pipe/idecoder

# ** Warning: (vsim-3722) C:/grlib-gpl-1.0.19-b3188/lib/gaisler/vlog/decode_pipe1.v(1982): [TFMPC] - Missing connection for port 'read_rs'.

# ** Warning: (vsim-3722) C:/grlib-gpl-1.0.19-b3188/lib/gaisler/vlog/decode_pipe1.v(1982): [TFMPC] - Missing connection for port 'read_rt'.

# .main_pane.mdi.interior.cs.vm.paneset.cli_2.wf.clip.cs.pw.wf

# LEON3 GR-XC3S-1500 Demonstration design

# GRLIB Version 1.0.19, build 3188

# Target technology: spartan3  ,  memory library: spartan3

# ahbctrl: AHB arbiter/multiplexer rev 1

# ahbctrl: Common I/O area disabled

# ahbctrl: AHB masters: 3, AHB slaves: 8

# ahbctrl: Configuration area at 0xfffff000, 4 kbyte

# ahbctrl: mst0: Gaisler Research        Leon3 SPARC V8 Processor

# ahbctrl: mst1: Gaisler Research        AHB Debug UART

# ahbctrl: mst2: Gaisler Research        JTAG Debug Link

# ahbctrl: slv0: European Space Agency   Leon2 Memory Controller

# ahbctrl:       memory at 0x00000000, size 512 Mbyte, cacheable, prefetch

# ahbctrl:       memory at 0x20000000, size 512 Mbyte

# ahbctrl:       memory at 0x40000000, size 1024 Mbyte, cacheable, prefetch

# ahbctrl: slv1: Gaisler Research        AHB/APB Bridge

# ahbctrl:       memory at 0x80000000, size 1 Mbyte

# apbctrl: APB Bridge at 0x80000000 rev 1

# apbctrl: slv0: European Space Agency   Leon2 Memory Controller

# apbctrl:       I/O ports at 0x80000000, size 256 byte

# apbctrl: slv1: Gaisler Research        Generic UART

# apbctrl:       I/O ports at 0x80000100, size 256 byte

# apbctrl: slv2: Gaisler Research        Multi-processor Interrupt Ctrl.

# apbctrl:       I/O ports at 0x80000200, size 256 byte

# apbctrl: slv7: Gaisler Research        AHB Debug UART

# apbctrl:       I/O ports at 0x80000700, size 256 byte

# irqmp: Multi-processor Interrupt Controller rev 3, #cpu 1, eirq 0

# apbuart1: Generic UART rev 1, fifo 4, irq 2

# ahbjtag AHB Debug JTAG rev 0

# ahbuart7: AHB Debug UART rev 0

# leon3_0: LEON3 SPARC V8 processor rev 0

# leon3_0: icache 1*4 kbyte, dcache 4*4 kbyte

# clkgen_spartan3e: spartan3/e sdram/pci clock generator, version 1

# clkgen_spartan3e: Frequency 50000 KHz, DCM divisor 4/5

# ** Failure: *** IU in error mode, simulation halted ***

#    Time: 5 ms  Iteration: 0  Process: /testbench/iuerr File: C:/grlib-gpl-1.0.19-b3188/designs/leon3-gr-xc3s-1500/testbench.vhd

# Break in Process iuerr at C:/grlib-gpl-1.0.19-b3188/designs/leon3-gr-xc3s-1500/testbench.vhd line 362

# Simulation Breakpoint: Break in Process iuerr at C:/grlib-gpl-1.0.19-b3188/designs/leon3-gr-xc3s-1500/testbench.vhd line 362

# MACRO ./modelsim.do PAUSED at line 13

# Compile of decode_pipe1.v was successful.

do modelsim.do

# vsim -quiet work.testbench

# ** Warning: (vsim-3017) C:/grlib-gpl-1.0.19-b3188/lib/gaisler/vlog/RF_stage1.v(199): [TFMPC] - Too few port connections. Expected 4, found 3.

#         Region: /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iRF_stage/jack2

# ** Warning: (vsim-3722) C:/grlib-gpl-1.0.19-b3188/lib/gaisler/vlog/RF_stage1.v(199): [TFMPC] - Missing connection for port 'rd_o'.

# ** Warning: (vsim-3017) C:/grlib-gpl-1.0.19-b3188/lib/gaisler/vlog/EXEC_stage.v(167): [TFMPC] - Too few port connections. Expected 7, found 6.

#         Region: /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iexec_stage/MIPS_alu/muldiv_ff

# ** Warning: (vsim-3722) C:/grlib-gpl-1.0.19-b3188/lib/gaisler/vlog/EXEC_stage.v(167): [TFMPC] - Missing connection for port 'rdy'.

# ** Warning: (vsim-3017) C:/grlib-gpl-1.0.19-b3188/lib/gaisler/vlog/decode_pipe1.v(1982): [TFMPC] - Too few port connections. Expected 20, found 18.

#         Region: /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/decoder_pipe/idecoder

# ** Warning: (vsim-3722) C:/grlib-gpl-1.0.19-b3188/lib/gaisler/vlog/decode_pipe1.v(1982): [TFMPC] - Missing connection for port 'read_rs'.

# ** Warning: (vsim-3722) C:/grlib-gpl-1.0.19-b3188/lib/gaisler/vlog/decode_pipe1.v(1982): [TFMPC] - Missing connection for port 'read_rt'.

# .main_pane.mdi.interior.cs.vm.paneset.cli_2.wf.clip.cs.pw.wf

# LEON3 GR-XC3S-1500 Demonstration design

# GRLIB Version 1.0.19, build 3188

# Target technology: spartan3  ,  memory library: spartan3

# ahbctrl: AHB arbiter/multiplexer rev 1

# ahbctrl: Common I/O area disabled

# ahbctrl: AHB masters: 3, AHB slaves: 8

# ahbctrl: Configuration area at 0xfffff000, 4 kbyte

# ahbctrl: mst0: Gaisler Research        Leon3 SPARC V8 Processor

# ahbctrl: mst1: Gaisler Research        AHB Debug UART

# ahbctrl: mst2: Gaisler Research        JTAG Debug Link

# ahbctrl: slv0: European Space Agency   Leon2 Memory Controller

# ahbctrl:       memory at 0x00000000, size 512 Mbyte, cacheable, prefetch

# ahbctrl:       memory at 0x20000000, size 512 Mbyte

# ahbctrl:       memory at 0x40000000, size 1024 Mbyte, cacheable, prefetch

# ahbctrl: slv1: Gaisler Research        AHB/APB Bridge

# ahbctrl:       memory at 0x80000000, size 1 Mbyte

# apbctrl: APB Bridge at 0x80000000 rev 1

# apbctrl: slv0: European Space Agency   Leon2 Memory Controller

# apbctrl:       I/O ports at 0x80000000, size 256 byte

# apbctrl: slv1: Gaisler Research        Generic UART

# apbctrl:       I/O ports at 0x80000100, size 256 byte

# apbctrl: slv2: Gaisler Research        Multi-processor Interrupt Ctrl.

# apbctrl:       I/O ports at 0x80000200, size 256 byte

# apbctrl: slv7: Gaisler Research        AHB Debug UART

# apbctrl:       I/O ports at 0x80000700, size 256 byte

# irqmp: Multi-processor Interrupt Controller rev 3, #cpu 1, eirq 0

# apbuart1: Generic UART rev 1, fifo 4, irq 2

# ahbjtag AHB Debug JTAG rev 0

# ahbuart7: AHB Debug UART rev 0

# leon3_0: LEON3 SPARC V8 processor rev 0

# leon3_0: icache 1*4 kbyte, dcache 4*4 kbyte

# clkgen_spartan3e: spartan3/e sdram/pci clock generator, version 1

# clkgen_spartan3e: Frequency 50000 KHz, DCM divisor 4/5

# Compile of ulit.v was successful.

# Break key hit

# Break in Process gen_reset at C:/grlib-gpl-1.0.19-b3188/lib/tech/unisim/simprims/xilinx_simprims.vhd line 4605

# Simulation Breakpoint: Break in Process gen_reset at C:/grlib-gpl-1.0.19-b3188/lib/tech/unisim/simprims/xilinx_simprims.vhd line 4605

# MACRO ./modelsim.do PAUSED at line 13

do modelsim.do

# vsim -quiet work.testbench

# ** Warning: (vsim-3017) C:/grlib-gpl-1.0.19-b3188/lib/gaisler/vlog/RF_stage1.v(199): [TFMPC] - Too few port connections. Expected 4, found 3.

#         Region: /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iRF_stage/jack2

# ** Warning: (vsim-3722) C:/grlib-gpl-1.0.19-b3188/lib/gaisler/vlog/RF_stage1.v(199): [TFMPC] - Missing connection for port 'rd_o'.

# ** Warning: (vsim-3017) C:/grlib-gpl-1.0.19-b3188/lib/gaisler/vlog/EXEC_stage.v(167): [TFMPC] - Too few port connections. Expected 7, found 6.

#         Region: /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iexec_stage/MIPS_alu/muldiv_ff

# ** Warning: (vsim-3722) C:/grlib-gpl-1.0.19-b3188/lib/gaisler/vlog/EXEC_stage.v(167): [TFMPC] - Missing connection for port 'rdy'.

# ** Warning: (vsim-3017) C:/grlib-gpl-1.0.19-b3188/lib/gaisler/vlog/decode_pipe1.v(1982): [TFMPC] - Too few port connections. Expected 20, found 18.

#         Region: /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/decoder_pipe/idecoder

# ** Warning: (vsim-3722) C:/grlib-gpl-1.0.19-b3188/lib/gaisler/vlog/decode_pipe1.v(1982): [TFMPC] - Missing connection for port 'read_rs'.

# ** Warning: (vsim-3722) C:/grlib-gpl-1.0.19-b3188/lib/gaisler/vlog/decode_pipe1.v(1982): [TFMPC] - Missing connection for port 'read_rt'.

# .main_pane.mdi.interior.cs.vm.paneset.cli_2.wf.clip.cs.pw.wf

# LEON3 GR-XC3S-1500 Demonstration design

# GRLIB Version 1.0.19, build 3188

# Target technology: spartan3  ,  memory library: spartan3

# ahbctrl: AHB arbiter/multiplexer rev 1

# ahbctrl: Common I/O area disabled

# ahbctrl: AHB masters: 3, AHB slaves: 8

# ahbctrl: Configuration area at 0xfffff000, 4 kbyte

# ahbctrl: mst0: Gaisler Research        Leon3 SPARC V8 Processor

# ahbctrl: mst1: Gaisler Research        AHB Debug UART

# ahbctrl: mst2: Gaisler Research        JTAG Debug Link

# ahbctrl: slv0: European Space Agency   Leon2 Memory Controller

# ahbctrl:       memory at 0x00000000, size 512 Mbyte, cacheable, prefetch

# ahbctrl:       memory at 0x20000000, size 512 Mbyte

# ahbctrl:       memory at 0x40000000, size 1024 Mbyte, cacheable, prefetch

# ahbctrl: slv1: Gaisler Research        AHB/APB Bridge

# ahbctrl:       memory at 0x80000000, size 1 Mbyte

# apbctrl: APB Bridge at 0x80000000 rev 1

# apbctrl: slv0: European Space Agency   Leon2 Memory Controller

# apbctrl:       I/O ports at 0x80000000, size 256 byte

# apbctrl: slv1: Gaisler Research        Generic UART

# apbctrl:       I/O ports at 0x80000100, size 256 byte

# apbctrl: slv2: Gaisler Research        Multi-processor Interrupt Ctrl.

# apbctrl:       I/O ports at 0x80000200, size 256 byte

# apbctrl: slv7: Gaisler Research        AHB Debug UART

# apbctrl:       I/O ports at 0x80000700, size 256 byte

# irqmp: Multi-processor Interrupt Controller rev 3, #cpu 1, eirq 0

# apbuart1: Generic UART rev 1, fifo 4, irq 2

# ahbjtag AHB Debug JTAG rev 0

# ahbuart7: AHB Debug UART rev 0

# leon3_0: LEON3 SPARC V8 processor rev 0

# leon3_0: icache 1*4 kbyte, dcache 4*4 kbyte

# clkgen_spartan3e: spartan3/e sdram/pci clock generator, version 1

# clkgen_spartan3e: Frequency 50000 KHz, DCM divisor 4/5

# ** Failure: *** IU in error mode, simulation halted ***

#    Time: 5 ms  Iteration: 0  Process: /testbench/iuerr File: C:/grlib-gpl-1.0.19-b3188/designs/leon3-gr-xc3s-1500/testbench.vhd

# Break in Process iuerr at C:/grlib-gpl-1.0.19-b3188/designs/leon3-gr-xc3s-1500/testbench.vhd line 362

# Simulation Breakpoint: Break in Process iuerr at C:/grlib-gpl-1.0.19-b3188/designs/leon3-gr-xc3s-1500/testbench.vhd line 362

# MACRO ./modelsim.do PAUSED at line 13

# Compile of decode_pipe1.v was successful.

do modelsim.do

# vsim -quiet work.testbench

# ** Warning: (vsim-3017) C:/grlib-gpl-1.0.19-b3188/lib/gaisler/vlog/RF_stage1.v(199): [TFMPC] - Too few port connections. Expected 4, found 3.

#         Region: /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iRF_stage/jack2

# ** Warning: (vsim-3722) C:/grlib-gpl-1.0.19-b3188/lib/gaisler/vlog/RF_stage1.v(199): [TFMPC] - Missing connection for port 'rd_o'.

# ** Warning: (vsim-3017) C:/grlib-gpl-1.0.19-b3188/lib/gaisler/vlog/EXEC_stage.v(167): [TFMPC] - Too few port connections. Expected 7, found 6.

#         Region: /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iexec_stage/MIPS_alu/muldiv_ff

# ** Warning: (vsim-3722) C:/grlib-gpl-1.0.19-b3188/lib/gaisler/vlog/EXEC_stage.v(167): [TFMPC] - Missing connection for port 'rdy'.

# ** Warning: (vsim-3017) C:/grlib-gpl-1.0.19-b3188/lib/gaisler/vlog/decode_pipe1.v(1982): [TFMPC] - Too few port connections. Expected 20, found 18.

#         Region: /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/decoder_pipe/idecoder

# ** Warning: (vsim-3722) C:/grlib-gpl-1.0.19-b3188/lib/gaisler/vlog/decode_pipe1.v(1982): [TFMPC] - Missing connection for port 'read_rs'.

# ** Warning: (vsim-3722) C:/grlib-gpl-1.0.19-b3188/lib/gaisler/vlog/decode_pipe1.v(1982): [TFMPC] - Missing connection for port 'read_rt'.

# .main_pane.mdi.interior.cs.vm.paneset.cli_2.wf.clip.cs.pw.wf

# LEON3 GR-XC3S-1500 Demonstration design

# GRLIB Version 1.0.19, build 3188

# Target technology: spartan3  ,  memory library: spartan3

# ahbctrl: AHB arbiter/multiplexer rev 1

# ahbctrl: Common I/O area disabled

# ahbctrl: AHB masters: 3, AHB slaves: 8

# ahbctrl: Configuration area at 0xfffff000, 4 kbyte

# ahbctrl: mst0: Gaisler Research        Leon3 SPARC V8 Processor

# ahbctrl: mst1: Gaisler Research        AHB Debug UART

# ahbctrl: mst2: Gaisler Research        JTAG Debug Link

# ahbctrl: slv0: European Space Agency   Leon2 Memory Controller

# ahbctrl:       memory at 0x00000000, size 512 Mbyte, cacheable, prefetch

# ahbctrl:       memory at 0x20000000, size 512 Mbyte

# ahbctrl:       memory at 0x40000000, size 1024 Mbyte, cacheable, prefetch

# ahbctrl: slv1: Gaisler Research        AHB/APB Bridge

# ahbctrl:       memory at 0x80000000, size 1 Mbyte

# apbctrl: APB Bridge at 0x80000000 rev 1

# apbctrl: slv0: European Space Agency   Leon2 Memory Controller

# apbctrl:       I/O ports at 0x80000000, size 256 byte

# apbctrl: slv1: Gaisler Research        Generic UART

# apbctrl:       I/O ports at 0x80000100, size 256 byte

# apbctrl: slv2: Gaisler Research        Multi-processor Interrupt Ctrl.

# apbctrl:       I/O ports at 0x80000200, size 256 byte

# apbctrl: slv7: Gaisler Research        AHB Debug UART

# apbctrl:       I/O ports at 0x80000700, size 256 byte

# irqmp: Multi-processor Interrupt Controller rev 3, #cpu 1, eirq 0

# apbuart1: Generic UART rev 1, fifo 4, irq 2

# ahbjtag AHB Debug JTAG rev 0

# ahbuart7: AHB Debug UART rev 0

# leon3_0: LEON3 SPARC V8 processor rev 0

# leon3_0: icache 1*4 kbyte, dcache 4*4 kbyte

# clkgen_spartan3e: spartan3/e sdram/pci clock generator, version 1

# clkgen_spartan3e: Frequency 50000 KHz, DCM divisor 4/5

# ** Failure: *** IU in error mode, simulation halted ***

#    Time: 5 ms  Iteration: 0  Process: /testbench/iuerr File: C:/grlib-gpl-1.0.19-b3188/designs/leon3-gr-xc3s-1500/testbench.vhd

# Break in Process iuerr at C:/grlib-gpl-1.0.19-b3188/designs/leon3-gr-xc3s-1500/testbench.vhd line 362

# Simulation Breakpoint: Break in Process iuerr at C:/grlib-gpl-1.0.19-b3188/designs/leon3-gr-xc3s-1500/testbench.vhd line 362

# MACRO ./modelsim.do PAUSED at line 13

# Compile of ulit.v was successful.

# Compile of core1.v was successful.

do modelsim.do

# vsim -quiet work.testbench

# ** Warning: (vsim-3017) C:/grlib-gpl-1.0.19-b3188/lib/gaisler/vlog/RF_stage1.v(199): [TFMPC] - Too few port connections. Expected 4, found 3.

#         Region: /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iRF_stage/jack2

# ** Warning: (vsim-3722) C:/grlib-gpl-1.0.19-b3188/lib/gaisler/vlog/RF_stage1.v(199): [TFMPC] - Missing connection for port 'rd_o'.

# ** Warning: (vsim-3017) C:/grlib-gpl-1.0.19-b3188/lib/gaisler/vlog/EXEC_stage.v(167): [TFMPC] - Too few port connections. Expected 7, found 6.

#         Region: /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iexec_stage/MIPS_alu/muldiv_ff

# ** Warning: (vsim-3722) C:/grlib-gpl-1.0.19-b3188/lib/gaisler/vlog/EXEC_stage.v(167): [TFMPC] - Missing connection for port 'rdy'.

# ** Warning: (vsim-3017) C:/grlib-gpl-1.0.19-b3188/lib/gaisler/vlog/decode_pipe1.v(1982): [TFMPC] - Too few port connections. Expected 20, found 18.

#         Region: /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/decoder_pipe/idecoder

# ** Warning: (vsim-3722) C:/grlib-gpl-1.0.19-b3188/lib/gaisler/vlog/decode_pipe1.v(1982): [TFMPC] - Missing connection for port 'read_rs'.

# ** Warning: (vsim-3722) C:/grlib-gpl-1.0.19-b3188/lib/gaisler/vlog/decode_pipe1.v(1982): [TFMPC] - Missing connection for port 'read_rt'.

# .main_pane.mdi.interior.cs.vm.paneset.cli_2.wf.clip.cs.pw.wf

# LEON3 GR-XC3S-1500 Demonstration design

# GRLIB Version 1.0.19, build 3188

# Target technology: spartan3  ,  memory library: spartan3

# ahbctrl: AHB arbiter/multiplexer rev 1

# ahbctrl: Common I/O area disabled

# ahbctrl: AHB masters: 3, AHB slaves: 8

# ahbctrl: Configuration area at 0xfffff000, 4 kbyte

# ahbctrl: mst0: Gaisler Research        Leon3 SPARC V8 Processor

# ahbctrl: mst1: Gaisler Research        AHB Debug UART

# ahbctrl: mst2: Gaisler Research        JTAG Debug Link

# ahbctrl: slv0: European Space Agency   Leon2 Memory Controller

# ahbctrl:       memory at 0x00000000, size 512 Mbyte, cacheable, prefetch

# ahbctrl:       memory at 0x20000000, size 512 Mbyte

# ahbctrl:       memory at 0x40000000, size 1024 Mbyte, cacheable, prefetch

# ahbctrl: slv1: Gaisler Research        AHB/APB Bridge

# ahbctrl:       memory at 0x80000000, size 1 Mbyte

# apbctrl: APB Bridge at 0x80000000 rev 1

# apbctrl: slv0: European Space Agency   Leon2 Memory Controller

# apbctrl:       I/O ports at 0x80000000, size 256 byte

# apbctrl: slv1: Gaisler Research        Generic UART

# apbctrl:       I/O ports at 0x80000100, size 256 byte

# apbctrl: slv2: Gaisler Research        Multi-processor Interrupt Ctrl.

# apbctrl:       I/O ports at 0x80000200, size 256 byte

# apbctrl: slv7: Gaisler Research        AHB Debug UART

# apbctrl:       I/O ports at 0x80000700, size 256 byte

# irqmp: Multi-processor Interrupt Controller rev 3, #cpu 1, eirq 0

# apbuart1: Generic UART rev 1, fifo 4, irq 2

# ahbjtag AHB Debug JTAG rev 0

# ahbuart7: AHB Debug UART rev 0

# leon3_0: LEON3 SPARC V8 processor rev 0

# leon3_0: icache 1*4 kbyte, dcache 4*4 kbyte

# clkgen_spartan3e: spartan3/e sdram/pci clock generator, version 1

# clkgen_spartan3e: Frequency 50000 KHz, DCM divisor 4/5

# Break key hit

# Break in ForLoop loop at C:/grlib-gpl-1.0.19-b3188/lib/esa/memoryctrl/mctrl.vhd line 907