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URL https://opencores.org/ocsvn/mips_enhanced/mips_enhanced/trunk

Subversion Repositories mips_enhanced

[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [designs/] [leon3-gr-xc3s-1500/] [wave.do] - Blame information for rev 2

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Line No. Rev Author Line
1 2 dimamali 
onerror {resume}
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quietly WaveActivateNextPane {} 0
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add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/clk
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add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/rstn
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add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/holdn
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add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/ahbi
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add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/ahbo
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add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/ahbso
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add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/rfi
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add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/crami
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add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/iack_o
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add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/hclk
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add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/iack_o
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add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/dmem_ctl_ur1
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add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/clk
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add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/rst
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add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/zz_ins_i
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add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/dmem_data_ur_o
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add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/wb_din_o
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add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/rdaddra_o
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add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/hold
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add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/imds
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add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/dmds
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add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/pc_next
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add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/load
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add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/load_o
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add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/NET1375
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add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iRF_stage/BUS3237
194 
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iRF_stage/BUS5421
195 
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iRF_stage/BUS6061
196 
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iRF_stage/BUS6095
197 
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iRF_stage/CLK_NO
198 
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iRF_stage/INS_NO
199 
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iexec_stage/clk
200 
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iexec_stage/rst
201 
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iexec_stage/spc_cls_i
202 
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iexec_stage/alu_func
203 
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iexec_stage/dmem_fw_ctl
204 
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iexec_stage/ext_i
205 
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iexec_stage/fw_alu
206 
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iexec_stage/fw_dmem
207 
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iexec_stage/muxa_ctl_i
208 
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iexec_stage/muxa_fw_ctl
209 
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iexec_stage/muxb_ctl_i
210 
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iexec_stage/muxb_fw_ctl
211 
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iexec_stage/pc_i
212 
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iexec_stage/rs_i
213 
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iexec_stage/rt_i
214 
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iexec_stage/alu_ur_o
215 
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iexec_stage/dmem_data_ur_o
216 
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iexec_stage/zz_spc_o
217 
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iexec_stage/hold
218 
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iexec_stage/BUS2332
219 
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iexec_stage/BUS2446
220 
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iexec_stage/BUS468
221 
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iexec_stage/BUS476
222 
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/decoder_pipe/load
223 
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/decoder_pipe/rt1
224 
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/decoder_pipe/load_o
225 
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/decoder_pipe/clk
226 
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/decoder_pipe/id2ra_ctl_clr
227 
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/decoder_pipe/id2ra_ctl_cls
228 
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/decoder_pipe/ra2ex_ctl_clr
229 
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/decoder_pipe/ins_i
230 
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/decoder_pipe/alu_func_o
231 
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/decoder_pipe/alu_we_o
232 
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/decoder_pipe/cmp_ctl_o
233 
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/decoder_pipe/dmem_ctl_o
234 
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/decoder_pipe/dmem_ctl_ur_o
235 
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/decoder_pipe/ext_ctl_o
236 
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/decoder_pipe/fsm_dly
237 
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/decoder_pipe/muxa_ctl_o
238 
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/decoder_pipe/muxb_ctl_o
239 
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/decoder_pipe/pc_gen_ctl_o
240 
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/decoder_pipe/rd_sel_o
241 
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/decoder_pipe/wb_mux_ctl_o
242 
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/decoder_pipe/wb_we_o
243 
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/decoder_pipe/size
244 
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/decoder_pipe/hold
245 
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/decoder_pipe/asi
246 
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/decoder_pipe/BUS2040
247 
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/decoder_pipe/BUS2048
248 
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/decoder_pipe/BUS2056
249 
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/decoder_pipe/BUS2064
250 
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/decoder_pipe/BUS2072
251 
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/decoder_pipe/BUS2086
252 
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/decoder_pipe/BUS2094
253 
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/decoder_pipe/BUS2102
254 
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/decoder_pipe/BUS2110
255 
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/decoder_pipe/BUS2118
256 
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/decoder_pipe/BUS2126
257 
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iforward/alu_we
258 
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iforward/clk
259 
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iforward/mem_We
260 
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iforward/fw_alu_rn
261 
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iforward/fw_mem_rn
262 
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iforward/rns_i
263 
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iforward/rnt_i
264 
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iforward/alu_rs_fw
265 
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iforward/alu_rt_fw
266 
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iforward/cmp_rs_fw
267 
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iforward/cmp_rt_fw
268 
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iforward/dmem_fw
269 
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iforward/hold
270 
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iforward/BUS1345
271 
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iforward/BUS82
272 
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iforward/BUS937
273 
TreeUpdate [SetDefaultTree]
274 
WaveRestoreCursors {{Cursor 1} {0 ps} 0}
275 
configure wave -namecolwidth 150
276 
configure wave -valuecolwidth 100
277 
configure wave -justifyvalue left
278 
configure wave -signalnamewidth 0
279 
configure wave -snapdistance 10
280 
configure wave -datasetprefix 0
281 
configure wave -rowmargin 4
282 
configure wave -childrowmargin 2
283 
configure wave -gridoffset 0
284 
configure wave -gridperiod 1
285 
configure wave -griddelta 40
286 
configure wave -timeline 0
287 
configure wave -timelineunits ns
288 
update
289 
WaveRestoreZoom {4999998984 ps} {5000000267 ps}

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