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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [designs/] [leon3-memec-v2mb1000/] [tkconfig.h] - Blame information for rev 2

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#if defined CONFIG_SYN_INFERRED
#define CONFIG_SYN_TECH inferred
#elif defined CONFIG_SYN_RHUMC
#define CONFIG_SYN_TECH rhumc
#elif defined CONFIG_SYN_ATC18
#define CONFIG_SYN_TECH atc18
#elif defined CONFIG_SYN_AXCEL
#define CONFIG_SYN_TECH axcel
#elif defined CONFIG_SYN_PROASICPLUS
#define CONFIG_SYN_TECH proasic
#elif defined CONFIG_SYN_ALTERA
#define CONFIG_SYN_TECH altera
#elif defined CONFIG_SYN_IHP25
#define CONFIG_SYN_TECH ihp25
#elif defined CONFIG_SYN_IHP25RH
#define CONFIG_SYN_TECH ihp25rh
#elif defined CONFIG_SYN_LATTICE
#define CONFIG_SYN_TECH lattice
#elif defined CONFIG_SYN_PEREGRINE
#define CONFIG_SYN_TECH peregrine
#elif defined CONFIG_SYN_PROASIC
#define CONFIG_SYN_TECH proasic
#elif defined CONFIG_SYN_PROASIC3
#define CONFIG_SYN_TECH proasic3
#elif defined CONFIG_SYN_SPARTAN2
#define CONFIG_SYN_TECH virtex
#elif defined CONFIG_SYN_VIRTEX
#define CONFIG_SYN_TECH virtex
#elif defined CONFIG_SYN_VIRTEXE
#define CONFIG_SYN_TECH virtex
#elif defined CONFIG_SYN_SPARTAN3
#define CONFIG_SYN_TECH spartan3
#elif defined CONFIG_SYN_SPARTAN3E
#define CONFIG_SYN_TECH spartan3e
#elif defined CONFIG_SYN_VIRTEX2
#define CONFIG_SYN_TECH virtex2
#elif defined CONFIG_SYN_VIRTEX4
#define CONFIG_SYN_TECH virtex4
#elif defined CONFIG_SYN_VIRTEX5
#define CONFIG_SYN_TECH virtex5
#elif defined CONFIG_SYN_RH_LIB18T
#define CONFIG_SYN_TECH rhlib18t
#elif defined CONFIG_SYN_UT025CRH
#define CONFIG_SYN_TECH ut25
#elif defined CONFIG_SYN_CUSTOM1
#define CONFIG_SYN_TECH custom1
#else
#error "unknown target technology"
#endif
 
#if defined CONFIG_SYN_INFER_RAM
#define CFG_RAM_TECH inferred
#elif defined CONFIG_MEM_RHUMC
#define CFG_RAM_TECH rhumc
#elif defined CONFIG_MEM_VIRAGE
#define CFG_RAM_TECH memvirage
#elif defined CONFIG_MEM_ARTISAN
#define CFG_RAM_TECH memartisan
#elif defined CONFIG_MEM_CUSTOM1
#define CFG_RAM_TECH custom1
#else
#define CFG_RAM_TECH CONFIG_SYN_TECH
#endif
 
#if defined CONFIG_SYN_INFER_PADS
#define CFG_PAD_TECH inferred
#else
#define CFG_PAD_TECH CONFIG_SYN_TECH
#endif
 
#ifndef CONFIG_SYN_NO_ASYNC
#define CONFIG_SYN_NO_ASYNC 0
#endif
 
 
 
#if defined CONFIG_CLK_ALTDLL
#define CFG_CLK_TECH stratix
#elif defined CONFIG_CLK_HCLKBUF
#define CFG_CLK_TECH axcel
#elif defined CONFIG_CLK_LATDLL
#define CFG_CLK_TECH lattice
#elif defined CONFIG_CLK_CLKDLL
#define CFG_CLK_TECH virtex
#elif defined CONFIG_CLK_DCM
#define CFG_CLK_TECH virtex2
#elif defined CONFIG_CLK_LIB18T
#define CFG_CLK_TECH rhlib18t
#else
#define CFG_CLK_TECH inferred
#endif
 
#ifndef CONFIG_CLK_MUL
#define CONFIG_CLK_MUL 2
#endif
 
#ifndef CONFIG_CLK_DIV
#define CONFIG_CLK_DIV 2
#endif
 
#ifndef CONFIG_PCI_CLKDLL
#define CONFIG_PCI_CLKDLL 0
#endif
 
#ifndef CONFIG_PCI_SYSCLK
#define CONFIG_PCI_SYSCLK 0
#endif
 
#ifndef CONFIG_CLK_NOFB
#define CONFIG_CLK_NOFB 0
#endif
 
#ifndef CONFIG_LEON3
#define CONFIG_LEON3 0
#endif
 
#ifndef CONFIG_PROC_NUM
#define CONFIG_PROC_NUM 1
#endif
 
#ifndef CONFIG_IU_NWINDOWS
#define CONFIG_IU_NWINDOWS 8
#endif
 
#ifndef CONFIG_IU_RSTADDR
#define CONFIG_IU_RSTADDR 8
#endif
 
#ifndef CONFIG_IU_LDELAY
#define CONFIG_IU_LDELAY 1
#endif
 
#ifndef CONFIG_IU_WATCHPOINTS
#define CONFIG_IU_WATCHPOINTS 0
#endif
 
#ifdef CONFIG_IU_V8MULDIV
#ifdef CONFIG_IU_MUL_LATENCY_4
#define CFG_IU_V8 1
#else
#define CFG_IU_V8 2
#endif
#else
#define CFG_IU_V8 0
#endif
#ifndef CONFIG_PWD
#define CONFIG_PWD 0
#endif
 
#ifndef CONFIG_IU_MUL_MAC
#define CONFIG_IU_MUL_MAC 0
#endif
 
#ifndef CONFIG_IU_SVT
#define CONFIG_IU_SVT 0
#endif
 
#if defined CONFIG_FPU_GRFPC1
#define CONFIG_FPU_GRFPC 1
#elif defined CONFIG_FPU_GRFPC2
#define CONFIG_FPU_GRFPC 2
#else
#define CONFIG_FPU_GRFPC 0
#endif
 
#if defined CONFIG_FPU_GRFPU_INFMUL
#define CONFIG_FPU_GRFPU_MUL 0
#elif defined CONFIG_FPU_GRFPU_DWMUL
#define CONFIG_FPU_GRFPU_MUL 1
#elif defined CONFIG_FPU_GRFPU_MODGEN 
#define CONFIG_FPU_GRFPU_MUL 2
#else
#define CONFIG_FPU_GRFPU_MUL 0
#endif
 
#if defined CONFIG_FPU_GRFPU
#define CONFIG_FPU (1+CONFIG_FPU_GRFPU_MUL)
#elif defined CONFIG_FPU_MEIKO
#define CONFIG_FPU 15
#elif defined CONFIG_FPU_GRFPULITE
#define CONFIG_FPU (8+CONFIG_FPU_GRFPC)
#else
#define CONFIG_FPU 0
#endif
 
#ifndef CONFIG_ICACHE_ENABLE
#define CONFIG_ICACHE_ENABLE 0
#endif
 
#if defined CONFIG_ICACHE_ASSO1
#define CFG_IU_ISETS 1
#elif defined CONFIG_ICACHE_ASSO2
#define CFG_IU_ISETS 2
#elif defined CONFIG_ICACHE_ASSO3
#define CFG_IU_ISETS 3
#elif defined CONFIG_ICACHE_ASSO4
#define CFG_IU_ISETS 4
#else
#define CFG_IU_ISETS 1
#endif
 
#if defined CONFIG_ICACHE_SZ1
#define CFG_ICACHE_SZ 1
#elif defined CONFIG_ICACHE_SZ2
#define CFG_ICACHE_SZ 2
#elif defined CONFIG_ICACHE_SZ4
#define CFG_ICACHE_SZ 4
#elif defined CONFIG_ICACHE_SZ8
#define CFG_ICACHE_SZ 8
#elif defined CONFIG_ICACHE_SZ16
#define CFG_ICACHE_SZ 16
#elif defined CONFIG_ICACHE_SZ32
#define CFG_ICACHE_SZ 32
#elif defined CONFIG_ICACHE_SZ64
#define CFG_ICACHE_SZ 64
#elif defined CONFIG_ICACHE_SZ128
#define CFG_ICACHE_SZ 128
#elif defined CONFIG_ICACHE_SZ256
#define CFG_ICACHE_SZ 256
#else
#define CFG_ICACHE_SZ 1
#endif
 
#ifdef CONFIG_ICACHE_LZ16
#define CFG_ILINE_SZ 4
#else
#define CFG_ILINE_SZ 8
#endif
 
#if defined CONFIG_ICACHE_ALGORND
#define CFG_ICACHE_ALGORND 2
#elif defined CONFIG_ICACHE_ALGOLRR
#define CFG_ICACHE_ALGORND 1
#else
#define CFG_ICACHE_ALGORND 0
#endif
 
#ifndef CONFIG_ICACHE_LOCK
#define CONFIG_ICACHE_LOCK 0
#endif
 
#ifndef CONFIG_ICACHE_LRAM
#define CONFIG_ICACHE_LRAM 0
#endif
 
#ifndef CONFIG_ICACHE_LRSTART
#define CONFIG_ICACHE_LRSTART 8E
#endif
 
#if defined CONFIG_ICACHE_LRAM_SZ2
#define CFG_ILRAM_SIZE 2
#elif defined CONFIG_ICACHE_LRAM_SZ4
#define CFG_ILRAM_SIZE 4
#elif defined CONFIG_ICACHE_LRAM_SZ8
#define CFG_ILRAM_SIZE 8
#elif defined CONFIG_ICACHE_LRAM_SZ16
#define CFG_ILRAM_SIZE 16
#elif defined CONFIG_ICACHE_LRAM_SZ32
#define CFG_ILRAM_SIZE 32
#elif defined CONFIG_ICACHE_LRAM_SZ64
#define CFG_ILRAM_SIZE 64
#elif defined CONFIG_ICACHE_LRAM_SZ128
#define CFG_ILRAM_SIZE 128
#elif defined CONFIG_ICACHE_LRAM_SZ256
#define CFG_ILRAM_SIZE 256
#else
#define CFG_ILRAM_SIZE 1
#endif
 
 
#ifndef CONFIG_DCACHE_ENABLE
#define CONFIG_DCACHE_ENABLE 0
#endif
 
#if defined CONFIG_DCACHE_ASSO1
#define CFG_IU_DSETS 1
#elif defined CONFIG_DCACHE_ASSO2
#define CFG_IU_DSETS 2
#elif defined CONFIG_DCACHE_ASSO3
#define CFG_IU_DSETS 3
#elif defined CONFIG_DCACHE_ASSO4
#define CFG_IU_DSETS 4
#else
#define CFG_IU_DSETS 1
#endif
 
#if defined CONFIG_DCACHE_SZ1
#define CFG_DCACHE_SZ 1
#elif defined CONFIG_DCACHE_SZ2
#define CFG_DCACHE_SZ 2
#elif defined CONFIG_DCACHE_SZ4
#define CFG_DCACHE_SZ 4
#elif defined CONFIG_DCACHE_SZ8
#define CFG_DCACHE_SZ 8
#elif defined CONFIG_DCACHE_SZ16
#define CFG_DCACHE_SZ 16
#elif defined CONFIG_DCACHE_SZ32
#define CFG_DCACHE_SZ 32
#elif defined CONFIG_DCACHE_SZ64
#define CFG_DCACHE_SZ 64
#elif defined CONFIG_DCACHE_SZ128
#define CFG_DCACHE_SZ 128
#elif defined CONFIG_DCACHE_SZ256
#define CFG_DCACHE_SZ 256
#else
#define CFG_DCACHE_SZ 1
#endif
 
#ifdef CONFIG_DCACHE_LZ16
#define CFG_DLINE_SZ 4
#else
#define CFG_DLINE_SZ 8
#endif
 
#if defined CONFIG_DCACHE_ALGORND
#define CFG_DCACHE_ALGORND 2
#elif defined CONFIG_DCACHE_ALGOLRR
#define CFG_DCACHE_ALGORND 1
#else
#define CFG_DCACHE_ALGORND 0
#endif
 
#ifndef CONFIG_DCACHE_LOCK
#define CONFIG_DCACHE_LOCK 0
#endif
 
#ifndef CONFIG_DCACHE_SNOOP
#define CONFIG_DCACHE_SNOOP 0
#endif
 
#ifndef CONFIG_DCACHE_SNOOP_FAST
#define CONFIG_DCACHE_SNOOP_FAST 0
#endif
 
#ifndef CONFIG_CACHE_FIXED
#define CONFIG_CACHE_FIXED 0
#endif
 
#ifndef CONFIG_DCACHE_LRAM
#define CONFIG_DCACHE_LRAM 0
#endif
 
#ifndef CONFIG_DCACHE_LRSTART
#define CONFIG_DCACHE_LRSTART 8F
#endif
 
#if defined CONFIG_DCACHE_LRAM_SZ2
#define CFG_DLRAM_SIZE 2
#elif defined CONFIG_DCACHE_LRAM_SZ4
#define CFG_DLRAM_SIZE 4
#elif defined CONFIG_DCACHE_LRAM_SZ8
#define CFG_DLRAM_SIZE 8
#elif defined CONFIG_DCACHE_LRAM_SZ16
#define CFG_DLRAM_SIZE 16
#elif defined CONFIG_DCACHE_LRAM_SZ32
#define CFG_DLRAM_SIZE 32
#elif defined CONFIG_DCACHE_LRAM_SZ64
#define CFG_DLRAM_SIZE 64
#elif defined CONFIG_DCACHE_LRAM_SZ128
#define CFG_DLRAM_SIZE 128
#elif defined CONFIG_DCACHE_LRAM_SZ256
#define CFG_DLRAM_SIZE 256
#else
#define CFG_DLRAM_SIZE 1
#endif
 
 
#ifdef CONFIG_MMU_ENABLE
#define CONFIG_MMUEN 1
 
#ifdef CONFIG_MMU_SPLIT
#define CONFIG_TLB_TYPE 0
#endif
#ifdef CONFIG_MMU_COMBINED
#define CONFIG_TLB_TYPE 1
#endif
 
#ifdef CONFIG_MMU_REPARRAY
#define CONFIG_TLB_REP 0
#endif
#ifdef CONFIG_MMU_REPINCREMENT
#define CONFIG_TLB_REP 1
#endif
 
#ifdef CONFIG_MMU_I2 
#define CONFIG_ITLBNUM 2
#endif
#ifdef CONFIG_MMU_I4 
#define CONFIG_ITLBNUM 4
#endif
#ifdef CONFIG_MMU_I8 
#define CONFIG_ITLBNUM 8
#endif
#ifdef CONFIG_MMU_I16 
#define CONFIG_ITLBNUM 16
#endif
#ifdef CONFIG_MMU_I32
#define CONFIG_ITLBNUM 32
#endif
 
#define CONFIG_DTLBNUM 2
#ifdef CONFIG_MMU_D2 
#undef CONFIG_DTLBNUM 
#define CONFIG_DTLBNUM 2
#endif
#ifdef CONFIG_MMU_D4 
#undef CONFIG_DTLBNUM 
#define CONFIG_DTLBNUM 4
#endif
#ifdef CONFIG_MMU_D8 
#undef CONFIG_DTLBNUM 
#define CONFIG_DTLBNUM 8
#endif
#ifdef CONFIG_MMU_D16 
#undef CONFIG_DTLBNUM 
#define CONFIG_DTLBNUM 16
#endif
#ifdef CONFIG_MMU_D32
#undef CONFIG_DTLBNUM 
#define CONFIG_DTLBNUM 32
#endif
 
#ifndef CONFIG_MMU_MMUSNOOP
#define CONFIG_DCACHE_MMUSNOOP 0
#else 
#define CONFIG_DCACHE_MMUSNOOP 4
#endif
 
#else
#define CONFIG_MMUEN 0
#define CONFIG_ITLBNUM 2
#define CONFIG_DTLBNUM 2
#define CONFIG_TLB_TYPE 1
#define CONFIG_TLB_REP 1
#define CONFIG_DCACHE_MMUSNOOP 0
#endif
 
#ifndef CONFIG_DSU_ENABLE
#define CONFIG_DSU_ENABLE 0
#endif
 
#if defined CONFIG_DSU_ITRACESZ1
#define CFG_DSU_ITB 1
#elif CONFIG_DSU_ITRACESZ2
#define CFG_DSU_ITB 2
#elif CONFIG_DSU_ITRACESZ4
#define CFG_DSU_ITB 4
#elif CONFIG_DSU_ITRACESZ8
#define CFG_DSU_ITB 8
#elif CONFIG_DSU_ITRACESZ16
#define CFG_DSU_ITB 16
#else
#define CFG_DSU_ITB 0
#endif
 
#if defined CONFIG_DSU_ATRACESZ1
#define CFG_DSU_ATB 1
#elif CONFIG_DSU_ATRACESZ2
#define CFG_DSU_ATB 2
#elif CONFIG_DSU_ATRACESZ4
#define CFG_DSU_ATB 4
#elif CONFIG_DSU_ATRACESZ8
#define CFG_DSU_ATB 8
#elif CONFIG_DSU_ATRACESZ16
#define CFG_DSU_ATB 16
#else
#define CFG_DSU_ATB 0
#endif
 
#ifdef CONFIG_DEBUG_PC32
#define CFG_DEBUG_PC32 0 
#else
#define CFG_DEBUG_PC32 2
#endif
#ifndef CONFIG_IU_DISAS
#define CONFIG_IU_DISAS 0
#endif
#ifndef CONFIG_IU_DISAS_NET
#define CONFIG_IU_DISAS_NET 0
#endif
 
#ifndef CONFIG_AHB_SPLIT
#define CONFIG_AHB_SPLIT 0
#endif
 
#ifndef CONFIG_AHB_RROBIN
#define CONFIG_AHB_RROBIN 0
#endif
 
#ifndef CONFIG_AHB_IOADDR
#define CONFIG_AHB_IOADDR FFF
#endif
 
#ifndef CONFIG_APB_HADDR
#define CONFIG_APB_HADDR 800
#endif
 
#ifndef CONFIG_DSU_UART
#define CONFIG_DSU_UART 0
#endif
 
 
#ifndef CONFIG_DSU_JTAG
#define CONFIG_DSU_JTAG 0
#endif
 
#ifndef CONFIG_DSU_ETH
#define CONFIG_DSU_ETH 0
#endif
 
#ifndef CONFIG_DSU_IPMSB
#define CONFIG_DSU_IPMSB C0A8
#endif
 
#ifndef CONFIG_DSU_IPLSB
#define CONFIG_DSU_IPLSB 0033
#endif
 
#ifndef CONFIG_DSU_ETHMSB
#define CONFIG_DSU_ETHMSB 00007A
#endif
 
#ifndef CONFIG_DSU_ETHLSB
#define CONFIG_DSU_ETHLSB CC0001
#endif
 
#if defined CONFIG_DSU_ETHSZ1
#define CFG_DSU_ETHB 1
#elif CONFIG_DSU_ETHSZ2
#define CFG_DSU_ETHB 2
#elif CONFIG_DSU_ETHSZ4
#define CFG_DSU_ETHB 4
#elif CONFIG_DSU_ETHSZ8
#define CFG_DSU_ETHB 8
#elif CONFIG_DSU_ETHSZ16
#define CFG_DSU_ETHB 16
#elif CONFIG_DSU_ETHSZ32
#define CFG_DSU_ETHB 32
#else
#define CFG_DSU_ETHB 1
#endif
 
#ifndef CONFIG_MCTRL_LEON2
#define CONFIG_MCTRL_LEON2 0
#endif
 
#ifndef CONFIG_MCTRL_SDRAM
#define CONFIG_MCTRL_SDRAM 0
#endif
 
#ifndef CONFIG_MCTRL_SDRAM_SEPBUS
#define CONFIG_MCTRL_SDRAM_SEPBUS 0
#endif
 
#ifndef CONFIG_MCTRL_SDRAM_INVCLK
#define CONFIG_MCTRL_SDRAM_INVCLK 0
#endif
 
#ifndef CONFIG_MCTRL_SDRAM_BUS64
#define CONFIG_MCTRL_SDRAM_BUS64 0
#endif
 
#ifndef CONFIG_MCTRL_8BIT
#define CONFIG_MCTRL_8BIT 0
#endif
 
#ifndef CONFIG_MCTRL_16BIT
#define CONFIG_MCTRL_16BIT 0
#endif
 
#ifndef CONFIG_MCTRL_5CS
#define CONFIG_MCTRL_5CS 0
#endif
 
#ifndef CONFIG_MCTRL_EDAC
#define CONFIG_MCTRL_EDAC 0
#endif
 
#ifndef CONFIG_MCTRL_PAGE
#define CONFIG_MCTRL_PAGE 0
#endif
 
#ifndef CONFIG_MCTRL_PROGPAGE
#define CONFIG_MCTRL_PROGPAGE 0
#endif
 
#ifndef CONFIG_DDRSP
#define CONFIG_DDRSP 0
#endif
 
#ifndef CONFIG_DDRSP_INIT
#define CONFIG_DDRSP_INIT 0
#endif
 
#ifndef CONFIG_DDRSP_FREQ
#define CONFIG_DDRSP_FREQ 100
#endif
 
#ifndef CONFIG_DDRSP_COL
#define CONFIG_DDRSP_COL 9
#endif
 
#ifndef CONFIG_DDRSP_MBYTE
#define CONFIG_DDRSP_MBYTE 8
#endif
 
#ifndef CONFIG_DDRSP_RSKEW
#define CONFIG_DDRSP_RSKEW 0
#endif
#ifndef CONFIG_AHBROM_ENABLE
#define CONFIG_AHBROM_ENABLE 0
#endif
 
#ifndef CONFIG_AHBROM_START
#define CONFIG_AHBROM_START 000
#endif
 
#ifndef CONFIG_AHBROM_PIPE
#define CONFIG_AHBROM_PIPE 0
#endif
 
#if (CONFIG_AHBROM_START == 0) && (CONFIG_AHBROM_ENABLE == 1)
#define CONFIG_ROM_START 100
#else
#define CONFIG_ROM_START 000
#endif
 
 
#ifndef CONFIG_AHBRAM_ENABLE
#define CONFIG_AHBRAM_ENABLE 0
#endif
 
#ifndef CONFIG_AHBRAM_START
#define CONFIG_AHBRAM_START A00
#endif
 
#if defined CONFIG_AHBRAM_SZ1
#define CFG_AHBRAMSZ 1
#elif CONFIG_AHBRAM_SZ2
#define CFG_AHBRAMSZ 2
#elif CONFIG_AHBRAM_SZ4
#define CFG_AHBRAMSZ 4
#elif CONFIG_AHBRAM_SZ8
#define CFG_AHBRAMSZ 8
#elif CONFIG_AHBRAM_SZ16
#define CFG_AHBRAMSZ 16
#elif CONFIG_AHBRAM_SZ32
#define CFG_AHBRAMSZ 32
#elif CONFIG_AHBRAM_SZ64
#define CFG_AHBRAMSZ 64
#else
#define CFG_AHBRAMSZ 1
#endif
 
#ifndef CONFIG_GRETH_ENABLE
#define CONFIG_GRETH_ENABLE 0
#endif
 
#ifndef CONFIG_GRETH_GIGA
#define CONFIG_GRETH_GIGA 0
#endif
 
#if defined CONFIG_GRETH_FIFO4
#define CFG_GRETH_FIFO 4
#elif defined CONFIG_GRETH_FIFO8
#define CFG_GRETH_FIFO 8
#elif defined CONFIG_GRETH_FIFO16
#define CFG_GRETH_FIFO 16
#elif defined CONFIG_GRETH_FIFO32
#define CFG_GRETH_FIFO 32
#elif defined CONFIG_GRETH_FIFO64
#define CFG_GRETH_FIFO 64
#else
#define CFG_GRETH_FIFO 8
#endif
 
#ifndef CONFIG_UART1_ENABLE
#define CONFIG_UART1_ENABLE 0
#endif
 
#if defined CONFIG_UA1_FIFO1
#define CFG_UA1_FIFO 1
#elif defined CONFIG_UA1_FIFO2
#define CFG_UA1_FIFO 2
#elif defined CONFIG_UA1_FIFO4
#define CFG_UA1_FIFO 4
#elif defined CONFIG_UA1_FIFO8
#define CFG_UA1_FIFO 8
#elif defined CONFIG_UA1_FIFO16
#define CFG_UA1_FIFO 16
#elif defined CONFIG_UA1_FIFO32
#define CFG_UA1_FIFO 32
#else
#define CFG_UA1_FIFO 1
#endif
 
#ifndef CONFIG_IRQ3_ENABLE
#define CONFIG_IRQ3_ENABLE 0
#endif
#ifndef CONFIG_GPT_ENABLE
#define CONFIG_GPT_ENABLE 0
#endif
 
#ifndef CONFIG_GPT_NTIM
#define CONFIG_GPT_NTIM 1
#endif
 
#ifndef CONFIG_GPT_SW
#define CONFIG_GPT_SW 8
#endif
 
#ifndef CONFIG_GPT_TW
#define CONFIG_GPT_TW 8
#endif
 
#ifndef CONFIG_GPT_IRQ
#define CONFIG_GPT_IRQ 8
#endif
 
#ifndef CONFIG_GPT_SEPIRQ
#define CONFIG_GPT_SEPIRQ 0
#endif
#ifndef CONFIG_GPT_ENABLE
#define CONFIG_GPT_ENABLE 0
#endif
 
#ifndef CONFIG_GPT_NTIM
#define CONFIG_GPT_NTIM 1
#endif
 
#ifndef CONFIG_GPT_SW
#define CONFIG_GPT_SW 8
#endif
 
#ifndef CONFIG_GPT_TW
#define CONFIG_GPT_TW 8
#endif
 
#ifndef CONFIG_GPT_IRQ
#define CONFIG_GPT_IRQ 8
#endif
 
#ifndef CONFIG_GPT_SEPIRQ
#define CONFIG_GPT_SEPIRQ 0
#endif
 
#ifndef CONFIG_GPT_WDOGEN
#define CONFIG_GPT_WDOGEN 0
#endif
 
#ifndef CONFIG_GPT_WDOG
#define CONFIG_GPT_WDOG 0
#endif
 
#ifndef CONFIG_GRGPIO_ENABLE
#define CONFIG_GRGPIO_ENABLE 0
#endif
#ifndef CONFIG_GRGPIO_IMASK
#define CONFIG_GRGPIO_IMASK 0000
#endif
#ifndef CONFIG_GRGPIO_WIDTH
#define CONFIG_GRGPIO_WIDTH 1
#endif
 
#ifndef CONFIG_VGA_ENABLE
#define CONFIG_VGA_ENABLE 0
#endif
#ifndef CONFIG_SVGA_ENABLE
#define CONFIG_SVGA_ENABLE 0
#endif
#ifndef CONFIG_KBD_ENABLE
#define CONFIG_KBD_ENABLE 0
#endif
 
 
#ifndef CONFIG_DEBUG_UART
#define CONFIG_DEBUG_UART 0
#endif

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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [designs/] [leon3-memec-v2mb1000/] [tkconfig.h] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	dimamali	`#if defined CONFIG_SYN_INFERRED`
2			`#define CONFIG_SYN_TECH inferred`
3			`#elif defined CONFIG_SYN_RHUMC`
4			`#define CONFIG_SYN_TECH rhumc`
5			`#elif defined CONFIG_SYN_ATC18`
6			`#define CONFIG_SYN_TECH atc18`
7			`#elif defined CONFIG_SYN_AXCEL`
8			`#define CONFIG_SYN_TECH axcel`
9			`#elif defined CONFIG_SYN_PROASICPLUS`
10			`#define CONFIG_SYN_TECH proasic`
11			`#elif defined CONFIG_SYN_ALTERA`
12			`#define CONFIG_SYN_TECH altera`
13			`#elif defined CONFIG_SYN_IHP25`
14			`#define CONFIG_SYN_TECH ihp25`
15			`#elif defined CONFIG_SYN_IHP25RH`
16			`#define CONFIG_SYN_TECH ihp25rh`
17			`#elif defined CONFIG_SYN_LATTICE`
18			`#define CONFIG_SYN_TECH lattice`
19			`#elif defined CONFIG_SYN_PEREGRINE`
20			`#define CONFIG_SYN_TECH peregrine`
21			`#elif defined CONFIG_SYN_PROASIC`
22			`#define CONFIG_SYN_TECH proasic`
23			`#elif defined CONFIG_SYN_PROASIC3`
24			`#define CONFIG_SYN_TECH proasic3`
25			`#elif defined CONFIG_SYN_SPARTAN2`
26			`#define CONFIG_SYN_TECH virtex`
27			`#elif defined CONFIG_SYN_VIRTEX`
28			`#define CONFIG_SYN_TECH virtex`
29			`#elif defined CONFIG_SYN_VIRTEXE`
30			`#define CONFIG_SYN_TECH virtex`
31			`#elif defined CONFIG_SYN_SPARTAN3`
32			`#define CONFIG_SYN_TECH spartan3`
33			`#elif defined CONFIG_SYN_SPARTAN3E`
34			`#define CONFIG_SYN_TECH spartan3e`
35			`#elif defined CONFIG_SYN_VIRTEX2`
36			`#define CONFIG_SYN_TECH virtex2`
37			`#elif defined CONFIG_SYN_VIRTEX4`
38			`#define CONFIG_SYN_TECH virtex4`
39			`#elif defined CONFIG_SYN_VIRTEX5`
40			`#define CONFIG_SYN_TECH virtex5`
41			`#elif defined CONFIG_SYN_RH_LIB18T`
42			`#define CONFIG_SYN_TECH rhlib18t`
43			`#elif defined CONFIG_SYN_UT025CRH`
44			`#define CONFIG_SYN_TECH ut25`
45			`#elif defined CONFIG_SYN_CUSTOM1`
46			`#define CONFIG_SYN_TECH custom1`
47			`#else`
48			`#error "unknown target technology"`
49			`#endif`
50
51			`#if defined CONFIG_SYN_INFER_RAM`
52			`#define CFG_RAM_TECH inferred`
53			`#elif defined CONFIG_MEM_RHUMC`
54			`#define CFG_RAM_TECH rhumc`
55			`#elif defined CONFIG_MEM_VIRAGE`
56			`#define CFG_RAM_TECH memvirage`
57			`#elif defined CONFIG_MEM_ARTISAN`
58			`#define CFG_RAM_TECH memartisan`
59			`#elif defined CONFIG_MEM_CUSTOM1`
60			`#define CFG_RAM_TECH custom1`
61			`#else`
62			`#define CFG_RAM_TECH CONFIG_SYN_TECH`
63			`#endif`
64
65			`#if defined CONFIG_SYN_INFER_PADS`
66			`#define CFG_PAD_TECH inferred`
67			`#else`
68			`#define CFG_PAD_TECH CONFIG_SYN_TECH`
69			`#endif`
70
71			`#ifndef CONFIG_SYN_NO_ASYNC`
72			`#define CONFIG_SYN_NO_ASYNC 0`
73			`#endif`
74
75
76
77			`#if defined CONFIG_CLK_ALTDLL`
78			`#define CFG_CLK_TECH stratix`
79			`#elif defined CONFIG_CLK_HCLKBUF`
80			`#define CFG_CLK_TECH axcel`
81			`#elif defined CONFIG_CLK_LATDLL`
82			`#define CFG_CLK_TECH lattice`
83			`#elif defined CONFIG_CLK_CLKDLL`
84			`#define CFG_CLK_TECH virtex`
85			`#elif defined CONFIG_CLK_DCM`
86			`#define CFG_CLK_TECH virtex2`
87			`#elif defined CONFIG_CLK_LIB18T`
88			`#define CFG_CLK_TECH rhlib18t`
89			`#else`
90			`#define CFG_CLK_TECH inferred`
91			`#endif`
92
93			`#ifndef CONFIG_CLK_MUL`
94			`#define CONFIG_CLK_MUL 2`
95			`#endif`
96
97			`#ifndef CONFIG_CLK_DIV`
98			`#define CONFIG_CLK_DIV 2`
99			`#endif`
100
101			`#ifndef CONFIG_PCI_CLKDLL`
102			`#define CONFIG_PCI_CLKDLL 0`
103			`#endif`
104
105			`#ifndef CONFIG_PCI_SYSCLK`
106			`#define CONFIG_PCI_SYSCLK 0`
107			`#endif`
108
109			`#ifndef CONFIG_CLK_NOFB`
110			`#define CONFIG_CLK_NOFB 0`
111			`#endif`
112
113			`#ifndef CONFIG_LEON3`
114			`#define CONFIG_LEON3 0`
115			`#endif`
116
117			`#ifndef CONFIG_PROC_NUM`
118			`#define CONFIG_PROC_NUM 1`
119			`#endif`
120
121			`#ifndef CONFIG_IU_NWINDOWS`
122			`#define CONFIG_IU_NWINDOWS 8`
123			`#endif`
124
125			`#ifndef CONFIG_IU_RSTADDR`
126			`#define CONFIG_IU_RSTADDR 8`
127			`#endif`
128
129			`#ifndef CONFIG_IU_LDELAY`
130			`#define CONFIG_IU_LDELAY 1`
131			`#endif`
132
133			`#ifndef CONFIG_IU_WATCHPOINTS`
134			`#define CONFIG_IU_WATCHPOINTS 0`
135			`#endif`
136
137			`#ifdef CONFIG_IU_V8MULDIV`
138			`#ifdef CONFIG_IU_MUL_LATENCY_4`
139			`#define CFG_IU_V8 1`
140			`#else`
141			`#define CFG_IU_V8 2`
142			`#endif`
143			`#else`
144			`#define CFG_IU_V8 0`
145			`#endif`
146			`#ifndef CONFIG_PWD`
147			`#define CONFIG_PWD 0`
148			`#endif`
149
150			`#ifndef CONFIG_IU_MUL_MAC`
151			`#define CONFIG_IU_MUL_MAC 0`
152			`#endif`
153
154			`#ifndef CONFIG_IU_SVT`
155			`#define CONFIG_IU_SVT 0`
156			`#endif`
157
158			`#if defined CONFIG_FPU_GRFPC1`
159			`#define CONFIG_FPU_GRFPC 1`
160			`#elif defined CONFIG_FPU_GRFPC2`
161			`#define CONFIG_FPU_GRFPC 2`
162			`#else`
163			`#define CONFIG_FPU_GRFPC 0`
164			`#endif`
165
166			`#if defined CONFIG_FPU_GRFPU_INFMUL`
167			`#define CONFIG_FPU_GRFPU_MUL 0`
168			`#elif defined CONFIG_FPU_GRFPU_DWMUL`
169			`#define CONFIG_FPU_GRFPU_MUL 1`
170			`#elif defined CONFIG_FPU_GRFPU_MODGEN`
171			`#define CONFIG_FPU_GRFPU_MUL 2`
172			`#else`
173			`#define CONFIG_FPU_GRFPU_MUL 0`
174			`#endif`
175
176			`#if defined CONFIG_FPU_GRFPU`
177			`#define CONFIG_FPU (1+CONFIG_FPU_GRFPU_MUL)`
178			`#elif defined CONFIG_FPU_MEIKO`
179			`#define CONFIG_FPU 15`
180			`#elif defined CONFIG_FPU_GRFPULITE`
181			`#define CONFIG_FPU (8+CONFIG_FPU_GRFPC)`
182			`#else`
183			`#define CONFIG_FPU 0`
184			`#endif`
185
186			`#ifndef CONFIG_ICACHE_ENABLE`
187			`#define CONFIG_ICACHE_ENABLE 0`
188			`#endif`
189
190			`#if defined CONFIG_ICACHE_ASSO1`
191			`#define CFG_IU_ISETS 1`
192			`#elif defined CONFIG_ICACHE_ASSO2`
193			`#define CFG_IU_ISETS 2`
194			`#elif defined CONFIG_ICACHE_ASSO3`
195			`#define CFG_IU_ISETS 3`
196			`#elif defined CONFIG_ICACHE_ASSO4`
197			`#define CFG_IU_ISETS 4`
198			`#else`
199			`#define CFG_IU_ISETS 1`
200			`#endif`
201
202			`#if defined CONFIG_ICACHE_SZ1`
203			`#define CFG_ICACHE_SZ 1`
204			`#elif defined CONFIG_ICACHE_SZ2`
205			`#define CFG_ICACHE_SZ 2`
206			`#elif defined CONFIG_ICACHE_SZ4`
207			`#define CFG_ICACHE_SZ 4`
208			`#elif defined CONFIG_ICACHE_SZ8`
209			`#define CFG_ICACHE_SZ 8`
210			`#elif defined CONFIG_ICACHE_SZ16`
211			`#define CFG_ICACHE_SZ 16`
212			`#elif defined CONFIG_ICACHE_SZ32`
213			`#define CFG_ICACHE_SZ 32`
214			`#elif defined CONFIG_ICACHE_SZ64`
215			`#define CFG_ICACHE_SZ 64`
216			`#elif defined CONFIG_ICACHE_SZ128`
217			`#define CFG_ICACHE_SZ 128`
218			`#elif defined CONFIG_ICACHE_SZ256`
219			`#define CFG_ICACHE_SZ 256`
220			`#else`
221			`#define CFG_ICACHE_SZ 1`
222			`#endif`
223
224			`#ifdef CONFIG_ICACHE_LZ16`
225			`#define CFG_ILINE_SZ 4`
226			`#else`
227			`#define CFG_ILINE_SZ 8`
228			`#endif`
229
230			`#if defined CONFIG_ICACHE_ALGORND`
231			`#define CFG_ICACHE_ALGORND 2`
232			`#elif defined CONFIG_ICACHE_ALGOLRR`
233			`#define CFG_ICACHE_ALGORND 1`
234			`#else`
235			`#define CFG_ICACHE_ALGORND 0`
236			`#endif`
237
238			`#ifndef CONFIG_ICACHE_LOCK`
239			`#define CONFIG_ICACHE_LOCK 0`
240			`#endif`
241
242			`#ifndef CONFIG_ICACHE_LRAM`
243			`#define CONFIG_ICACHE_LRAM 0`
244			`#endif`
245
246			`#ifndef CONFIG_ICACHE_LRSTART`
247			`#define CONFIG_ICACHE_LRSTART 8E`
248			`#endif`
249
250			`#if defined CONFIG_ICACHE_LRAM_SZ2`
251			`#define CFG_ILRAM_SIZE 2`
252			`#elif defined CONFIG_ICACHE_LRAM_SZ4`
253			`#define CFG_ILRAM_SIZE 4`
254			`#elif defined CONFIG_ICACHE_LRAM_SZ8`
255			`#define CFG_ILRAM_SIZE 8`
256			`#elif defined CONFIG_ICACHE_LRAM_SZ16`
257			`#define CFG_ILRAM_SIZE 16`
258			`#elif defined CONFIG_ICACHE_LRAM_SZ32`
259			`#define CFG_ILRAM_SIZE 32`
260			`#elif defined CONFIG_ICACHE_LRAM_SZ64`
261			`#define CFG_ILRAM_SIZE 64`
262			`#elif defined CONFIG_ICACHE_LRAM_SZ128`
263			`#define CFG_ILRAM_SIZE 128`
264			`#elif defined CONFIG_ICACHE_LRAM_SZ256`
265			`#define CFG_ILRAM_SIZE 256`
266			`#else`
267			`#define CFG_ILRAM_SIZE 1`
268			`#endif`
269
270
271			`#ifndef CONFIG_DCACHE_ENABLE`
272			`#define CONFIG_DCACHE_ENABLE 0`
273			`#endif`
274
275			`#if defined CONFIG_DCACHE_ASSO1`
276			`#define CFG_IU_DSETS 1`
277			`#elif defined CONFIG_DCACHE_ASSO2`
278			`#define CFG_IU_DSETS 2`
279			`#elif defined CONFIG_DCACHE_ASSO3`
280			`#define CFG_IU_DSETS 3`
281			`#elif defined CONFIG_DCACHE_ASSO4`
282			`#define CFG_IU_DSETS 4`
283			`#else`
284			`#define CFG_IU_DSETS 1`
285			`#endif`
286
287			`#if defined CONFIG_DCACHE_SZ1`
288			`#define CFG_DCACHE_SZ 1`
289			`#elif defined CONFIG_DCACHE_SZ2`
290			`#define CFG_DCACHE_SZ 2`
291			`#elif defined CONFIG_DCACHE_SZ4`
292			`#define CFG_DCACHE_SZ 4`
293			`#elif defined CONFIG_DCACHE_SZ8`
294			`#define CFG_DCACHE_SZ 8`
295			`#elif defined CONFIG_DCACHE_SZ16`
296			`#define CFG_DCACHE_SZ 16`
297			`#elif defined CONFIG_DCACHE_SZ32`
298			`#define CFG_DCACHE_SZ 32`
299			`#elif defined CONFIG_DCACHE_SZ64`
300			`#define CFG_DCACHE_SZ 64`
301			`#elif defined CONFIG_DCACHE_SZ128`
302			`#define CFG_DCACHE_SZ 128`
303			`#elif defined CONFIG_DCACHE_SZ256`
304			`#define CFG_DCACHE_SZ 256`
305			`#else`
306			`#define CFG_DCACHE_SZ 1`
307			`#endif`
308
309			`#ifdef CONFIG_DCACHE_LZ16`
310			`#define CFG_DLINE_SZ 4`
311			`#else`
312			`#define CFG_DLINE_SZ 8`
313			`#endif`
314
315			`#if defined CONFIG_DCACHE_ALGORND`
316			`#define CFG_DCACHE_ALGORND 2`
317			`#elif defined CONFIG_DCACHE_ALGOLRR`
318			`#define CFG_DCACHE_ALGORND 1`
319			`#else`
320			`#define CFG_DCACHE_ALGORND 0`
321			`#endif`
322
323			`#ifndef CONFIG_DCACHE_LOCK`
324			`#define CONFIG_DCACHE_LOCK 0`
325			`#endif`
326
327			`#ifndef CONFIG_DCACHE_SNOOP`
328			`#define CONFIG_DCACHE_SNOOP 0`
329			`#endif`
330
331			`#ifndef CONFIG_DCACHE_SNOOP_FAST`
332			`#define CONFIG_DCACHE_SNOOP_FAST 0`
333			`#endif`
334
335			`#ifndef CONFIG_CACHE_FIXED`
336			`#define CONFIG_CACHE_FIXED 0`
337			`#endif`
338
339			`#ifndef CONFIG_DCACHE_LRAM`
340			`#define CONFIG_DCACHE_LRAM 0`
341			`#endif`
342
343			`#ifndef CONFIG_DCACHE_LRSTART`
344			`#define CONFIG_DCACHE_LRSTART 8F`
345			`#endif`
346
347			`#if defined CONFIG_DCACHE_LRAM_SZ2`
348			`#define CFG_DLRAM_SIZE 2`
349			`#elif defined CONFIG_DCACHE_LRAM_SZ4`
350			`#define CFG_DLRAM_SIZE 4`
351			`#elif defined CONFIG_DCACHE_LRAM_SZ8`
352			`#define CFG_DLRAM_SIZE 8`
353			`#elif defined CONFIG_DCACHE_LRAM_SZ16`
354			`#define CFG_DLRAM_SIZE 16`
355			`#elif defined CONFIG_DCACHE_LRAM_SZ32`
356			`#define CFG_DLRAM_SIZE 32`
357			`#elif defined CONFIG_DCACHE_LRAM_SZ64`
358			`#define CFG_DLRAM_SIZE 64`
359			`#elif defined CONFIG_DCACHE_LRAM_SZ128`
360			`#define CFG_DLRAM_SIZE 128`
361			`#elif defined CONFIG_DCACHE_LRAM_SZ256`
362			`#define CFG_DLRAM_SIZE 256`
363			`#else`
364			`#define CFG_DLRAM_SIZE 1`
365			`#endif`
366
367
368			`#ifdef CONFIG_MMU_ENABLE`
369			`#define CONFIG_MMUEN 1`
370
371			`#ifdef CONFIG_MMU_SPLIT`
372			`#define CONFIG_TLB_TYPE 0`
373			`#endif`
374			`#ifdef CONFIG_MMU_COMBINED`
375			`#define CONFIG_TLB_TYPE 1`
376			`#endif`
377
378			`#ifdef CONFIG_MMU_REPARRAY`
379			`#define CONFIG_TLB_REP 0`
380			`#endif`
381			`#ifdef CONFIG_MMU_REPINCREMENT`
382			`#define CONFIG_TLB_REP 1`
383			`#endif`
384
385			`#ifdef CONFIG_MMU_I2`
386			`#define CONFIG_ITLBNUM 2`
387			`#endif`
388			`#ifdef CONFIG_MMU_I4`
389			`#define CONFIG_ITLBNUM 4`
390			`#endif`
391			`#ifdef CONFIG_MMU_I8`
392			`#define CONFIG_ITLBNUM 8`
393			`#endif`
394			`#ifdef CONFIG_MMU_I16`
395			`#define CONFIG_ITLBNUM 16`
396			`#endif`
397			`#ifdef CONFIG_MMU_I32`
398			`#define CONFIG_ITLBNUM 32`
399			`#endif`
400
401			`#define CONFIG_DTLBNUM 2`
402			`#ifdef CONFIG_MMU_D2`
403			`#undef CONFIG_DTLBNUM`
404			`#define CONFIG_DTLBNUM 2`
405			`#endif`
406			`#ifdef CONFIG_MMU_D4`
407			`#undef CONFIG_DTLBNUM`
408			`#define CONFIG_DTLBNUM 4`
409			`#endif`
410			`#ifdef CONFIG_MMU_D8`
411			`#undef CONFIG_DTLBNUM`
412			`#define CONFIG_DTLBNUM 8`
413			`#endif`
414			`#ifdef CONFIG_MMU_D16`
415			`#undef CONFIG_DTLBNUM`
416			`#define CONFIG_DTLBNUM 16`
417			`#endif`
418			`#ifdef CONFIG_MMU_D32`
419			`#undef CONFIG_DTLBNUM`
420			`#define CONFIG_DTLBNUM 32`
421			`#endif`
422
423			`#ifndef CONFIG_MMU_MMUSNOOP`
424			`#define CONFIG_DCACHE_MMUSNOOP 0`
425			`#else`
426			`#define CONFIG_DCACHE_MMUSNOOP 4`
427			`#endif`
428
429			`#else`
430			`#define CONFIG_MMUEN 0`
431			`#define CONFIG_ITLBNUM 2`
432			`#define CONFIG_DTLBNUM 2`
433			`#define CONFIG_TLB_TYPE 1`
434			`#define CONFIG_TLB_REP 1`
435			`#define CONFIG_DCACHE_MMUSNOOP 0`
436			`#endif`
437
438			`#ifndef CONFIG_DSU_ENABLE`
439			`#define CONFIG_DSU_ENABLE 0`
440			`#endif`
441
442			`#if defined CONFIG_DSU_ITRACESZ1`
443			`#define CFG_DSU_ITB 1`
444			`#elif CONFIG_DSU_ITRACESZ2`
445			`#define CFG_DSU_ITB 2`
446			`#elif CONFIG_DSU_ITRACESZ4`
447			`#define CFG_DSU_ITB 4`
448			`#elif CONFIG_DSU_ITRACESZ8`
449			`#define CFG_DSU_ITB 8`
450			`#elif CONFIG_DSU_ITRACESZ16`
451			`#define CFG_DSU_ITB 16`
452			`#else`
453			`#define CFG_DSU_ITB 0`
454			`#endif`
455
456			`#if defined CONFIG_DSU_ATRACESZ1`
457			`#define CFG_DSU_ATB 1`
458			`#elif CONFIG_DSU_ATRACESZ2`
459			`#define CFG_DSU_ATB 2`
460			`#elif CONFIG_DSU_ATRACESZ4`
461			`#define CFG_DSU_ATB 4`
462			`#elif CONFIG_DSU_ATRACESZ8`
463			`#define CFG_DSU_ATB 8`
464			`#elif CONFIG_DSU_ATRACESZ16`
465			`#define CFG_DSU_ATB 16`
466			`#else`
467			`#define CFG_DSU_ATB 0`
468			`#endif`
469
470			`#ifdef CONFIG_DEBUG_PC32`
471			`#define CFG_DEBUG_PC32 0`
472			`#else`
473			`#define CFG_DEBUG_PC32 2`
474			`#endif`
475			`#ifndef CONFIG_IU_DISAS`
476			`#define CONFIG_IU_DISAS 0`
477			`#endif`
478			`#ifndef CONFIG_IU_DISAS_NET`
479			`#define CONFIG_IU_DISAS_NET 0`
480			`#endif`
481
482			`#ifndef CONFIG_AHB_SPLIT`
483			`#define CONFIG_AHB_SPLIT 0`
484			`#endif`
485
486			`#ifndef CONFIG_AHB_RROBIN`
487			`#define CONFIG_AHB_RROBIN 0`
488			`#endif`
489
490			`#ifndef CONFIG_AHB_IOADDR`
491			`#define CONFIG_AHB_IOADDR FFF`
492			`#endif`
493
494			`#ifndef CONFIG_APB_HADDR`
495			`#define CONFIG_APB_HADDR 800`
496			`#endif`
497
498			`#ifndef CONFIG_DSU_UART`
499			`#define CONFIG_DSU_UART 0`
500			`#endif`
501
502
503			`#ifndef CONFIG_DSU_JTAG`
504			`#define CONFIG_DSU_JTAG 0`
505			`#endif`
506
507			`#ifndef CONFIG_DSU_ETH`
508			`#define CONFIG_DSU_ETH 0`
509			`#endif`
510
511			`#ifndef CONFIG_DSU_IPMSB`
512			`#define CONFIG_DSU_IPMSB C0A8`
513			`#endif`
514
515			`#ifndef CONFIG_DSU_IPLSB`
516			`#define CONFIG_DSU_IPLSB 0033`
517			`#endif`
518
519			`#ifndef CONFIG_DSU_ETHMSB`
520			`#define CONFIG_DSU_ETHMSB 00007A`
521			`#endif`
522
523			`#ifndef CONFIG_DSU_ETHLSB`
524			`#define CONFIG_DSU_ETHLSB CC0001`
525			`#endif`
526
527			`#if defined CONFIG_DSU_ETHSZ1`
528			`#define CFG_DSU_ETHB 1`
529			`#elif CONFIG_DSU_ETHSZ2`
530			`#define CFG_DSU_ETHB 2`
531			`#elif CONFIG_DSU_ETHSZ4`
532			`#define CFG_DSU_ETHB 4`
533			`#elif CONFIG_DSU_ETHSZ8`
534			`#define CFG_DSU_ETHB 8`
535			`#elif CONFIG_DSU_ETHSZ16`
536			`#define CFG_DSU_ETHB 16`
537			`#elif CONFIG_DSU_ETHSZ32`
538			`#define CFG_DSU_ETHB 32`
539			`#else`
540			`#define CFG_DSU_ETHB 1`
541			`#endif`
542
543			`#ifndef CONFIG_MCTRL_LEON2`
544			`#define CONFIG_MCTRL_LEON2 0`
545			`#endif`
546
547			`#ifndef CONFIG_MCTRL_SDRAM`
548			`#define CONFIG_MCTRL_SDRAM 0`
549			`#endif`
550
551			`#ifndef CONFIG_MCTRL_SDRAM_SEPBUS`
552			`#define CONFIG_MCTRL_SDRAM_SEPBUS 0`
553			`#endif`
554
555			`#ifndef CONFIG_MCTRL_SDRAM_INVCLK`
556			`#define CONFIG_MCTRL_SDRAM_INVCLK 0`
557			`#endif`
558
559			`#ifndef CONFIG_MCTRL_SDRAM_BUS64`
560			`#define CONFIG_MCTRL_SDRAM_BUS64 0`
561			`#endif`
562
563			`#ifndef CONFIG_MCTRL_8BIT`
564			`#define CONFIG_MCTRL_8BIT 0`
565			`#endif`
566
567			`#ifndef CONFIG_MCTRL_16BIT`
568			`#define CONFIG_MCTRL_16BIT 0`
569			`#endif`
570
571			`#ifndef CONFIG_MCTRL_5CS`
572			`#define CONFIG_MCTRL_5CS 0`
573			`#endif`
574
575			`#ifndef CONFIG_MCTRL_EDAC`
576			`#define CONFIG_MCTRL_EDAC 0`
577			`#endif`
578
579			`#ifndef CONFIG_MCTRL_PAGE`
580			`#define CONFIG_MCTRL_PAGE 0`
581			`#endif`
582
583			`#ifndef CONFIG_MCTRL_PROGPAGE`
584			`#define CONFIG_MCTRL_PROGPAGE 0`
585			`#endif`
586
587			`#ifndef CONFIG_DDRSP`
588			`#define CONFIG_DDRSP 0`
589			`#endif`
590
591			`#ifndef CONFIG_DDRSP_INIT`
592			`#define CONFIG_DDRSP_INIT 0`
593			`#endif`
594
595			`#ifndef CONFIG_DDRSP_FREQ`
596			`#define CONFIG_DDRSP_FREQ 100`
597			`#endif`
598
599			`#ifndef CONFIG_DDRSP_COL`
600			`#define CONFIG_DDRSP_COL 9`
601			`#endif`
602
603			`#ifndef CONFIG_DDRSP_MBYTE`
604			`#define CONFIG_DDRSP_MBYTE 8`
605			`#endif`
606
607			`#ifndef CONFIG_DDRSP_RSKEW`
608			`#define CONFIG_DDRSP_RSKEW 0`
609			`#endif`
610			`#ifndef CONFIG_AHBROM_ENABLE`
611			`#define CONFIG_AHBROM_ENABLE 0`
612			`#endif`
613
614			`#ifndef CONFIG_AHBROM_START`
615			`#define CONFIG_AHBROM_START 000`
616			`#endif`
617
618			`#ifndef CONFIG_AHBROM_PIPE`
619			`#define CONFIG_AHBROM_PIPE 0`
620			`#endif`
621
622			`#if (CONFIG_AHBROM_START == 0) && (CONFIG_AHBROM_ENABLE == 1)`
623			`#define CONFIG_ROM_START 100`
624			`#else`
625			`#define CONFIG_ROM_START 000`
626			`#endif`
627
628
629			`#ifndef CONFIG_AHBRAM_ENABLE`
630			`#define CONFIG_AHBRAM_ENABLE 0`
631			`#endif`
632
633			`#ifndef CONFIG_AHBRAM_START`
634			`#define CONFIG_AHBRAM_START A00`
635			`#endif`
636
637			`#if defined CONFIG_AHBRAM_SZ1`
638			`#define CFG_AHBRAMSZ 1`
639			`#elif CONFIG_AHBRAM_SZ2`
640			`#define CFG_AHBRAMSZ 2`
641			`#elif CONFIG_AHBRAM_SZ4`
642			`#define CFG_AHBRAMSZ 4`
643			`#elif CONFIG_AHBRAM_SZ8`
644			`#define CFG_AHBRAMSZ 8`
645			`#elif CONFIG_AHBRAM_SZ16`
646			`#define CFG_AHBRAMSZ 16`
647			`#elif CONFIG_AHBRAM_SZ32`
648			`#define CFG_AHBRAMSZ 32`
649			`#elif CONFIG_AHBRAM_SZ64`
650			`#define CFG_AHBRAMSZ 64`
651			`#else`
652			`#define CFG_AHBRAMSZ 1`
653			`#endif`
654
655			`#ifndef CONFIG_GRETH_ENABLE`
656			`#define CONFIG_GRETH_ENABLE 0`
657			`#endif`
658
659			`#ifndef CONFIG_GRETH_GIGA`
660			`#define CONFIG_GRETH_GIGA 0`
661			`#endif`
662
663			`#if defined CONFIG_GRETH_FIFO4`
664			`#define CFG_GRETH_FIFO 4`
665			`#elif defined CONFIG_GRETH_FIFO8`
666			`#define CFG_GRETH_FIFO 8`
667			`#elif defined CONFIG_GRETH_FIFO16`
668			`#define CFG_GRETH_FIFO 16`
669			`#elif defined CONFIG_GRETH_FIFO32`
670			`#define CFG_GRETH_FIFO 32`
671			`#elif defined CONFIG_GRETH_FIFO64`
672			`#define CFG_GRETH_FIFO 64`
673			`#else`
674			`#define CFG_GRETH_FIFO 8`
675			`#endif`
676
677			`#ifndef CONFIG_UART1_ENABLE`
678			`#define CONFIG_UART1_ENABLE 0`
679			`#endif`
680
681			`#if defined CONFIG_UA1_FIFO1`
682			`#define CFG_UA1_FIFO 1`
683			`#elif defined CONFIG_UA1_FIFO2`
684			`#define CFG_UA1_FIFO 2`
685			`#elif defined CONFIG_UA1_FIFO4`
686			`#define CFG_UA1_FIFO 4`
687			`#elif defined CONFIG_UA1_FIFO8`
688			`#define CFG_UA1_FIFO 8`
689			`#elif defined CONFIG_UA1_FIFO16`
690			`#define CFG_UA1_FIFO 16`
691			`#elif defined CONFIG_UA1_FIFO32`
692			`#define CFG_UA1_FIFO 32`
693			`#else`
694			`#define CFG_UA1_FIFO 1`
695			`#endif`
696
697			`#ifndef CONFIG_IRQ3_ENABLE`
698			`#define CONFIG_IRQ3_ENABLE 0`
699			`#endif`
700			`#ifndef CONFIG_GPT_ENABLE`
701			`#define CONFIG_GPT_ENABLE 0`
702			`#endif`
703
704			`#ifndef CONFIG_GPT_NTIM`
705			`#define CONFIG_GPT_NTIM 1`
706			`#endif`
707
708			`#ifndef CONFIG_GPT_SW`
709			`#define CONFIG_GPT_SW 8`
710			`#endif`
711
712			`#ifndef CONFIG_GPT_TW`
713			`#define CONFIG_GPT_TW 8`
714			`#endif`
715
716			`#ifndef CONFIG_GPT_IRQ`
717			`#define CONFIG_GPT_IRQ 8`
718			`#endif`
719
720			`#ifndef CONFIG_GPT_SEPIRQ`
721			`#define CONFIG_GPT_SEPIRQ 0`
722			`#endif`
723			`#ifndef CONFIG_GPT_ENABLE`
724			`#define CONFIG_GPT_ENABLE 0`
725			`#endif`
726
727			`#ifndef CONFIG_GPT_NTIM`
728			`#define CONFIG_GPT_NTIM 1`
729			`#endif`
730
731			`#ifndef CONFIG_GPT_SW`
732			`#define CONFIG_GPT_SW 8`
733			`#endif`
734
735			`#ifndef CONFIG_GPT_TW`
736			`#define CONFIG_GPT_TW 8`
737			`#endif`
738
739			`#ifndef CONFIG_GPT_IRQ`
740			`#define CONFIG_GPT_IRQ 8`
741			`#endif`
742
743			`#ifndef CONFIG_GPT_SEPIRQ`
744			`#define CONFIG_GPT_SEPIRQ 0`
745			`#endif`
746
747			`#ifndef CONFIG_GPT_WDOGEN`
748			`#define CONFIG_GPT_WDOGEN 0`
749			`#endif`
750
751			`#ifndef CONFIG_GPT_WDOG`
752			`#define CONFIG_GPT_WDOG 0`
753			`#endif`
754
755			`#ifndef CONFIG_GRGPIO_ENABLE`
756			`#define CONFIG_GRGPIO_ENABLE 0`
757			`#endif`
758			`#ifndef CONFIG_GRGPIO_IMASK`
759			`#define CONFIG_GRGPIO_IMASK 0000`
760			`#endif`
761			`#ifndef CONFIG_GRGPIO_WIDTH`
762			`#define CONFIG_GRGPIO_WIDTH 1`
763			`#endif`
764
765			`#ifndef CONFIG_VGA_ENABLE`
766			`#define CONFIG_VGA_ENABLE 0`
767			`#endif`
768			`#ifndef CONFIG_SVGA_ENABLE`
769			`#define CONFIG_SVGA_ENABLE 0`
770			`#endif`
771			`#ifndef CONFIG_KBD_ENABLE`
772			`#define CONFIG_KBD_ENABLE 0`
773			`#endif`
774
775
776			`#ifndef CONFIG_DEBUG_UART`
777			`#define CONFIG_DEBUG_UART 0`
778			`#endif`