URL
https://opencores.org/ocsvn/mips_enhanced/mips_enhanced/trunk
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dimamali |
GRLIB=../../
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#WILDCARD_BASE={path to wildcard root directory}
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TOP=wildfpga
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BOARD=wildcard-xcv300e
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include $(GRLIB)/boards/$(BOARD)/Makefile.inc
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DEVICE=$(PART)-$(PACKAGE)$(SPEED)
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UCF=$(GRLIB)/boards/$(BOARD)/default.ucf
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EFFORT=high
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XSTOPT=
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ISEMAPOPT="-r"
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SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0; set_option -resource_sharing 1"
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VHDLSYNFILES=config.vhd wildfpga.vhd
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VHDLSIMFILES=
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SIMTOP=system_cfg
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SDCFILE=$(GRLIB)/boards/$(BOARD)/default.sdc
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BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut
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CLEAN=soft-clean
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LIBSKIP=apa proasic3 axcelerator ecaltera altera_mf stratixii ec altera \
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eclipsee cycloneiii virage atc18 umc18 dw02 spw usbhc eth gleichmann \
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fmf spansion gsi cypress hynix ihp25 sgb25vrh ut025crh rh_lib18t ihp \
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artisan virage90 tsmc90 dare nextreme micron \
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core1553bbc core1553brt core1553brm corePCIF gr1553 openchip tmtc
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DIRSKIP=spw usbhc spacewire greth grusbhc can leon3ft pcif b1553 crypto satcan
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FILESKIP=simple_spi_top.v
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include $(GRLIB)/software/leon3/Makefile
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include $(GRLIB)/bin/Makefile
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| 30 |
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################## project specific targets ##########################
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