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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [designs/] [leon3-xilinx-ml40x/] [leon3mp.ucf] - Blame information for rev 2

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Line No. Rev Author Line
1 2 dimamali 
 
2 
#     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
3 
#     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
4 
#     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
5 
#     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
6 
#     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
7 
#     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
8 
#     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
9 
#     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
10 
#     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
11 
#     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
12 
#     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
13 
#     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
14 
#     FOR A PARTICULAR PURPOSE.
15 
#
16 
#     (c) Copyright 2005 Xilinx, Inc.
17 
#     All rights reserved.
18 
#
19 
 
20 
# Bus clock nets
21 
#NET "clkm"  TNM_NET = "clkm";
22 
#NET "tft_clk"  TNM_NET = "tft_clk";
23 
#NET sys_clk TNM_NET = "sys_clk";
24 
#TIMESPEC "TSSYSCLK" = PERIOD "sys_clk" 9.9 ns HIGH 50 %;
25 
 
26 
NET sys_clk LOC = AE14;
27 
NET sys_clk IOSTANDARD = LVCMOS33;
28 
NET sys_rst_in LOC = D6 | IOSTANDARD = LVCMOS25;
29 
NET sys_rst_in PULLUP;
30 
NET sys_rst_in TIG;
31 
 
32 
#OFFSET = OUT : 5.600 : AFTER sys_clk ;
33 
#OFFSET = OUT : 22.000 : AFTER sys_clk ;
34 
#OFFSET = IN : 5.000 : BEFORE sys_clk ;
35 
 
36 
# SSRAM output delay
37 
#NET sram_flash_data(*) TNM = ssrdatapads;
38 
#TIMEGRP ssrdatapads OFFSET = OUT 5.900 AFTER sys_clk;
39 
 
40 
NET rxd1 LOC = W2;
41 
NET rxd1 IOSTANDARD = LVCMOS33;
42 
NET rxd1 TIG;
43 
NET txd1 LOC = W1;
44 
NET txd1 IOSTANDARD = LVCMOS33;
45 
NET txd1 TIG;
46 
 
47 
#NET ext_irq TIG;
48 
 
49 
# Reset timing ignore - treat as async paths
50 
#NET sys_rst TIG;
51 
#NET opb_v20_0_OPB_Rst TIG;
52 
#NET lmb_v10_1_OPB_Rst TIG;
53 
#NET lmb_v10_0_OPB_Rst TIG;
54 
#NET opb_v20_0_Debug_SYS_Rst TIG;
55 
#NET Debug_Rst TIG;
56 
#NET plb_v34_0_PLB_Rst TIG;
57 
#NET dcm_locked TIG;
58 
 
59 
# Locate DCM/BUFG - Tools can probably figure them out automatically
60 
#                   but just LOC them down to be safe
61 
#INST dcm_0/dcm_0/DCM_ADV_INST LOC = DCM_ADV_X0Y2;
62 
#INST dcm_1/dcm_1/DCM_ADV_INST LOC = DCM_ADV_X0Y4;
63 
#INST dcm_2/dcm_2/DCM_ADV_INST LOC = DCM_ADV_X0Y1;
64 
 
65 
#INST dcm_0/dcm_0/CLK0_BUFG_INST  LOC = BUFGCTRL_X0Y0;
66 
#INST dcm_0/dcm_0/CLK90_BUFG_INST LOC = BUFGCTRL_X0Y1;
67 
#INST dcm_0/dcm_0/CLKDV_BUFG_INST LOC = BUFGCTRL_X0Y2;
68 
 
69 
#INST dcm_1/dcm_1/CLK0_BUFG_INST  LOC = BUFGCTRL_X0Y31;
70 
#INST dcm_1/dcm_1/CLK90_BUFG_INST LOC = BUFGCTRL_X0Y30;
71 
 
72 
////////////////////////////////////////////////////////////////////////////
73 
// Buttons, LEDs, and DIP Switches
74 
////////////////////////////////////////////////////////////////////////////
75 
 
76 
# GPLED 0-3
77 
NET gpio(0)  LOC = G5 | IOSTANDARD = LVCMOS25;  #GPLED0
78 
NET gpio(1)  LOC = G6 | IOSTANDARD = LVCMOS25;  #GPLED1
79 
NET gpio(2)  LOC = A11 | IOSTANDARD = LVCMOS25; #GPLED2
80 
NET gpio(3)  LOC = A12 | IOSTANDARD = LVCMOS25; #GPLED3
81 
# North-East-South-West-Center LEDs
82 
NET gpio(4)  LOC = C6 | IOSTANDARD = LVCMOS25;  # C LED
83 
NET gpio(5)  LOC = F9 | IOSTANDARD = LVCMOS25;  # W LED
84 
NET gpio(6)  LOC = A5 | IOSTANDARD = LVCMOS25;  # S LED
85 
NET gpio(7)  LOC = E10 | IOSTANDARD = LVCMOS25; # E LED
86 
NET gpio(8)  LOC = E2 | IOSTANDARD = LVCMOS25;  # N LED
87 
# North-East-South-West-Center Buttons
88 
NET gpio(9)  LOC = B6 | IOSTANDARD = LVCMOS25;  # C Button
89 
NET gpio(10) LOC = E9 | IOSTANDARD = LVCMOS25;  # W Button
90 
NET gpio(11) LOC = A6 | IOSTANDARD = LVCMOS25;  # S Button
91 
NET gpio(12) LOC = F10 | IOSTANDARD = LVCMOS25; # E Button
92 
NET gpio(13) LOC = E7 | IOSTANDARD = LVCMOS25;  # N Button
93 
# Dip Switches 1-8
94 
NET gpio(14) LOC = U24; # DIP SW 8
95 
NET gpio(15) LOC = U25; # DIP SW 7
96 
NET gpio(16) LOC = V23; # DIP SW 6
97 
NET gpio(17) LOC = U23; # DIP SW 5
98 
NET gpio(18) LOC = U26; # DIP SW 4
99 
NET gpio(19) LOC = T26; # DIP SW 3
100 
NET gpio(20) LOC = R19; # DIP SW 2
101 
NET gpio(21) LOC = R20; # DIP SW 1
102 
NET gpio(14) IOSTANDARD = LVCMOS33;
103 
NET gpio(15) IOSTANDARD = LVCMOS33;
104 
NET gpio(16) IOSTANDARD = LVCMOS33;
105 
NET gpio(17) IOSTANDARD = LVCMOS33;
106 
NET gpio(18) IOSTANDARD = LVCMOS33;
107 
NET gpio(19) IOSTANDARD = LVCMOS33;
108 
NET gpio(20) IOSTANDARD = LVCMOS33;
109 
NET gpio(21) IOSTANDARD = LVCMOS33;
110 
#SMA Connectors
111 
NET gpio(22) LOC = C12; # SMA_IN_N
112 
NET gpio(23) LOC = C13; # SMA_IN_P
113 
NET gpio(24) LOC = D7 | IOSTANDARD = LVCMOS25;  # SMA_OUT_N
114 
NET gpio(25) LOC = D8 | IOSTANDARD = LVCMOS25;  # SMA_OUT_P
115 
NET gpio(26) LOC = AD12;# USERCLK
116 
NET gpio(26) IOSTANDARD = LVCMOS33;
117 
 
118 
NET "gpio(*)" PULLDOWN;
119 
NET "gpio(*)" TIG;
120 
NET "gpio(*)" SLEW = SLOW;
121 
NET "gpio(*)" DRIVE = 2;
122 
 
123 
NET "gpio(22)" SLEW = FAST;
124 
NET "gpio(22)" DRIVE = 12;
125 
NET "gpio(23)" SLEW = FAST;
126 
NET "gpio(23)" DRIVE = 12;
127 
NET "gpio(24)" SLEW = FAST;
128 
NET "gpio(24)" DRIVE = 12;
129 
NET "gpio(25)" SLEW = FAST;
130 
NET "gpio(25)" DRIVE = 12;
131 
 
132 
NET gpio(22) IOSTANDARD = LVCMOS25;
133 
NET gpio(23) IOSTANDARD = LVCMOS25;
134 
 
135 
#NET  "gpio2_d_out(*)" TIG;
136 
#NET  "gpio2_t_out(*)" TIG;
137 
#NET  "gpio2_in(*)" TIG;
138 
 
139 
#------------------------------------------------------------------------------
140 
# IO Pad Location Constraints / Properties for PS/2 Ports
141 
#------------------------------------------------------------------------------
142 
 
143 
#Keyboard
144 
NET ps2_keyb_clk  LOC = D2;
145 
NET ps2_keyb_clk  SLEW = SLOW;
146 
NET ps2_keyb_clk  DRIVE = 2;
147 
NET ps2_keyb_clk  TIG;
148 
NET ps2_keyb_data LOC = G9;
149 
NET ps2_keyb_data SLEW = SLOW;
150 
NET ps2_keyb_data DRIVE = 2;
151 
NET ps2_keyb_data TIG;
152 
NET ps2_keyb_clk IOSTANDARD = LVCMOS25;
153 
NET ps2_keyb_data IOSTANDARD = LVCMOS25;
154 
 
155 
#Mouse
156 
NET ps2_mouse_clk  LOC = B14;
157 
NET ps2_mouse_clk  SLEW = SLOW;
158 
NET ps2_mouse_clk  DRIVE = 2;
159 
NET ps2_mouse_clk  TIG;
160 
NET ps2_mouse_clk IOSTANDARD = LVCMOS25;
161 
NET ps2_mouse_data LOC = C14;
162 
NET ps2_mouse_data SLEW = SLOW;
163 
NET ps2_mouse_data DRIVE = 2;
164 
NET ps2_mouse_data TIG;
165 
NET ps2_mouse_data IOSTANDARD = LVCMOS25;
166 
 
167 
#------------------------------------------------------------------------------
168 
# IO Pad Location Constraints / Properties for IIC Controller
169 
#------------------------------------------------------------------------------
170 
 
171 
NET iic_scl    LOC = A17;
172 
NET iic_sda    LOC = B17;
173 
NET iic_scl    SLEW = SLOW;
174 
NET iic_scl    DRIVE = 6;
175 
NET iic_scl    IOSTANDARD = LVCMOS25;
176 
#NET iic_scl    TIG;
177 
#NET iic_sda    SLEW = SLOW;
178 
NET iic_sda    DRIVE = 6;
179 
NET iic_sda    IOSTANDARD = LVCMOS25;
180 
#NET iic_sda    TIG;
181 
 
182 
#------------------------------------------------------------------------------
183 
# IO Pad Location Constraints / Properties for AC97 Sound Controller
184 
#------------------------------------------------------------------------------
185 
 
186 
NET ac97_bit_clk   LOC = AE10;
187 
#NET ac97_bit_clk   IOSTANDARD = LVCMOS33;
188 
#NET ac97_bit_clk   PERIOD = 80;
189 
NET ac97_sdata_in  LOC = AD16;
190 
#NET ac97_sdata_in  IOSTANDARD = LVCMOS33;
191 
NET ac97_reset_n   LOC = AD10;
192 
#NET ac97_reset_n   IOSTANDARD = LVCMOS33;
193 
#NET ac97_reset_n   TIG;
194 
NET ac97_sdata_out LOC = C8;
195 
NET ac97_sync      LOC = D9;
196 
#NET ac97_sdata_out   IOSTANDARD = LVCMOS25;
197 
#NET ac97_sync   IOSTANDARD = LVCMOS25;
198 
 
199 
#------------------------------------------------------------------------------
200 
# IO Pad Location Constraints / Properties for System ACE MPU / USB
201 
#------------------------------------------------------------------------------
202 
 
203 
NET sysace_clk_in   LOC        = AF11;
204 
#NET sysace_clk_in   IOSTANDARD = LVCMOS33;
205 
#NET sysace_clk_in   TNM_NET    = "sysace_clk_in";
206 
# Leave 1 ns margin
207 
#TIMESPEC "TSSYSACE" = PERIOD "sysace_clk_in" 29 ns;
208 
 
209 
NET sace_usb_a(0)   LOC        = U22;
210 
NET sace_usb_a(1)   LOC        = Y10;
211 
NET sace_usb_a(2)   LOC        = AA10;
212 
NET sace_usb_a(3)   LOC        = AC7;
213 
NET sace_usb_a(4)   LOC        = Y7;
214 
NET sace_usb_a(5)   LOC        = AA9;
215 
NET sace_usb_a(6)   LOC        = Y9;
216 
#NET sace_usb_a(*)   IOSTANDARD = LVCMOS33;
217 
#NET sace_usb_a(*)   SLEW       = FAST;
218 
#NET sace_usb_a(*)   DRIVE      = 8;
219 
NET sace_mpce       LOC        = AD5;
220 
#NET sace_mpce       IOSTANDARD = LVCMOS33;
221 
#NET sace_mpce       SLEW       = FAST;
222 
#NET sace_mpce       DRIVE      = 8;
223 
NET sace_usb_d(0)   LOC        = AB7;
224 
NET sace_usb_d(1)   LOC        = AC9;
225 
NET sace_usb_d(2)   LOC        = AB9;
226 
NET sace_usb_d(3)   LOC        = AE6;
227 
NET sace_usb_d(4)   LOC        = AD6;
228 
NET sace_usb_d(5)   LOC        = AF9;
229 
NET sace_usb_d(6)   LOC        = AE9;
230 
NET sace_usb_d(7)   LOC        = AD8;
231 
NET sace_usb_d(8)   LOC        = AC8;
232 
NET sace_usb_d(9)   LOC        = AF4;
233 
NET sace_usb_d(10)  LOC        = AE4;
234 
NET sace_usb_d(11)  LOC        = AD3;
235 
NET sace_usb_d(12)  LOC        = AC3;
236 
NET sace_usb_d(13)  LOC        = AF6;
237 
NET sace_usb_d(14)  LOC        = AF5;
238 
NET sace_usb_d(15)  LOC        = AA7;
239 
#NET sace_usb_d(*)   IOSTANDARD = LVCMOS33;
240 
#NET sace_usb_d(*)   SLEW       = FAST;
241 
#NET sace_usb_d(*)   DRIVE      = 8;
242 
#NET sace_usb_d(*)   PULLDOWN;
243 
NET sace_usb_oen    LOC        = AA8;
244 
#NET sace_usb_oen    IOSTANDARD = LVCMOS33;
245 
#NET sace_usb_oen    SLEW       = FAST;
246 
#NET sace_usb_oen    DRIVE      = 8;
247 
NET sace_usb_wen    LOC        = Y8;
248 
#NET sace_usb_wen    IOSTANDARD = LVCMOS33;
249 
#NET sace_usb_wen    SLEW       = FAST;
250 
#NET sace_usb_wen    DRIVE      = 8;
251 
NET sysace_mpirq    LOC        = AD4;
252 
#NET sysace_mpirq    IOSTANDARD = LVCMOS33;
253 
#NET sysace_mpirq    TIG;
254 
#NET sysace_mpirq    PULLDOWN;
255 
 
256 
NET usb_csn         LOC        = AF10;
257 
NET usb_csn         IOSTANDARD = LVCMOS33;
258 
#NET usb_csn         SLEW       = FAST;
259 
NET usb_csn         DRIVE      = 8;
260 
NET usb_hpi_reset_n LOC        = A7;
261 
#NET usb_hpi_reset_n IOSTANDARD = LVCMOS25;
262 
#NET usb_hpi_reset_n TIG;
263 
NET usb_hpi_int     LOC        = V5;
264 
#NET usb_hpi_int     IOSTANDARD = LVCMOS33;
265 
#NET usb_hpi_int     TIG;
266 
#NET usb_hpi_int     PULLDOWN;
267 
 
268 
#------------------------------------------------------------------------------
269 
# IO Pad Location Constraints / Properties for DDR Controllers
270 
#------------------------------------------------------------------------------
271 
 
272 
NET ddr_ad(0)  LOC = C26; # DDR_A0
273 
NET ddr_ad(1)  LOC = E17; # DDR_A1
274 
NET ddr_ad(2)  LOC = D18; # DDR_A2
275 
NET ddr_ad(3)  LOC = C19; # DDR_A3
276 
NET ddr_ad(4)  LOC = F17; # DDR_A4
277 
NET ddr_ad(5)  LOC = B18; # DDR_A5
278 
NET ddr_ad(6)  LOC = B20; # DDR_A6
279 
NET ddr_ad(7)  LOC = C20; # DDR_A7
280 
NET ddr_ad(8)  LOC = D20; # DDR_A8
281 
NET ddr_ad(9)  LOC = C21; # DDR_A9
282 
NET ddr_ad(10) LOC = A18; # DDR_A10
283 
NET ddr_ad(11) LOC = B21; # DDR_A11
284 
NET ddr_ad(12) LOC = A24; # DDR_A12
285 
NET ddr_ba(0)  LOC = B12; # DDR_BA0
286 
NET ddr_ba(1)  LOC = A16; # DDR_BA1
287 
NET ddr_casb   LOC = F23; # DDR_CAS_N
288 
NET ddr_cke    LOC = G22; # DDR_CKE
289 
NET ddr_csb    LOC = G21; # DDR_CS_N
290 
NET ddr_rasb   LOC = F24; # DDR_RAS_N
291 
NET ddr_web    LOC = A23; # DDR_WE_N
292 
 
293 
NET ddr_clk    LOC = A10; # DDR_CK1_P
294 
NET ddr_clk_fb LOC = B13; # DDR_CK1_P (FEEDBACK)
295 
NET ddr_clkb   LOC = B10; # DDR_CK1_N
296 
 
297 
NET ddr_dm(0)  LOC = G19; # DDR_DM0
298 
NET ddr_dm(1)  LOC = G24; # DDR_DM1
299 
NET ddr_dm(2)  LOC = G20; # DDR_DM2
300 
NET ddr_dm(3)  LOC = C22; # DDR_DM3
301 
 
302 
NET ddr_dqs(0) LOC = D25; # DDR_DQS0
303 
NET ddr_dqs(1) LOC = G18; # DDR_DQS1
304 
NET ddr_dqs(2) LOC = G17; # DDR_DQS2
305 
NET ddr_dqs(3) LOC = D26; # DDR_DQS3
306 
 
307 
NET ddr_dq(0) LOC = H20; # DDR_D0
308 
NET ddr_dq(1) LOC = E23; # DDR_D1
309 
NET ddr_dq(2) LOC = H26; # DDR_D2
310 
NET ddr_dq(3) LOC = H22; # DDR_D3
311 
NET ddr_dq(4) LOC = E25; # DDR_D4
312 
NET ddr_dq(5) LOC = E26; # DDR_D5
313 
NET ddr_dq(6) LOC = F26; # DDR_D6
314 
NET ddr_dq(7) LOC = E24; # DDR_D7
315 
NET ddr_dq(8) LOC = E20; # DDR_D8
316 
NET ddr_dq(9) LOC = A22; # DDR_D9
317 
NET ddr_dq(10) LOC = C23; # DDR_D10
318 
NET ddr_dq(11) LOC = C24; # DDR_D11
319 
NET ddr_dq(12) LOC = A20; # DDR_D12
320 
NET ddr_dq(13) LOC = A21; # DDR_D13
321 
NET ddr_dq(14) LOC = D24; # DDR_D14
322 
NET ddr_dq(15) LOC = E18; # DDR_D15
323 
NET ddr_dq(16) LOC = F18; # DDR_D16
324 
NET ddr_dq(17) LOC = A19; # DDR_D17
325 
NET ddr_dq(18) LOC = F19; # DDR_D18
326 
NET ddr_dq(19) LOC = B23; # DDR_D19
327 
NET ddr_dq(20) LOC = E21; # DDR_D20
328 
NET ddr_dq(21) LOC = D22; # DDR_D21
329 
NET ddr_dq(22) LOC = D23; # DDR_D22
330 
NET ddr_dq(23) LOC = B24; # DDR_D23
331 
NET ddr_dq(24) LOC = E22; # DDR_D24
332 
NET ddr_dq(25) LOC = F20; # DDR_D25
333 
NET ddr_dq(26) LOC = H23; # DDR_D26
334 
NET ddr_dq(27) LOC = G25; # DDR_D27
335 
NET ddr_dq(28) LOC = G26; # DDR_D28
336 
NET ddr_dq(29) LOC = H25; # DDR_D29
337 
NET ddr_dq(30) LOC = H24; # DDR_D30
338 
NET ddr_dq(31) LOC = H21; # DDR_D31
339 
 
340 
NET ddr_ad(*)  IOSTANDARD = SSTL2_I;
341 
NET ddr_ba(*)  IOSTANDARD = SSTL2_I;
342 
NET ddr_casb   IOSTANDARD = SSTL2_I;
343 
NET ddr_cke    IOSTANDARD = SSTL2_I;
344 
NET ddr_clk    IOSTANDARD = SSTL2_I;
345 
NET ddr_clk_fb IOSTANDARD = LVCMOS25;
346 
NET ddr_clkb   IOSTANDARD = SSTL2_I;
347 
NET ddr_casb   IOSTANDARD = SSTL2_I;
348 
NET ddr_csb    IOSTANDARD = SSTL2_I;
349 
NET ddr_rasb   IOSTANDARD = SSTL2_I;
350 
NET ddr_web    IOSTANDARD = SSTL2_I;
351 
 
352 
NET ddr_dqs(*) IOSTANDARD = SSTL2_II;
353 
NET ddr_dm(*)  IOSTANDARD = SSTL2_II;
354 
NET ddr_dq(*)  IOSTANDARD = SSTL2_II;
355 
 
356 
// Timing Constraint for DDR Feedback Clock
357 
#NET "ddr_clk_fb" TNM_NET = "ddr_clk_fb";
358 
#TIMESPEC "TSDDR_FB" = PERIOD "ddr_clk_fb" 9.9 ns;
359 
 
360 
#------------------------------------------------------------------------------
361 
# IO Pad Location Constraints / Properties for ADV7125 VGA Controller
362 
#------------------------------------------------------------------------------
363 
 
364 
NET vid_b(0) LOC = M21 | IOSTANDARD = LVCMOS33; # VGA_B0
365 
NET vid_b(1) LOC = M26 | IOSTANDARD = LVCMOS33; # VGA_B1
366 
NET vid_b(2) LOC = L26 | IOSTANDARD = LVCMOS33; # VGA_B2
367 
NET vid_b(3) LOC = C5 | IOSTANDARD = LVCMOS25;  # VGA_B3
368 
NET vid_b(4) LOC = C7 | IOSTANDARD = LVCMOS25;  # VGA_B4
369 
NET vid_b(5) LOC = B7 | IOSTANDARD = LVCMOS25;  # VGA_B5
370 
NET vid_b(6) LOC = G8 | IOSTANDARD = LVCMOS25;  # VGA_B6
371 
NET vid_b(7) LOC = F8 | IOSTANDARD = LVCMOS25;  # VGA_B7
372 
NET vid_b(*) SLEW = FAST;
373 
NET vid_b(*) DRIVE = 8;
374 
 
375 
NET tft_lcd_clk  LOC = AF8;
376 
NET tft_lcd_clk  IOSTANDARD = LVDCI_33;
377 
NET tft_lcd_clk  SLEW = FAST;
378 
NET tft_lcd_clk  DRIVE = 8;
379 
 
380 
NET vid_g(0) LOC = M22 | IOSTANDARD = LVCMOS33; # VGA_G0
381 
NET vid_g(1) LOC = M23 | IOSTANDARD = LVCMOS33; # VGA_G1
382 
NET vid_g(2) LOC = M20 | IOSTANDARD = LVCMOS33; # VGA_G2
383 
NET vid_g(3) LOC = E4 | IOSTANDARD = LVCMOS25;  # VGA_G3
384 
NET vid_g(4) LOC = D3 | IOSTANDARD = LVCMOS25;  # VGA_G4
385 
NET vid_g(5) LOC = H7 | IOSTANDARD = LVCMOS25;  # VGA_G5
386 
NET vid_g(6) LOC = H8 | IOSTANDARD = LVCMOS25;  # VGA_G6
387 
NET vid_g(7) LOC = C1 | IOSTANDARD = LVCMOS25;  # VGA_G7
388 
NET vid_g(*) SLEW = FAST;
389 
NET vid_g(*) DRIVE = 8;
390 
 
391 
NET vid_hsync LOC = C10 | IOSTANDARD = LVCMOS25;
392 
NET vid_hsync SLEW = FAST;
393 
NET vid_hsync DRIVE = 8;
394 
NET vid_blankn LOC = M24 | IOSTANDARD = LVCMOS33;
395 
NET vid_syncn LOC = L23 | IOSTANDARD = LVCMOS33;
396 
#NET vid_psaven LOC = M25 | IOSTANDARD = LVCMOS33;
397 
 
398 
NET vid_r(0) LOC = N23 | IOSTANDARD = LVCMOS33; #VGA_R0
399 
NET vid_r(1) LOC = N24 | IOSTANDARD = LVCMOS33; #VGA_R1
400 
NET vid_r(2) LOC = N25 | IOSTANDARD = LVCMOS33; #VGA_R2
401 
NET vid_r(3) LOC = C2 | IOSTANDARD = LVCMOS25; #VGA_R3
402 
NET vid_r(4) LOC = G7 | IOSTANDARD = LVCMOS25; #VGA_R4
403 
NET vid_r(5) LOC = F7 | IOSTANDARD = LVCMOS25; #VGA_R5
404 
NET vid_r(6) LOC = E5 | IOSTANDARD = LVCMOS25; #VGA_R6
405 
NET vid_r(7) LOC = E6 | IOSTANDARD = LVCMOS25; #VGA_R7
406 
NET vid_r(*) SLEW = FAST;
407 
NET vid_r(*) DRIVE = 8;
408 
 
409 
NET vid_vsync LOC = A8 | IOSTANDARD = LVCMOS25;
410 
NET vid_vsync SLEW = FAST;
411 
NET vid_vsync DRIVE = 8;
412 
 
413 
#TIMESPEC "TSPLB_TFT" = FROM "clkm" TO "tft_clk" TIG;
414 
#TIMESPEC "TSTFT_PLB" = FROM "tft_clk" TO "clkm" TIG;
415 
 
416 
////////////////////////////////////////////////////////////////////////////
417 
// Misc Board Signals
418 
////////////////////////////////////////////////////////////////////////////
419 
 
420 
NET plb_error LOC = L24;
421 
NET plb_error IOSTANDARD = LVCMOS33;
422 
NET plb_error TIG;
423 
NET opb_error LOC = V6;
424 
NET opb_error IOSTANDARD = LVCMOS33;
425 
NET opb_error TIG;
426 
 
427 
#------------------------------------------------------------------------------
428 
# IO Pad Location Constraints / Properties for Ethernet
429 
#------------------------------------------------------------------------------
430 
 
431 
NET phy_col        LOC = E3 | IOSTANDARD = LVCMOS25;
432 
NET phy_crs        LOC = D5 | IOSTANDARD = LVCMOS25;
433 
NET phy_dv         LOC = A9 | IOSTANDARD = LVCMOS25;
434 
NET phy_rx_clk     LOC = B15 | IOSTANDARD = LVCMOS25;
435 
NET phy_rx_data(7) LOC = A3 | IOSTANDARD = LVCMOS25;
436 
NET phy_rx_data(6) LOC = B3 | IOSTANDARD = LVCMOS25;
437 
NET phy_rx_data(5) LOC = A4 | IOSTANDARD = LVCMOS25;
438 
NET phy_rx_data(4) LOC = B4 | IOSTANDARD = LVCMOS25;
439 
NET phy_rx_data(3) LOC = C4 | IOSTANDARD = LVCMOS25;
440 
NET phy_rx_data(2) LOC = D4 | IOSTANDARD = LVCMOS25;
441 
NET phy_rx_data(1) LOC = E1 | IOSTANDARD = LVCMOS25;
442 
NET phy_rx_data(0) LOC = F1 | IOSTANDARD = LVCMOS25;
443 
 
444 
NET phy_rx_er      LOC = B9 | IOSTANDARD = LVCMOS25;
445 
NET phy_tx_clk     LOC = C15 | IOSTANDARD = LVCMOS25;
446 
NET phy_mii_clk    LOC = D1 | IOSTANDARD = LVCMOS25;
447 
NET phy_rst_n      LOC = D10 | IOSTANDARD = LVCMOS25;
448 
NET phy_tx_data(7) LOC = G3 | IOSTANDARD = LVCMOS25;
449 
NET phy_tx_data(6) LOC = H6 | IOSTANDARD = LVCMOS25;
450 
NET phy_tx_data(5) LOC = H5 | IOSTANDARD = LVCMOS25;
451 
NET phy_tx_data(4) LOC = G2 | IOSTANDARD = LVCMOS25;
452 
NET phy_tx_data(3) LOC = G1 | IOSTANDARD = LVCMOS25;
453 
NET phy_tx_data(2) LOC = H3 | IOSTANDARD = LVCMOS25;
454 
NET phy_tx_data(1) LOC = H2 | IOSTANDARD = LVCMOS25;
455 
NET phy_tx_data(0) LOC = H1 | IOSTANDARD = LVCMOS25;
456 
NET phy_tx_en      LOC = F4 | IOSTANDARD = LVCMOS25;
457 
NET phy_tx_er      LOC = F3 | IOSTANDARD = LVCMOS25;
458 
NET phy_mii_data   LOC = G4 | IOSTANDARD = LVCMOS25;
459 
NET phy_gtx_clk     LOC = G10 | IOSTANDARD = LVCMOS25;
460 
 
461 
#NET phy_mii_int_n  LOC = H4;
462 
#NET phy_mii_int_n  PULLUP;
463 
#NET phy_mii_int_n  TIG;
464 
 
465 
NET phy_rst_n      TIG;
466 
NET phy_mii_data   TIG;
467 
NET phy_mii_clk    TIG;
468 
 
469 
# Timing Constraints (these are recommended in documentation and
470 
# are unaltered except for the TIG)
471 
NET "phy_rx_clk" TNM_NET = "RXCLK_GRP";
472 
NET "phy_tx_clk" TNM_NET = "TXCLK_GRP";
473 
TIMESPEC "TSTXOUT" = FROM "TXCLK_GRP" TO "PADS" 10 ns;
474 
#TIMESPEC "TSRXIN" = FROM "PADS" TO "RXCLK_GRP" 10 ns;
475 
 
476 
NET "phy_tx_clk" MAXSKEW= 1.0 ns;
477 
NET "phy_rx_clk" MAXSKEW= 1.0 ns;
478 
NET "phy_rx_clk" PERIOD = 8 ns;
479 
NET "phy_tx_clk" PERIOD = 40 ns HIGH 14 ns;
480 
#OFFSET = IN : 2.600 : BEFORE phy_rx_clk;
481 
OFFSET = IN : 2.800 : BEFORE phy_rx_clk;
482 
 
483 
# If the gigabit version of the ethernet mac is excluded from the design,
484 
# the IOBDELAY constraints for phy_rx_data(7 downto 4) must be commented
485 
# out due to a bug in Xilinx's map tool.
486 
#NET "phy_rx_data(7)" IOBDELAY=BOTH;
487 
#NET "phy_rx_data(6)" IOBDELAY=BOTH;
488 
#NET "phy_rx_data(5)" IOBDELAY=BOTH;
489 
#NET "phy_rx_data(4)" IOBDELAY=BOTH;
490 
NET "phy_rx_data(3)" IOBDELAY=BOTH;
491 
NET "phy_rx_data(2)" IOBDELAY=BOTH;
492 
NET "phy_rx_data(1)" IOBDELAY=BOTH;
493 
NET "phy_rx_data(0)" IOBDELAY=BOTH;
494 
NET "phy_dv" IOBDELAY=BOTH;
495 
NET "phy_rx_er" IOBDELAY=BOTH;
496 
 
497 
 
498 
# Timing ignores (to specify unconstrained paths)
499 
#TIMESPEC "TS_PHYTX_OPB" = FROM "TXCLK_GRP" TO "clkm" TIG;
500 
#TIMESPEC "TS_OPB_PHYTX" = FROM "clkm" TO "TXCLK_GRP" TIG;
501 
#TIMESPEC "TS_PHYRX_OPB" = FROM "RXCLK_GRP" TO "clkm" TIG;
502 
#TIMESPEC "TS_OPB_PHYRX" = FROM "clkm" TO "RXCLK_GRP" TIG;
503 
 
504 
#------------------------------------------------------------------------------
505 
# IO Pad Location Constraints / Properties for SRAM/FLASH
506 
#------------------------------------------------------------------------------
507 
 
508 
NET sram_clk            LOC = AF7;
509 
NET sram_clk_fb         LOC = AD17;
510 
NET flash_a23           LOC = T21;
511 
NET sram_flash_addr(22) LOC = U20;
512 
NET sram_flash_addr(21) LOC = T19;
513 
NET sram_flash_addr(20) LOC = AC5;
514 
NET sram_flash_addr(19) LOC = AB5;
515 
NET sram_flash_addr(18) LOC = AC4;
516 
NET sram_flash_addr(17) LOC = AB4;
517 
 
518 
NET sram_flash_addr(16) LOC = AB3;
519 
NET sram_flash_addr(15) LOC = AA4;
520 
NET sram_flash_addr(14) LOC = AA3;
521 
NET sram_flash_addr(13) LOC = W5;
522 
NET sram_flash_addr(12) LOC = W6;
523 
NET sram_flash_addr(11) LOC = W3;
524 
NET sram_flash_addr(10) LOC = AF3;
525 
NET sram_flash_addr(9)  LOC = AE3;
526 
NET sram_flash_addr(8)  LOC = AD2;
527 
NET sram_flash_addr(7)  LOC = AD1;
528 
NET sram_flash_addr(6)  LOC = AC2;
529 
NET sram_flash_addr(5)  LOC = AC1;
530 
NET sram_flash_addr(4)  LOC = AB2;
531 
NET sram_flash_addr(3)  LOC = AB1;
532 
NET sram_flash_addr(2)  LOC = AA1;
533 
NET sram_flash_addr(1)  LOC = Y2;
534 
NET sram_flash_addr(0)  LOC = Y1;
535 
NET sram_flash_data(31) LOC = F14;
536 
NET sram_flash_data(30) LOC = F13;
537 
NET sram_flash_data(29) LOC = F12;
538 
NET sram_flash_data(28) LOC = F11;
539 
NET sram_flash_data(27) LOC = F16;
540 
NET sram_flash_data(26) LOC = F15;
541 
NET sram_flash_data(25) LOC = D14;
542 
NET sram_flash_data(24) LOC = D13;
543 
NET sram_flash_data(23) LOC = D15;
544 
NET sram_flash_data(22) LOC = E14;
545 
NET sram_flash_data(21) LOC = C11;
546 
NET sram_flash_data(20) LOC = D11;
547 
NET sram_flash_data(19) LOC = D16;
548 
NET sram_flash_data(18) LOC = C16;
549 
NET sram_flash_data(17) LOC = E13;
550 
NET sram_flash_data(16) LOC = D12;
551 
NET sram_flash_data(15) LOC = AA14;
552 
NET sram_flash_data(14) LOC = AB14;
553 
NET sram_flash_data(13) LOC = AC12;
554 
NET sram_flash_data(12) LOC = AC11;
555 
NET sram_flash_data(11) LOC = AA16;
556 
NET sram_flash_data(10) LOC = AA15;
557 
NET sram_flash_data(9)  LOC = AB13;
558 
NET sram_flash_data(8)  LOC = AA13;
559 
NET sram_flash_data(7)  LOC = AC14;
560 
NET sram_flash_data(6)  LOC = AD14;
561 
NET sram_flash_data(5)  LOC = AA12;
562 
NET sram_flash_data(4)  LOC = AA11;
563 
NET sram_flash_data(3)  LOC = AC16;
564 
NET sram_flash_data(2)  LOC = AC15;
565 
NET sram_flash_data(1)  LOC = AC13;
566 
NET sram_flash_data(0)  LOC = AD13;
567 
NET sram_cen            LOC = V7;
568 
NET sram_flash_oe_n     LOC = AC6;
569 
NET sram_flash_we_n     LOC = AB6;
570 
NET sram_bw(3)          LOC = Y3; #Y4;
571 
NET sram_bw(2)          LOC = Y4; #Y3;
572 
NET sram_bw(1)          LOC = Y5; #Y6;
573 
NET sram_bw(0)          LOC = Y6; #Y5;
574 
NET flash_ce            LOC = W7;
575 
NET sram_adv_ld_n       LOC = W4;
576 
NET sram_mode           LOC = V26;
577 
 
578 
NET sram_clk           IOSTANDARD = LVCMOS33;
579 
NET sram_clk           DRIVE = 16;
580 
NET sram_clk           SLEW = FAST;
581 
NET sram_clk_fb        IOSTANDARD = LVCMOS33;
582 
 
583 
NET flash_a23          IOSTANDARD = LVDCI_33;
584 
NET flash_a23  SLEW = FAST;
585 
NET flash_a23  DRIVE = 8;
586 
 
587 
NET sram_mode          IOSTANDARD = LVDCI_33;
588 
NET sram_mode SLEW = FAST;
589 
NET sram_mode DRIVE = 8;
590 
 
591 
NET sram_flash_addr(*) IOSTANDARD = LVDCI_33;
592 
NET sram_flash_addr(*)  SLEW = FAST;
593 
NET sram_flash_addr(*)  DRIVE = 8;
594 
 
595 
NET sram_flash_data(*) IOSTANDARD = LVCMOS33;
596 
NET sram_flash_data(*) DRIVE = 12;
597 
NET sram_flash_data(*) SLEW = FAST;
598 
NET sram_flash_data(*) PULLDOWN;
599 
 
600 
NET sram_flash_oe_n    IOSTANDARD = LVDCI_33;
601 
NET sram_flash_oe_n SLEW = FAST;
602 
NET sram_flash_oe_n DRIVE = 8;
603 
 
604 
NET sram_flash_we_n    IOSTANDARD = LVDCI_33;
605 
NET sram_flash_we_n SLEW = FAST;
606 
NET sram_flash_we_n DRIVE = 8;
607 
 
608 
NET sram_bw(*)         IOSTANDARD = LVDCI_33;
609 
NET sram_bw(*) SLEW = FAST;
610 
NET sram_bw(*) DRIVE = 8;
611 
 
612 
NET flash_ce           IOSTANDARD = LVDCI_33;
613 
NET flash_ce SLEW = FAST;
614 
NET flash_ce DRIVE = 8;
615 
 
616 
NET sram_cen           IOSTANDARD = LVDCI_33;
617 
NET sram_cen SLEW = FAST;
618 
NET sram_cen DRIVE = 8;
619 
 
620 
NET sram_adv_ld_n      IOSTANDARD = LVDCI_33;
621 
NET sram_adv_ld_n SLEW = FAST;
622 
NET sram_adv_ld_n DRIVE = 8;
623 
 
624 
#------------------------------------------------------------------------------
625 
# IO Pad Location Constraints / Properties for Expansion Header GPIO
626 
#------------------------------------------------------------------------------
627 
 
628 
NET gpio_exp_hdr1(31) LOC = AF24; # HDR1_64
629 
NET gpio_exp_hdr1(30) LOC = AE24; # HDR1_62
630 
NET gpio_exp_hdr1(29) LOC = AD22; # HDR1_8
631 
NET gpio_exp_hdr1(28) LOC = AB21; # HDR1_58
632 
NET gpio_exp_hdr1(27) LOC = W20;  # HDR1_44
633 
NET gpio_exp_hdr1(26) LOC = W21;  # HDR1_48
634 
NET gpio_exp_hdr1(25) LOC = AB22; # HDR1_14
635 
NET gpio_exp_hdr1(24) LOC = AD25; # HDR1_20
636 
NET gpio_exp_hdr1(23) LOC = W22;  # HDR1_46
637 
NET gpio_exp_hdr1(22) LOC = V21;  # HDR1_56
638 
NET gpio_exp_hdr1(21) LOC = V22;  # HDR1_54
639 
NET gpio_exp_hdr1(20) LOC = AC22; # HDR1_16
640 
NET gpio_exp_hdr1(19) LOC = AD26; # HDR1_18
641 
NET gpio_exp_hdr1(18) LOC = AC26; # HDR1_34
642 
NET gpio_exp_hdr1(17) LOC = AD23; # HDR1_6
643 
NET gpio_exp_hdr1(16) LOC = AB25; # HDR1_30
644 
NET gpio_exp_hdr1(15) LOC = AC23; # HDR1_4
645 
NET gpio_exp_hdr1(14) LOC = AB26; # HDR1_24
646 
NET gpio_exp_hdr1(13) LOC = AC21; # HDR1_60
647 
NET gpio_exp_hdr1(12) LOC = AA23; # HDR1_10
648 
NET gpio_exp_hdr1(11) LOC = AA26; # HDR1_22
649 
NET gpio_exp_hdr1(10) LOC = Y25;  # HDR1_40
650 
NET gpio_exp_hdr1(9)  LOC = Y26;  # HDR1_38
651 
NET gpio_exp_hdr1(8)  LOC = W26;  # HDR1_50
652 
NET gpio_exp_hdr1(7)  LOC = AB23; # HDR1_12
653 
NET gpio_exp_hdr1(6)  LOC = Y24;  # HDR1_26
654 
NET gpio_exp_hdr1(5)  LOC = AB24; # HDR1_32
655 
NET gpio_exp_hdr1(4)  LOC = W25;  # HDR1_52
656 
NET gpio_exp_hdr1(3)  LOC = AC24; # HDR1_2
657 
NET gpio_exp_hdr1(2)  LOC = AC25; # HDR1_36
658 
NET gpio_exp_hdr1(1)  LOC = V20;  # HDR1_42
659 
NET gpio_exp_hdr1(0)  LOC = AA24; # HDR1_28
660 
 
661 
#NET gpio_exp_hdr1(*) TIG;
662 
#NET gpio_exp_hdr1(*) PULLDOWN;
663 
 
664 
NET gpio_exp_hdr2(31) LOC = AF18; # HDR2_40
665 
NET gpio_exp_hdr2(30) LOC = AE18; # HDR2_38
666 
NET gpio_exp_hdr2(29) LOC = AF19; # HDR2_32
667 
NET gpio_exp_hdr2(28) LOC = AF20; # HDR2_30
668 
NET gpio_exp_hdr2(27) LOC = AF21; # HDR2_44
669 
NET gpio_exp_hdr2(26) LOC = AF22; # HDR2_42
670 
NET gpio_exp_hdr2(25) LOC = AF23; # HDR2_24
671 
NET gpio_exp_hdr2(24) LOC = AE23; # HDR2_22
672 
NET gpio_exp_hdr2(23) LOC = AC18; # HDR2_48
673 
NET gpio_exp_hdr2(22) LOC = AB18; # HDR2_46
674 
NET gpio_exp_hdr2(21) LOC = AD19; # HDR2_64
675 
NET gpio_exp_hdr2(20) LOC = AC19; # HDR2_62
676 
NET gpio_exp_hdr2(19) LOC = AE20; # HDR2_16
677 
NET gpio_exp_hdr2(18) LOC = AD20; # HDR2_14
678 
NET gpio_exp_hdr2(17) LOC = AE21; # HDR2_36
679 
NET gpio_exp_hdr2(16) LOC = AD21; # HDR2_34
680 
NET gpio_exp_hdr2(15) LOC = AB20; # HDR2_52
681 
NET gpio_exp_hdr2(14) LOC = AC20; # HDR2_50
682 
NET gpio_exp_hdr2(13) LOC = Y17;  # HDR2_56
683 
NET gpio_exp_hdr2(12) LOC = AA17; # HDR2_54
684 
NET gpio_exp_hdr2(11) LOC = AA19; # HDR2_60
685 
NET gpio_exp_hdr2(10) LOC = AA20; # HDR2_58
686 
NET gpio_exp_hdr2(9)  LOC = Y22;  # HDR2_8
687 
NET gpio_exp_hdr2(8)  LOC = Y23;  # HDR2_6
688 
NET gpio_exp_hdr2(7)  LOC = W23;  # HDR2_12
689 
NET gpio_exp_hdr2(6)  LOC = W24;  # HDR2_10
690 
NET gpio_exp_hdr2(5)  LOC = Y20;  # HDR2_20
691 
NET gpio_exp_hdr2(4)  LOC = Y21;  # HDR2_18
692 
NET gpio_exp_hdr2(3)  LOC = Y19;  # HDR2_28
693 
NET gpio_exp_hdr2(2)  LOC = W19;  # HDR2_26
694 
NET gpio_exp_hdr2(1)  LOC = AA18; # HDR2_4
695 
NET gpio_exp_hdr2(0)  LOC = Y18;  # HDR2_2
696 
 
697 
#NET gpio_exp_hdr2(*) TIG;
698 
#NET gpio_exp_hdr2(*) PULLDOWN;
699 
 
700 
#------------------------------------------------------------------------------
701 
# IO Pad Location Constraints / Properties for Character LCD GPIO
702 
#------------------------------------------------------------------------------
703 
 
704 
NET gpio_char_lcd(6) LOC = AE13; # LCD_E
705 
NET gpio_char_lcd(5) LOC = AC17; # LCD_RS
706 
NET gpio_char_lcd(4) LOC = AB17; # LCD_RW
707 
NET gpio_char_lcd(3) LOC = AF12; # LCD_DB7
708 
NET gpio_char_lcd(2) LOC = AE12; # LCD_DB6
709 
NET gpio_char_lcd(1) LOC = AC10; # LCD_DB5
710 
NET gpio_char_lcd(0) LOC = AB10; # LCD_DB4
711 
#NET gpio_char_lcd(*) IOSTANDARD = LVCMOS33;
712 
#NET gpio_char_lcd(*) TIG;
713 
#NET gpio_char_lcd(*) PULLDOWN;
714 
 
715 
NET sram_clk FEEDBACK = 1.0 NET sram_clk_fb;
716 
#NET ddr_clk FEEDBACK = 1.0 NET ddr_clk_fb;
717 
NET "clkm"              TNM_NET = "clkm";
718 
NET "clkml"             TNM_NET = "clkml";
719 
TIMESPEC "TS_clkm_clkml" = FROM "clkm" TO "clkml" TIG;
720 
TIMESPEC "TS_clkml_clkm" = FROM "clkml" TO "clkm" TIG;
721 
NET "lock"  TIG;
722 
 
723 
NET phy_tx_data(*) TNM = gtxphypads;
724 
NET "egtx_clk"          TNM_NET = "egtx_clk";
725 
TIMESPEC "TS_clkm_egtx_clk" = FROM "clkm" TO "egtx_clk" TIG;
726 
TIMESPEC "TS_egtx_clk_clkm" = FROM "egtx_clk" TO "clkm" TIG;
727 
#TIMESPEC "TSGTXOUT" = FROM "egtx_clk" TO "PADS" 4 ns;
728 
#TIMESPEC "TSGRXIN" = FROM "PADS" TO "eth1_e1_m1000_u0_rxclk" 10 ns;
729 
NET sys_clk period = 10.000 ;
730 
 
731 
NET "ddrsp0.ddrc0/ddr_phy0/ddr_phy0/xc4v.ddr_phy0/rclk90b" TNM_NET = "rclk90b";
732 
TIMEGRP "rclk270b_rise" = FALLING "rclk90b";
733 
TIMEGRP "clkml_rise" = RISING "clkml";
734 
TIMESPEC "TS_rclk270b_clkml_rise" = FROM "rclk270b_rise" TO "clkml_rise" 3.700;
735 
 
736 
NET "ddr_clk_fb" TNM_NET = "ddr_clk_fb";
737 
TIMESPEC "TS_ddr_clk_fb" = PERIOD "ddr_clk_fb" 8.00 ns HIGH 50 %;
738 
 
739 
#NET "clkvga" TNM_NET = "clkvga";
740 
#TIMESPEC "TS_clkm_clkvga" = FROM "clkm" TO "clkvga" TIG;
741 
#TIMESPEC "TS_clkmvga_clkm" = FROM "clkvga" TO "clkm" TIG;
742 
 

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