1 |
2 |
dimamali |
|
2 |
|
|
NET sram_clk FEEDBACK = 1.0 NET sram_clk_fb;
|
3 |
|
|
NET "clkm" TNM_NET = "clkm";
|
4 |
|
|
NET "clkml" TNM_NET = "clkml";
|
5 |
|
|
TIMESPEC "TS_clkm_clkml" = FROM "clkm" TO "clkml" TIG;
|
6 |
|
|
TIMESPEC "TS_clkml_clkm" = FROM "clkml" TO "clkm" TIG;
|
7 |
|
|
#NET "lock" TIG;
|
8 |
|
|
|
9 |
|
|
NET phy_tx_data(*) TNM = gtxphypads;
|
10 |
|
|
NET "egtx_clk" TNM_NET = "egtx_clk";
|
11 |
|
|
TIMESPEC "TS_clkm_egtx_clk" = FROM "clkm" TO "egtx_clk" TIG;
|
12 |
|
|
TIMESPEC "TS_egtx_clk_clkm" = FROM "egtx_clk" TO "clkm" TIG;
|
13 |
|
|
|
14 |
|
|
#TIMESPEC "TSGTXOUT" = FROM "egtx_clk" TO "gtxphypads" 4.3 ns;
|
15 |
|
|
#TIMESPEC "TSGRXIN" = FROM "gtxphypads" TO "eth1_e1_m1000_u0_rxclk" 10 ns;
|
16 |
|
|
|
17 |
|
|
NET clk_100 period = 10.000 ;
|
18 |
|
|
NET clk_200 period = 5.000;
|
19 |
|
|
|
20 |
|
|
NET clk_100 LOC="AD8" | IOSTANDARD = LVCMOS33; # Bank 4, Vcco=3.3V, No DCI
|
21 |
|
|
NET clk_200_p LOC="E16" | IOSTANDARD = LVDS_25; # Bank 3, Vcco=2.5V, No DCI
|
22 |
|
|
NET clk_200_n LOC="E17" | IOSTANDARD = LVDS_25; # Bank 3, Vcco=2.5V, No DCI
|
23 |
|
|
|
24 |
|
|
#NET "ddrsp0.ddrc0/ddr_phy0/ddr_phy0/xc4v.ddr_phy0/dqsclk(*)" TNM_NET = "dqsclk";
|
25 |
|
|
#TIMEGRP "dqsclk_rise" = FALLING "dqsclk";
|
26 |
|
|
#TIMEGRP "clkml_rise" = RISING "clkml";
|
27 |
|
|
#TIMESPEC "TS_dqsclk_clkml_rise" = FROM "dqsclk_rise" TO "clkml_rise" 3.500;
|
28 |
|
|
|
29 |
|
|
INST "ddrsp0.ddrc0/ddr_phy0/ddr_phy0/xc4v.ddr_phy0/idelctrl.0.u" LOC = "IDELAYCTRL_X2Y4";
|
30 |
|
|
INST "ddrsp0.ddrc0/ddr_phy0/ddr_phy0/xc4v.ddr_phy0/idelctrl.1.u" LOC = "IDELAYCTRL_X2Y3";
|
31 |
|
|
INST "ddrsp0.ddrc0/ddr_phy0/ddr_phy0/xc4v.ddr_phy0/idelctrl.2.u" LOC = "IDELAYCTRL_X2Y2";
|
32 |
|
|
INST "ddrsp0.ddrc0/ddr_phy0/ddr_phy0/xc4v.ddr_phy0/idelctrl.3.u" LOC = "IDELAYCTRL_X0Y0";
|
33 |
|
|
INST "ddrsp0.ddrc0/ddr_phy0/ddr_phy0/xc4v.ddr_phy0/idelctrl[0].u" LOC = "IDELAYCTRL_X2Y4";
|
34 |
|
|
INST "ddrsp0.ddrc0/ddr_phy0/ddr_phy0/xc4v.ddr_phy0/idelctrl[1].u" LOC = "IDELAYCTRL_X2Y3";
|
35 |
|
|
INST "ddrsp0.ddrc0/ddr_phy0/ddr_phy0/xc4v.ddr_phy0/idelctrl[2].u" LOC = "IDELAYCTRL_X2Y2";
|
36 |
|
|
INST "ddrsp0.ddrc0/ddr_phy0/ddr_phy0/xc4v.ddr_phy0/idelctrl[3].u" LOC = "IDELAYCTRL_X0Y0";
|
37 |
|
|
|
38 |
|
|
|
39 |
|
|
NET sys_rst_in PULLUP;
|
40 |
|
|
NET sys_rst_in TIG;
|
41 |
|
|
NET sys_rst_in LOC="T23" | IOSTANDARD = LVCMOS33; # Bank 17, Vcco=3.3V, DCI using 49.9 ohm resistors
|
42 |
|
|
|
43 |
|
|
|
44 |
|
|
////////////////////////////////////////////////////////////////////////////
|
45 |
|
|
// Buttons, LEDs, Piezo, and DIP Switches
|
46 |
|
|
////////////////////////////////////////////////////////////////////////////
|
47 |
|
|
|
48 |
|
|
# GPLED
|
49 |
|
|
NET led(0) LOC = E11; #GPLED7 (Rightmost - LSB)
|
50 |
|
|
NET led(1) LOC = E10; #GPLED6
|
51 |
|
|
NET led(2) LOC = E15; #GPLED5
|
52 |
|
|
NET led(3) LOC = D15; #GPLED4
|
53 |
|
|
NET led(4) LOC = F12; #GPLED3
|
54 |
|
|
NET led(5) LOC = E12; #GPLED2
|
55 |
|
|
NET led(6) LOC = D14; #GPLED1
|
56 |
|
|
NET led(7) LOC = E13; #GPLED0 (Leftmost - MSB)
|
57 |
|
|
|
58 |
|
|
NET led(0) IOSTANDARD = LVCMOS25;
|
59 |
|
|
NET led(1) IOSTANDARD = LVCMOS25;
|
60 |
|
|
NET led(2) IOSTANDARD = LVCMOS25;
|
61 |
|
|
NET led(3) IOSTANDARD = LVCMOS25;
|
62 |
|
|
NET led(4) IOSTANDARD = LVCMOS25;
|
63 |
|
|
NET led(5) IOSTANDARD = LVCMOS25;
|
64 |
|
|
NET led(6) IOSTANDARD = LVCMOS25;
|
65 |
|
|
NET led(7) IOSTANDARD = LVCMOS25;
|
66 |
|
|
# North-East-South-West-Center LEDs
|
67 |
|
|
NET led(8) LOC = T22; # C LED
|
68 |
|
|
NET led(9) LOC = AA18; # W LED
|
69 |
|
|
NET led(9) LOC = AA8; # S LED
|
70 |
|
|
NET led(10) LOC = Y18; # E LED
|
71 |
|
|
NET led(11) LOC = Y8; # N LED
|
72 |
|
|
NET led(8) IOSTANDARD = LVCMOS33;
|
73 |
|
|
NET led(9) IOSTANDARD = LVCMOS33;
|
74 |
|
|
NET led(10) IOSTANDARD = LVCMOS33;
|
75 |
|
|
NET led(11) IOSTANDARD = LVCMOS33;
|
76 |
|
|
NET led(12) IOSTANDARD = LVCMOS33;
|
77 |
|
|
# North-East-South-West-Center Buttons
|
78 |
|
|
NET gpio(9) LOC = B21; # C Button
|
79 |
|
|
NET gpio(10) LOC = C21; # W Button
|
80 |
|
|
NET gpio(11) LOC = B22; # S Button
|
81 |
|
|
NET gpio(12) LOC = A23; # E Button
|
82 |
|
|
NET gpio(13) LOC = A22; # N Button
|
83 |
|
|
NET gpio(9) IOSTANDARD = LVCMOS33;
|
84 |
|
|
NET gpio(10) IOSTANDARD = LVCMOS33;
|
85 |
|
|
NET gpio(11) IOSTANDARD = LVCMOS33;
|
86 |
|
|
NET gpio(12) IOSTANDARD = LVCMOS33;
|
87 |
|
|
NET gpio(13) IOSTANDARD = LVCMOS33;
|
88 |
|
|
|
89 |
|
|
# Dip Switches 1-8
|
90 |
|
|
NET gpio(0) LOC = T7; # DIP SW 8
|
91 |
|
|
NET gpio(1) LOC = U7; # DIP SW 7
|
92 |
|
|
NET gpio(2) LOC = U5; # DIP SW 6
|
93 |
|
|
NET gpio(3) LOC = U6; # DIP SW 5
|
94 |
|
|
NET gpio(4) LOC = T5; # DIP SW 4
|
95 |
|
|
NET gpio(5) LOC = T4; # DIP SW 3
|
96 |
|
|
NET gpio(6) LOC = V3; # DIP SW 2
|
97 |
|
|
NET gpio(7) LOC = U4; # DIP SW 1
|
98 |
|
|
NET gpio(0) IOSTANDARD = LVCMOS18;
|
99 |
|
|
NET gpio(1) IOSTANDARD = LVCMOS18;
|
100 |
|
|
NET gpio(2) IOSTANDARD = LVCMOS18;
|
101 |
|
|
NET gpio(3) IOSTANDARD = LVCMOS18;
|
102 |
|
|
NET gpio(4) IOSTANDARD = LVCMOS18;
|
103 |
|
|
NET gpio(5) IOSTANDARD = LVCMOS18;
|
104 |
|
|
NET gpio(6) IOSTANDARD = LVCMOS18;
|
105 |
|
|
NET gpio(7) IOSTANDARD = LVCMOS18;
|
106 |
|
|
#SMA Connectors
|
107 |
|
|
NET gpio(8) LOC = F10; # SMA_IN_N
|
108 |
|
|
NET gpio(9) LOC = F9; # SMA_IN_P
|
109 |
|
|
NET gpio(10) LOC = F19; # SMA_OUT_N
|
110 |
|
|
NET gpio(11) LOC = E18; # SMA_OUT_P
|
111 |
|
|
#NET gpio(26) LOC = AD8; # USERCLK
|
112 |
|
|
NET gpio(8) IOSTANDARD = LVCMOS25;
|
113 |
|
|
NET gpio(9) IOSTANDARD = LVCMOS25;
|
114 |
|
|
NET gpio(10) IOSTANDARD = LVCMOS25;
|
115 |
|
|
NET gpio(11) IOSTANDARD = LVCMOS25;
|
116 |
|
|
#NET gpio(26) IOSTANDARD = LVCMOS33;
|
117 |
|
|
|
118 |
|
|
NET "gpio(*)" PULLDOWN;
|
119 |
|
|
NET "gpio(*)" TIG;
|
120 |
|
|
NET "gpio(*)" SLEW = SLOW;
|
121 |
|
|
NET "gpio(*)" DRIVE = 2;
|
122 |
|
|
|
123 |
|
|
NET "gpio(8)" SLEW = FAST;
|
124 |
|
|
NET "gpio(8)" DRIVE = 12;
|
125 |
|
|
NET "gpio(9)" SLEW = FAST;
|
126 |
|
|
NET "gpio(9)" DRIVE = 12;
|
127 |
|
|
NET "gpio(10)" SLEW = FAST;
|
128 |
|
|
NET "gpio(10)" DRIVE = 12;
|
129 |
|
|
NET "gpio(11)" SLEW = FAST;
|
130 |
|
|
NET "gpio(11)" DRIVE = 12;
|
131 |
|
|
|
132 |
|
|
#NET "gpio2_d_out(*)" TIG;
|
133 |
|
|
#NET "gpio2_t_out(*)" TIG;
|
134 |
|
|
#NET "gpio2_in(*)" TIG;
|
135 |
|
|
|
136 |
|
|
#NET "piezo" LOC = V1;
|
137 |
|
|
#NET "piezo" IOSTANDARD = LVCMOS18;
|
138 |
|
|
#NET "piezo" TIG;
|
139 |
|
|
|
140 |
|
|
#------------------------------------------------------------------------------
|
141 |
|
|
# IO Pad Location Constraints / Properties for PS/2 Ports
|
142 |
|
|
#------------------------------------------------------------------------------
|
143 |
|
|
|
144 |
|
|
#Keyboard
|
145 |
|
|
NET ps2_keyb_clk LOC = J1;
|
146 |
|
|
NET ps2_keyb_clk SLEW = SLOW;
|
147 |
|
|
NET ps2_keyb_clk DRIVE = 2;
|
148 |
|
|
NET ps2_keyb_clk IOSTANDARD = LVCMOS18;
|
149 |
|
|
NET ps2_keyb_clk TIG;
|
150 |
|
|
NET ps2_keyb_data LOC = H2;
|
151 |
|
|
NET ps2_keyb_data SLEW = SLOW;
|
152 |
|
|
NET ps2_keyb_data DRIVE = 2;
|
153 |
|
|
NET ps2_keyb_data IOSTANDARD = LVCMOS18;
|
154 |
|
|
NET ps2_keyb_data TIG;
|
155 |
|
|
|
156 |
|
|
#Mouse
|
157 |
|
|
NET ps2_mouse_clk LOC = L2;
|
158 |
|
|
NET ps2_mouse_clk SLEW = SLOW;
|
159 |
|
|
NET ps2_mouse_clk DRIVE = 2;
|
160 |
|
|
NET ps2_mouse_clk IOSTANDARD = LVCMOS18;
|
161 |
|
|
NET ps2_mouse_clk TIG;
|
162 |
|
|
NET ps2_mouse_data LOC = K1;
|
163 |
|
|
NET ps2_mouse_data SLEW = SLOW;
|
164 |
|
|
NET ps2_mouse_data DRIVE = 2;
|
165 |
|
|
NET ps2_mouse_data IOSTANDARD = LVCMOS18;
|
166 |
|
|
NET ps2_mouse_data TIG;
|
167 |
|
|
|
168 |
|
|
#------------------------------------------------------------------------------
|
169 |
|
|
# IO Pad Location Constraints / Properties for IIC Controller
|
170 |
|
|
#------------------------------------------------------------------------------
|
171 |
|
|
|
172 |
|
|
NET iic_scl LOC = R20;
|
173 |
|
|
NET iic_sda LOC = T20;
|
174 |
|
|
NET iic_scl SLEW = SLOW;
|
175 |
|
|
NET iic_scl DRIVE = 6;
|
176 |
|
|
NET iic_scl TIG;
|
177 |
|
|
NET iic_scl IOSTANDARD = LVCMOS33;
|
178 |
|
|
NET iic_sda SLEW = SLOW;
|
179 |
|
|
NET iic_sda DRIVE = 6;
|
180 |
|
|
NET iic_sda TIG;
|
181 |
|
|
NET iic_sda IOSTANDARD = LVCMOS33;
|
182 |
|
|
|
183 |
|
|
#NET ddr_iic_scl LOC = Y7;
|
184 |
|
|
#NET ddr_iic_sda LOC = AA7;
|
185 |
|
|
#NET ddr_iic_scl SLEW = SLOW;
|
186 |
|
|
#NET ddr_iic_scl DRIVE = 6;
|
187 |
|
|
#NET ddr_iic_scl TIG;
|
188 |
|
|
#NET ddr_iic_scl IOSTANDARD = LVCMOS18;
|
189 |
|
|
#NET ddr_iic_sda SLEW = SLOW;
|
190 |
|
|
#NET ddr_iic_sda DRIVE = 6;
|
191 |
|
|
#NET ddr_iic_sda TIG;
|
192 |
|
|
#NET ddr_iic_sda IOSTANDARD = LVCMOS18;
|
193 |
|
|
|
194 |
|
|
#------------------------------------------------------------------------------
|
195 |
|
|
# IO Pad Location Constraints / Properties for System ACE MPU / USB
|
196 |
|
|
#------------------------------------------------------------------------------
|
197 |
|
|
|
198 |
|
|
#NET sysace_clk_in LOC = AB12;
|
199 |
|
|
#NET sysace_clk_in IOSTANDARD = LVCMOS33;
|
200 |
|
|
#NET sysace_clk_in TNM_NET = "sysace_clk_in";
|
201 |
|
|
# Leave 1 ns margin
|
202 |
|
|
#TIMESPEC "TSSYSACE" = PERIOD "sysace_clk_in" 29 ns;
|
203 |
|
|
|
204 |
|
|
#NET sace_usb_a(0) LOC = N6;
|
205 |
|
|
#NET sace_usb_a(1) LOC = E5;
|
206 |
|
|
#NET sace_usb_a(2) LOC = F5;
|
207 |
|
|
#NET sace_usb_a(3) LOC = F4;
|
208 |
|
|
#NET sace_usb_a(4) LOC = J5;
|
209 |
|
|
#NET sace_usb_a(5) LOC = E7;
|
210 |
|
|
#NET sace_usb_a(6) LOC = G7;
|
211 |
|
|
#NET sace_usb_a(*) IOSTANDARD = LVCMOS33;
|
212 |
|
|
#NET sace_usb_a(*) SLEW = FAST;
|
213 |
|
|
#NET sace_usb_a(*) DRIVE = 8;
|
214 |
|
|
#NET sace_mpce LOC = F7;
|
215 |
|
|
#NET sace_mpce IOSTANDARD = LVCMOS33;
|
216 |
|
|
#NET sace_mpce SLEW = FAST;
|
217 |
|
|
#NET sace_mpce DRIVE = 8;
|
218 |
|
|
#NET sace_usb_d(0) LOC = M6;
|
219 |
|
|
#NET sace_usb_d(1) LOC = K5;
|
220 |
|
|
#NET sace_usb_d(2) LOC = L3;
|
221 |
|
|
#NET sace_usb_d(3) LOC = L4;
|
222 |
|
|
#NET sace_usb_d(4) LOC = L7;
|
223 |
|
|
#NET sace_usb_d(5) LOC = L5;
|
224 |
|
|
#NET sace_usb_d(6) LOC = H6;
|
225 |
|
|
#NET sace_usb_d(7) LOC = G5;
|
226 |
|
|
#NET sace_usb_d(8) LOC = M7;
|
227 |
|
|
#NET sace_usb_d(9) LOC = H7;
|
228 |
|
|
#NET sace_usb_d(10) LOC = J6;
|
229 |
|
|
#NET sace_usb_d(11) LOC = G4;
|
230 |
|
|
#NET sace_usb_d(12) LOC = K7;
|
231 |
|
|
#NET sace_usb_d(13) LOC = J4;
|
232 |
|
|
#NET sace_usb_d(14) LOC = H4;
|
233 |
|
|
#NET sace_usb_d(15) LOC = K6;
|
234 |
|
|
#NET sace_usb_d(*) IOSTANDARD = LVCMOS33;
|
235 |
|
|
#NET sace_usb_d(*) SLEW = FAST;
|
236 |
|
|
#NET sace_usb_d(*) DRIVE = 8;
|
237 |
|
|
#NET sace_usb_d(*) PULLDOWN;
|
238 |
|
|
#NET sace_usb_oen LOC = E6;
|
239 |
|
|
#NET sace_usb_oen IOSTANDARD = LVCMOS33;
|
240 |
|
|
#NET sace_usb_oen SLEW = FAST;
|
241 |
|
|
#NET sace_usb_oen DRIVE = 8;
|
242 |
|
|
#NET sace_usb_wen LOC = M5;
|
243 |
|
|
#NET sace_usb_wen IOSTANDARD = LVCMOS33;
|
244 |
|
|
#NET sace_usb_wen SLEW = FAST;
|
245 |
|
|
#NET sace_usb_wen DRIVE = 8;
|
246 |
|
|
#NET sysace_mpirq LOC = G6;
|
247 |
|
|
#NET sysace_mpirq IOSTANDARD = LVCMOS33;
|
248 |
|
|
#NET sysace_mpirq TIG;
|
249 |
|
|
#NET sysace_mpirq PULLDOWN;
|
250 |
|
|
|
251 |
|
|
NET usb_rstn LOC = P3;
|
252 |
|
|
NET usb_rstn IOSTANDARD = LVCMOS33;
|
253 |
|
|
NET usb_csn LOC = N3;
|
254 |
|
|
NET usb_csn IOSTANDARD = LVCMOS33;
|
255 |
|
|
NET usb_csn SLEW = FAST;
|
256 |
|
|
NET usb_csn DRIVE = 8;
|
257 |
|
|
#NET usb_hpi_reset_n LOC = P3;
|
258 |
|
|
#NET usb_hpi_reset_n IOSTANDARD = LVCMOS33;
|
259 |
|
|
#NET usb_hpi_reset_n TIG;
|
260 |
|
|
#NET usb_hpi_int LOC = M4;
|
261 |
|
|
#NET usb_hpi_int IOSTANDARD = LVCMOS33;
|
262 |
|
|
#NET usb_hpi_int TIG;
|
263 |
|
|
#NET usb_hpi_int PULLDOWN;
|
264 |
|
|
|
265 |
|
|
////////////////////////////////////////////////////////////////////////////
|
266 |
|
|
// Misc Board Signals
|
267 |
|
|
////////////////////////////////////////////////////////////////////////////
|
268 |
|
|
|
269 |
|
|
NET bus_error(0) LOC = N4; # Bus Error 1
|
270 |
|
|
NET bus_error(0) IOSTANDARD = LVCMOS33;
|
271 |
|
|
NET bus_error(0) TIG;
|
272 |
|
|
NET bus_error(1) LOC = P5; # Bus Error 2
|
273 |
|
|
NET bus_error(1) IOSTANDARD = LVCMOS33;
|
274 |
|
|
NET bus_error(1) TIG;
|
275 |
|
|
|
276 |
|
|
#------------------------------------------------------------------------------
|
277 |
|
|
# IO Pad Location Constraints / Properties for Expansion Header GPIO
|
278 |
|
|
#------------------------------------------------------------------------------
|
279 |
|
|
|
280 |
|
|
#NET gpio_exp_hdr1(31) LOC = AB26; # HDR1_64
|
281 |
|
|
#NET gpio_exp_hdr1(30) LOC = AC26; # HDR1_62
|
282 |
|
|
#NET gpio_exp_hdr1(29) LOC = AA25; # HDR1_60
|
283 |
|
|
#NET gpio_exp_hdr1(28) LOC = P26; # HDR1_58
|
284 |
|
|
#NET gpio_exp_hdr1(27) LOC = Y26; # HDR1_56
|
285 |
|
|
#NET gpio_exp_hdr1(26) LOC = Y25; # HDR1_54
|
286 |
|
|
#NET gpio_exp_hdr1(25) LOC = W26; # HDR1_52
|
287 |
|
|
#NET gpio_exp_hdr1(24) LOC = W25; # HDR1_50
|
288 |
|
|
#NET gpio_exp_hdr1(23) LOC = U25; # HDR1_48
|
289 |
|
|
#NET gpio_exp_hdr1(22) LOC = U24; # HDR1_46
|
290 |
|
|
#NET gpio_exp_hdr1(21) LOC = T25; # HDR1_44
|
291 |
|
|
#NET gpio_exp_hdr1(20) LOC = T24; # HDR1_42
|
292 |
|
|
#NET gpio_exp_hdr1(19) LOC = P24; # HDR1_40
|
293 |
|
|
#NET gpio_exp_hdr1(18) LOC = P25; # HDR1_38
|
294 |
|
|
#NET gpio_exp_hdr1(17) LOC = N26; # HDR1_36
|
295 |
|
|
#NET gpio_exp_hdr1(16) LOC = AB25; # HDR1_34
|
296 |
|
|
#NET gpio_exp_hdr1(15) LOC = M24; # HDR1_32
|
297 |
|
|
#NET gpio_exp_hdr1(14) LOC = N24; # HDR1_30
|
298 |
|
|
#NET gpio_exp_hdr1(13) LOC = M25; # HDR1_28
|
299 |
|
|
#NET gpio_exp_hdr1(12) LOC = M26; # HDR1_26
|
300 |
|
|
#NET gpio_exp_hdr1(11) LOC = K25; # HDR1_24
|
301 |
|
|
#NET gpio_exp_hdr1(10) LOC = K26; # HDR1_22
|
302 |
|
|
#NET gpio_exp_hdr1(9) LOC = L24; # HDR1_20
|
303 |
|
|
#NET gpio_exp_hdr1(8) LOC = L25; # HDR1_18
|
304 |
|
|
#NET gpio_exp_hdr1(7) LOC = M21; # HDR1_16
|
305 |
|
|
#NET gpio_exp_hdr1(6) LOC = K21; # HDR1_14
|
306 |
|
|
#NET gpio_exp_hdr1(5) LOC = K20; # HDR1_12
|
307 |
|
|
#NET gpio_exp_hdr1(4) LOC = M22; # HDR1_10
|
308 |
|
|
#NET gpio_exp_hdr1(3) LOC = H23; # HDR1_8
|
309 |
|
|
#NET gpio_exp_hdr1(2) LOC = J21; # HDR1_6
|
310 |
|
|
#NET gpio_exp_hdr1(1) LOC = J23; # HDR1_4
|
311 |
|
|
#NET gpio_exp_hdr1(0) LOC = J20; # HDR1_2
|
312 |
|
|
#NET gpio_exp_hdr1(*) TIG;
|
313 |
|
|
#NET gpio_exp_hdr1(*) PULLDOWN;
|
314 |
|
|
#NET gpio_exp_hdr1(*) IOSTANDARD = LVCMOS25;
|
315 |
|
|
#
|
316 |
|
|
#NET gpio_exp_hdr2(31) LOC = P21; # HDR2_64
|
317 |
|
|
#NET gpio_exp_hdr2(30) LOC = P20; # HDR2_62
|
318 |
|
|
#NET gpio_exp_hdr2(29) LOC = H24; # HDR2_60
|
319 |
|
|
#NET gpio_exp_hdr2(28) LOC = J24; # HDR2_58
|
320 |
|
|
#NET gpio_exp_hdr2(27) LOC = M20; # HDR2_56
|
321 |
|
|
#NET gpio_exp_hdr2(26) LOC = M19; # HDR2_54
|
322 |
|
|
#NET gpio_exp_hdr2(25) LOC = G24; # HDR2_52
|
323 |
|
|
#NET gpio_exp_hdr2(24) LOC = G25; # HDR2_50
|
324 |
|
|
#NET gpio_exp_hdr2(23) LOC = P23; # HDR2_48
|
325 |
|
|
#NET gpio_exp_hdr2(22) LOC = N23; # HDR2_46
|
326 |
|
|
#NET gpio_exp_hdr2(21) LOC = L20; # HDR2_44
|
327 |
|
|
#NET gpio_exp_hdr2(20) LOC = L19; # HDR2_42
|
328 |
|
|
#NET gpio_exp_hdr2(19) LOC = G26; # HDR2_40
|
329 |
|
|
#NET gpio_exp_hdr2(18) LOC = H26; # HDR2_38
|
330 |
|
|
#NET gpio_exp_hdr2(17) LOC = K23; # HDR2_36
|
331 |
|
|
#NET gpio_exp_hdr2(16) LOC = K22; # HDR2_34
|
332 |
|
|
#NET gpio_exp_hdr2(15) LOC = V26; # HDR2_32
|
333 |
|
|
#NET gpio_exp_hdr2(14) LOC = U26; # HDR2_30
|
334 |
|
|
#NET gpio_exp_hdr2(13) LOC = N22; # HDR2_28
|
335 |
|
|
#NET gpio_exp_hdr2(12) LOC = N21; # HDR2_26
|
336 |
|
|
#NET gpio_exp_hdr2(11) LOC = R22; # HDR2_24
|
337 |
|
|
#NET gpio_exp_hdr2(10) LOC = R23; # HDR2_22
|
338 |
|
|
#NET gpio_exp_hdr2(9) LOC = J25; # HDR2_20
|
339 |
|
|
#NET gpio_exp_hdr2(8) LOC = J26; # HDR2_18
|
340 |
|
|
#NET gpio_exp_hdr2(7) LOC = P19; # HDR2_16
|
341 |
|
|
#NET gpio_exp_hdr2(6) LOC = N19; # HDR2_14
|
342 |
|
|
#NET gpio_exp_hdr2(5) LOC = G21; # HDR2_12
|
343 |
|
|
#NET gpio_exp_hdr2(4) LOC = G22; # HDR2_10
|
344 |
|
|
#NET gpio_exp_hdr2(3) LOC = E25; # HDR2_8
|
345 |
|
|
#NET gpio_exp_hdr2(2) LOC = E26; # HDR2_6
|
346 |
|
|
#NET gpio_exp_hdr2(1) LOC = F24; # HDR2_4
|
347 |
|
|
#NET gpio_exp_hdr2(0) LOC = F25; # HDR2_2
|
348 |
|
|
#NET gpio_exp_hdr2(*) TIG;
|
349 |
|
|
#NET gpio_exp_hdr2(*) PULLDOWN;
|
350 |
|
|
#NET gpio_exp_hdr2(*) IOSTANDARD = LVCMOS25;
|
351 |
|
|
|
352 |
|
|
#------------------------------------------------------------------------------
|
353 |
|
|
# IO Pad Location Constraints / Properties for Character LCD GPIO
|
354 |
|
|
#------------------------------------------------------------------------------
|
355 |
|
|
|
356 |
|
|
#NET gpio_char_lcd(6) LOC = P6; # LCD_E
|
357 |
|
|
#NET gpio_char_lcd(5) LOC = R7; # LCD_RS
|
358 |
|
|
#NET gpio_char_lcd(4) LOC = R5; # LCD_RW
|
359 |
|
|
#NET gpio_char_lcd(3) LOC = P4; # LCD_DB7
|
360 |
|
|
#NET gpio_char_lcd(2) LOC = R3; # LCD_DB6
|
361 |
|
|
#NET gpio_char_lcd(1) LOC = T3; # LCD_DB5
|
362 |
|
|
#NET gpio_char_lcd(0) LOC = R6; # LCD_DB4
|
363 |
|
|
#NET gpio_char_lcd(*) IOSTANDARD = LVCMOS33;
|
364 |
|
|
#NET gpio_char_lcd(*) TIG;
|
365 |
|
|
#NET gpio_char_lcd(*) PULLDOWN;
|
366 |
|
|
|
367 |
|
|
#------------------------------------------------------------------------------
|
368 |
|
|
# IO Pad Location Constraints / Properties for DDR Controllers
|
369 |
|
|
#------------------------------------------------------------------------------
|
370 |
|
|
|
371 |
|
|
NET ddr_ad(0) LOC = Y5; # DDR_A0
|
372 |
|
|
NET ddr_ad(1) LOC = Y6; # DDR_A1
|
373 |
|
|
NET ddr_ad(2) LOC = W6; # DDR_A2
|
374 |
|
|
NET ddr_ad(3) LOC = W5; # DDR_A3
|
375 |
|
|
NET ddr_ad(4) LOC = V7; # DDR_A4
|
376 |
|
|
NET ddr_ad(5) LOC = V6; # DDR_A5
|
377 |
|
|
NET ddr_ad(6) LOC = Y3; # DDR_A6
|
378 |
|
|
NET ddr_ad(7) LOC = W3; # DDR_A7
|
379 |
|
|
NET ddr_ad(8) LOC = W4; # DDR_A8
|
380 |
|
|
NET ddr_ad(9) LOC = V4; # DDR_A9
|
381 |
|
|
NET ddr_ad(10) LOC = AD3; # DDR_A10
|
382 |
|
|
NET ddr_ad(11) LOC = AD4; # DDR_A11
|
383 |
|
|
NET ddr_ad(12) LOC = AC3; # DDR_A12
|
384 |
|
|
NET ddr_ad(13) LOC = AD5; # DDR_A13
|
385 |
|
|
NET ddr_ba(0) LOC = AB5; # DDR_BA0
|
386 |
|
|
NET ddr_ba(1) LOC = AB6; # DDR_BA1
|
387 |
|
|
NET ddr_casb LOC = AE3; # DDR_CAS_N
|
388 |
|
|
NET ddr_cke(0) LOC = AA3; # DDR_CKE
|
389 |
|
|
NET ddr_cke(1) LOC = AB4; # DDR_CKE
|
390 |
|
|
NET ddr_csb(0) LOC = AF3; # DDR_CS_N
|
391 |
|
|
NET ddr_csb(1) LOC = AD6; # DDR_CS_N
|
392 |
|
|
NET ddr_rasb LOC = AC6; # DDR_RAS_N
|
393 |
|
|
NET ddr_web LOC = AB7; # DDR_WE_N
|
394 |
|
|
NET ddr_clk(0) LOC = E2; # DDR_CK0_P
|
395 |
|
|
NET ddr_clkb(0) LOC = E1; # DDR_CK0_N
|
396 |
|
|
NET ddr_clk(1) LOC = P1; # DDR_CK1_P
|
397 |
|
|
NET ddr_clkb(1) LOC = R1; # DDR_CK1_N
|
398 |
|
|
NET ddr_odt(0) LOC =AE6; # DDR_ODT0
|
399 |
|
|
NET ddr_odt(1) LOC =AE5; # DDR_ODT1
|
400 |
|
|
|
401 |
|
|
NET ddr_dm(0) LOC = B9; # DDR_DM0
|
402 |
|
|
NET ddr_dm(1) LOC = A8; # DDR_DM1
|
403 |
|
|
NET ddr_dm(2) LOC = C4; # DDR_DM2
|
404 |
|
|
NET ddr_dm(3) LOC = F2; # DDR_DM3
|
405 |
|
|
NET ddr_dm(4) LOC = AB1; # DDR_DM4
|
406 |
|
|
NET ddr_dm(5) LOC = AF24; # DDR_DM5
|
407 |
|
|
NET ddr_dm(6) LOC = AF22; # DDR_DM6
|
408 |
|
|
NET ddr_dm(7) LOC = AF8; # DDR_DM7
|
409 |
|
|
|
410 |
|
|
NET ddr_dqsp(0) LOC = B7; # DDR_DQS0
|
411 |
|
|
NET ddr_dqsn(0) LOC = A7; # DDR_DQSN0
|
412 |
|
|
NET ddr_dqsp(1) LOC = D5; # DDR_DQS1
|
413 |
|
|
NET ddr_dqsn(1) LOC = D6; # DDR_DQSN1
|
414 |
|
|
NET ddr_dqsp(2) LOC = C6; # DDR_DQS2
|
415 |
|
|
NET ddr_dqsn(2) LOC = C7; # DDR_DQSN2
|
416 |
|
|
NET ddr_dqsp(3) LOC = M1; # DDR_DQS3
|
417 |
|
|
NET ddr_dqsn(3) LOC = N1; # DDR_DQSN3
|
418 |
|
|
NET ddr_dqsp(4) LOC = T2; # DDR_DQS4
|
419 |
|
|
NET ddr_dqsn(4) LOC = R2; # DDR_DQSN4
|
420 |
|
|
NET ddr_dqsp(5) LOC = AF18; # DDR_DQS5
|
421 |
|
|
NET ddr_dqsn(5) LOC = AE18; # DDR_DQSN5
|
422 |
|
|
NET ddr_dqsp(6) LOC = AF19; # DDR_DQS6
|
423 |
|
|
NET ddr_dqsn(6) LOC = AF20; # DDR_DQSN6
|
424 |
|
|
NET ddr_dqsp(7) LOC = AF17; # DDR_DQS7
|
425 |
|
|
NET ddr_dqsn(7) LOC = AE17; # DDR_DQSN7
|
426 |
|
|
|
427 |
|
|
NET ddr_dq(0) LOC = C11; # DDR_D0
|
428 |
|
|
NET ddr_dq(1) LOC = C13; # DDR_D1
|
429 |
|
|
NET ddr_dq(2) LOC = A12; # DDR_D2
|
430 |
|
|
NET ddr_dq(3) LOC = C9; # DDR_D3
|
431 |
|
|
NET ddr_dq(4) LOC = D10; # DDR_D4
|
432 |
|
|
NET ddr_dq(5) LOC = C12; # DDR_D5
|
433 |
|
|
NET ddr_dq(6) LOC = B12; # DDR_D6
|
434 |
|
|
NET ddr_dq(7) LOC = A13; # DDR_D7
|
435 |
|
|
NET ddr_dq(8) LOC = A10; # DDR_D8
|
436 |
|
|
NET ddr_dq(9) LOC = A9; # DDR_D9
|
437 |
|
|
NET ddr_dq(10) LOC = B5; # DDR_D10
|
438 |
|
|
NET ddr_dq(11) LOC = D3; # DDR_D11
|
439 |
|
|
NET ddr_dq(12) LOC = B10; # DDR_D12
|
440 |
|
|
NET ddr_dq(13) LOC = B11; # DDR_D13
|
441 |
|
|
NET ddr_dq(14) LOC = B6; # DDR_D14
|
442 |
|
|
NET ddr_dq(15) LOC = B4; # DDR_D15
|
443 |
|
|
NET ddr_dq(16) LOC = C2; # DDR_D16
|
444 |
|
|
NET ddr_dq(17) LOC = A2; # DDR_D17
|
445 |
|
|
NET ddr_dq(18) LOC = D1; # DDR_D18
|
446 |
|
|
NET ddr_dq(19) LOC = B1; # DDR_D19
|
447 |
|
|
NET ddr_dq(20) LOC = C3; # DDR_D20
|
448 |
|
|
NET ddr_dq(21) LOC = A3; # DDR_D21
|
449 |
|
|
NET ddr_dq(22) LOC = C1; # DDR_D22
|
450 |
|
|
NET ddr_dq(23) LOC = B2; # DDR_D23
|
451 |
|
|
NET ddr_dq(24) LOC = F3; # DDR_D24
|
452 |
|
|
NET ddr_dq(25) LOC = G1; # DDR_D25
|
453 |
|
|
NET ddr_dq(26) LOC = G2; # DDR_D26
|
454 |
|
|
NET ddr_dq(27) LOC = H3; # DDR_D27
|
455 |
|
|
NET ddr_dq(28) LOC = E3; # DDR_D28
|
456 |
|
|
NET ddr_dq(29) LOC = H1; # DDR_D29
|
457 |
|
|
NET ddr_dq(30) LOC = K3; # DDR_D30
|
458 |
|
|
NET ddr_dq(31) LOC = J3; # DDR_D31
|
459 |
|
|
|
460 |
|
|
NET ddr_dq(32) LOC = Y1; # DDR_D32
|
461 |
|
|
NET ddr_dq(33) LOC = Y2; # DDR_D33
|
462 |
|
|
NET ddr_dq(34) LOC = AC1; # DDR_D34
|
463 |
|
|
NET ddr_dq(35) LOC = AD1; # DDR_D35
|
464 |
|
|
NET ddr_dq(36) LOC = AA2; # DDR_D36
|
465 |
|
|
NET ddr_dq(37) LOC = AB2; # DDR_D37
|
466 |
|
|
NET ddr_dq(38) LOC = AC2; # DDR_D38
|
467 |
|
|
NET ddr_dq(39) LOC = AE1; # DDR_D39
|
468 |
|
|
NET ddr_dq(40) LOC = AD23; # DDR_D40
|
469 |
|
|
NET ddr_dq(41) LOC = AD26; # DDR_D41
|
470 |
|
|
NET ddr_dq(42) LOC = AF25; # DDR_D42
|
471 |
|
|
NET ddr_dq(43) LOC = AD25; # DDR_D43
|
472 |
|
|
NET ddr_dq(44) LOC = AD24; # DDR_D44
|
473 |
|
|
NET ddr_dq(45) LOC = AE26; # DDR_D45
|
474 |
|
|
NET ddr_dq(46) LOC = AE25; # DDR_D46
|
475 |
|
|
NET ddr_dq(47) LOC = AF23; # DDR_D47
|
476 |
|
|
NET ddr_dq(48) LOC = AD20; # DDR_D48
|
477 |
|
|
NET ddr_dq(49) LOC = AE20; # DDR_D49
|
478 |
|
|
NET ddr_dq(50) LOC = AF14; # DDR_D50
|
479 |
|
|
NET ddr_dq(51) LOC = AF12; # DDR_D51
|
480 |
|
|
NET ddr_dq(52) LOC = AD21; # DDR_D52
|
481 |
|
|
NET ddr_dq(53) LOC = AE21; # DDR_D53
|
482 |
|
|
NET ddr_dq(54) LOC = AF13; # DDR_D54
|
483 |
|
|
NET ddr_dq(55) LOC = AE12; # DDR_D55
|
484 |
|
|
NET ddr_dq(56) LOC = AE11; # DDR_D56
|
485 |
|
|
NET ddr_dq(57) LOC = AE10; # DDR_D57
|
486 |
|
|
NET ddr_dq(58) LOC = AF7; # DDR_D58
|
487 |
|
|
NET ddr_dq(59) LOC = AE7; # DDR_D59
|
488 |
|
|
NET ddr_dq(60) LOC = AF10; # DDR_D60
|
489 |
|
|
NET ddr_dq(61) LOC = AF9; # DDR_D61
|
490 |
|
|
NET ddr_dq(62) LOC = AE8; # DDR_D62
|
491 |
|
|
NET ddr_dq(63) LOC = AD9; # DDR_D63
|
492 |
|
|
|
493 |
|
|
NET ddr_ad(*) IOSTANDARD = SSTL18_II;
|
494 |
|
|
NET ddr_ba(*) IOSTANDARD = SSTL18_II;
|
495 |
|
|
NET ddr_casb IOSTANDARD = SSTL18_II;
|
496 |
|
|
NET ddr_cke(*) IOSTANDARD = SSTL18_II;
|
497 |
|
|
NET ddr_clk(*) IOSTANDARD = SSTL18_II;
|
498 |
|
|
NET ddr_clkb(*) IOSTANDARD = SSTL18_II;
|
499 |
|
|
NET ddr_casb IOSTANDARD = SSTL18_II;
|
500 |
|
|
NET ddr_csb(*) IOSTANDARD = SSTL18_II;
|
501 |
|
|
NET ddr_rasb IOSTANDARD = SSTL18_II;
|
502 |
|
|
NET ddr_web IOSTANDARD = SSTL18_II;
|
503 |
|
|
NET ddr_odt(*) IOSTANDARD = SSTL18_II;
|
504 |
|
|
|
505 |
|
|
#NET ddr_dqsp(*) IOSTANDARD = SSTL18_II_DCI;
|
506 |
|
|
#NET ddr_dqsn(*) IOSTANDARD = SSTL18_II_DCI;
|
507 |
|
|
#NET ddr_dm(*) IOSTANDARD = SSTL18_II_DCI;
|
508 |
|
|
#NET ddr_dq(*) IOSTANDARD = SSTL18_II_DCI;
|
509 |
|
|
|
510 |
|
|
NET ddr_dqsp(*) IOSTANDARD = DIFF_SSTL18_II;
|
511 |
|
|
NET ddr_dqsn(*) IOSTANDARD = DIFF_SSTL18_II;
|
512 |
|
|
NET ddr_dm(*) IOSTANDARD = SSTL18_II;
|
513 |
|
|
NET ddr_dq(*) IOSTANDARD = SSTL18_II;
|
514 |
|
|
|
515 |
|
|
#NET "ddr_cal_clk" TNM_NET = "ddr_cal_clk";
|
516 |
|
|
#NET "ddr_dev_clk_*" TNM_NET = "ddr_dev_clk";
|
517 |
|
|
#TIMESPEC "TSCAL_DEV" = FROM "ddr_cal_clk" TO "ddr_dev_clk" TIG;
|
518 |
|
|
#TIMESPEC "TSDEV_CAL" = FROM "ddr_dev_clk" TO "ddr_cal_clk" TIG;
|
519 |
|
|
|
520 |
|
|
#------------------------------------------------------------------------------
|
521 |
|
|
# IO Pad Location Constraints / Properties for UART
|
522 |
|
|
#------------------------------------------------------------------------------
|
523 |
|
|
|
524 |
|
|
NET rxd1 LOC = AC7;
|
525 |
|
|
NET rxd1 IOSTANDARD = LVCMOS33;
|
526 |
|
|
NET rxd1 TIG;
|
527 |
|
|
NET txd1 LOC = AD14;
|
528 |
|
|
NET txd1 IOSTANDARD = LVCMOS33;
|
529 |
|
|
NET txd1 TIG;
|
530 |
|
|
|
531 |
|
|
#------------------------------------------------------------------------------
|
532 |
|
|
# IO Pad Location Constraints / Properties for SRAM
|
533 |
|
|
#------------------------------------------------------------------------------
|
534 |
|
|
|
535 |
|
|
NET sram_clk LOC = U22;
|
536 |
|
|
NET sram_clk_fb LOC = AD15;
|
537 |
|
|
NET sram_clk_fb IOSTANDARD = LVCMOS33;
|
538 |
|
|
NET sram_clk IOSTANDARD = LVDCI_33;
|
539 |
|
|
|
540 |
|
|
NET sram_flash_addr(23) LOC = Y10;
|
541 |
|
|
NET sram_flash_addr(22) LOC = Y11;
|
542 |
|
|
NET sram_flash_addr(21) LOC = AA17;
|
543 |
|
|
NET sram_flash_addr(20) LOC = AB17;
|
544 |
|
|
NET sram_flash_addr(19) LOC = G14;
|
545 |
|
|
NET sram_flash_addr(18) LOC = F13;
|
546 |
|
|
NET sram_flash_addr(17) LOC = H14;
|
547 |
|
|
NET sram_flash_addr(16) LOC = H13;
|
548 |
|
|
NET sram_flash_addr(15) LOC = F15;
|
549 |
|
|
NET sram_flash_addr(14) LOC = G15;
|
550 |
|
|
NET sram_flash_addr(13) LOC = G12;
|
551 |
|
|
NET sram_flash_addr(12) LOC = H12;
|
552 |
|
|
NET sram_flash_addr(11) LOC = G16;
|
553 |
|
|
NET sram_flash_addr(10) LOC = H16;
|
554 |
|
|
NET sram_flash_addr(9) LOC = H11;
|
555 |
|
|
NET sram_flash_addr(8) LOC = G11;
|
556 |
|
|
NET sram_flash_addr(7) LOC = H17;
|
557 |
|
|
NET sram_flash_addr(6) LOC = G17;
|
558 |
|
|
NET sram_flash_addr(5) LOC = G10;
|
559 |
|
|
NET sram_flash_addr(4) LOC = G9;
|
560 |
|
|
NET sram_flash_addr(3) LOC = G19;
|
561 |
|
|
NET sram_flash_addr(2) LOC = H18;
|
562 |
|
|
NET sram_flash_addr(1) LOC = H9;
|
563 |
|
|
NET sram_flash_addr(0) LOC = H8;
|
564 |
|
|
NET sram_flash_addr(*) IOSTANDARD = LVCMOS33;
|
565 |
|
|
NET sram_flash_addr(*) SLEW = FAST;
|
566 |
|
|
NET sram_flash_addr(*) DRIVE = 8;
|
567 |
|
|
|
568 |
|
|
NET sram_flash_data(15) LOC = AD18 | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST;
|
569 |
|
|
NET sram_flash_data(14) LOC = AC18 | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST;
|
570 |
|
|
NET sram_flash_data(13) LOC = AB10 | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST;
|
571 |
|
|
NET sram_flash_data(12) LOC = AB9 | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST;
|
572 |
|
|
NET sram_flash_data(11) LOC = AC17 | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST;
|
573 |
|
|
NET sram_flash_data(10) LOC = AC16 | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST;
|
574 |
|
|
NET sram_flash_data(9) LOC = AC8 | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST;
|
575 |
|
|
NET sram_flash_data(8) LOC = AC9 | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST;
|
576 |
|
|
NET sram_flash_data(7) LOC = Y12 | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST;
|
577 |
|
|
NET sram_flash_data(6) LOC = Y13 | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST;
|
578 |
|
|
NET sram_flash_data(5) LOC = AA15 | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST;
|
579 |
|
|
NET sram_flash_data(4) LOC = AB14 | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST;
|
580 |
|
|
NET sram_flash_data(3) LOC = AA12 | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST;
|
581 |
|
|
NET sram_flash_data(2) LOC = AB11 | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST;
|
582 |
|
|
NET sram_flash_data(1) LOC = AA13 | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST;
|
583 |
|
|
NET sram_flash_data(0) LOC = AA14 | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST;
|
584 |
|
|
NET sram_flash_data(31) LOC = AC24 | IOSTANDARD = LVDCI_33;
|
585 |
|
|
NET sram_flash_data(30) LOC = AB22 | IOSTANDARD = LVDCI_33;
|
586 |
|
|
NET sram_flash_data(29) LOC = AA22 | IOSTANDARD = LVDCI_33;
|
587 |
|
|
NET sram_flash_data(28) LOC = AC21 | IOSTANDARD = LVDCI_33;
|
588 |
|
|
NET sram_flash_data(27) LOC = AB21 | IOSTANDARD = LVDCI_33;
|
589 |
|
|
NET sram_flash_data(26) LOC = W21 | IOSTANDARD = LVDCI_33;
|
590 |
|
|
NET sram_flash_data(25) LOC = W20 | IOSTANDARD = LVDCI_33;
|
591 |
|
|
NET sram_flash_data(24) LOC = U19 | IOSTANDARD = LVDCI_33;
|
592 |
|
|
NET sram_flash_data(23) LOC = U20 | IOSTANDARD = LVDCI_33;
|
593 |
|
|
NET sram_flash_data(22) LOC = V19 | IOSTANDARD = LVDCI_33;
|
594 |
|
|
NET sram_flash_data(21) LOC = W19 | IOSTANDARD = LVDCI_33;
|
595 |
|
|
NET sram_flash_data(20) LOC = Y21 | IOSTANDARD = LVDCI_33;
|
596 |
|
|
NET sram_flash_data(19) LOC = Y20 | IOSTANDARD = LVDCI_33;
|
597 |
|
|
NET sram_flash_data(18) LOC = AD19 | IOSTANDARD = LVDCI_33;
|
598 |
|
|
NET sram_flash_data(17) LOC = AC19 | IOSTANDARD = LVDCI_33;
|
599 |
|
|
NET sram_flash_data(16) LOC = AB20 | IOSTANDARD = LVDCI_33;
|
600 |
|
|
|
601 |
|
|
NET sram_flash_data(*) PULLDOWN;
|
602 |
|
|
|
603 |
|
|
NET sram_cen LOC = AB24 | IOSTANDARD = LVDCI_33;
|
604 |
|
|
NET sram_oen LOC = AC22 | IOSTANDARD = LVDCI_33;
|
605 |
|
|
NET flash_oen LOC = AA9 | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST;
|
606 |
|
|
NET sram_flash_we_n LOC = AB15 | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST;
|
607 |
|
|
NET sram_bw(3) LOC = W24 | IOSTANDARD = LVDCI_33;
|
608 |
|
|
NET sram_bw(2) LOC = W23 | IOSTANDARD = LVDCI_33;
|
609 |
|
|
NET sram_bw(1) LOC = V24 | IOSTANDARD = LVDCI_33;
|
610 |
|
|
NET sram_bw(0) LOC = V23 | IOSTANDARD = LVDCI_33;
|
611 |
|
|
NET flash_ce LOC = AA10 | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST;
|
612 |
|
|
NET sram_adv_ld_n LOC = U21 | IOSTANDARD = LVDCI_33;
|
613 |
|
|
NET sram_mode LOC = AC23 | IOSTANDARD = LVDCI_33;
|
614 |
|
|
NET flash_audio_reset_n LOC = AD10 | IOSTANDARD = LVCMOS33;
|
615 |
|
|
NET flash_adv_n LOC="AA20"; # Bank 17, Vcco=3.3V (FLASH_ADV_B)
|
616 |
|
|
|
617 |
|
|
|
618 |
|
|
#------------------------------------------------------------------------------
|
619 |
|
|
# IO Pad Location Constraints / Properties for TFT VGA LCD Controller
|
620 |
|
|
#------------------------------------------------------------------------------
|
621 |
|
|
|
622 |
|
|
#NET dvi_iic_scl LOC = D21;
|
623 |
|
|
#NET dvi_iic_sda LOC = D20;
|
624 |
|
|
#NET dvi_iic_scl SLEW = SLOW;
|
625 |
|
|
#NET dvi_iic_scl DRIVE = 6;
|
626 |
|
|
#NET dvi_iic_scl TIG;
|
627 |
|
|
#NET dvi_iic_scl IOSTANDARD = LVCMOS33;
|
628 |
|
|
#NET dvi_iic_sda SLEW = SLOW;
|
629 |
|
|
#NET dvi_iic_sda DRIVE = 6;
|
630 |
|
|
#NET dvi_iic_sda TIG;
|
631 |
|
|
#NET dvi_iic_sda IOSTANDARD = LVCMOS33;
|
632 |
|
|
#
|
633 |
|
|
#NET tft_lcd_data(0) LOC = A17;
|
634 |
|
|
#NET tft_lcd_data(1) LOC = B17;
|
635 |
|
|
#NET tft_lcd_data(2) LOC = C17;
|
636 |
|
|
#NET tft_lcd_data(3) LOC = D18;
|
637 |
|
|
#NET tft_lcd_data(4) LOC = C16;
|
638 |
|
|
#NET tft_lcd_data(5) LOC = D16;
|
639 |
|
|
#NET tft_lcd_data(6) LOC = B16;
|
640 |
|
|
#NET tft_lcd_data(7) LOC = B15;
|
641 |
|
|
#NET tft_lcd_data(8) LOC = A15;
|
642 |
|
|
#NET tft_lcd_data(9) LOC = A14;
|
643 |
|
|
#NET tft_lcd_data(10) LOC = B14;
|
644 |
|
|
#NET tft_lcd_data(11) LOC = C14;
|
645 |
|
|
#NET tft_lcd_data(*) IOSTANDARD = LVDCI_33;
|
646 |
|
|
#
|
647 |
|
|
#NET tft_lcd_clk_p LOC = A20;
|
648 |
|
|
#NET tft_lcd_clk_p IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = FAST;
|
649 |
|
|
#NET tft_lcd_clk_n LOC = B20;
|
650 |
|
|
#NET tft_lcd_clk_n IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = FAST;
|
651 |
|
|
#
|
652 |
|
|
#NET tft_lcd_hsync LOC = C19;
|
653 |
|
|
#NET tft_lcd_hsync IOSTANDARD = LVDCI_33;
|
654 |
|
|
#NET tft_lcd_vsync LOC = D19;
|
655 |
|
|
#NET tft_lcd_vsync IOSTANDARD = LVDCI_33;
|
656 |
|
|
#NET tft_lcd_de LOC = C18;
|
657 |
|
|
#NET tft_lcd_de IOSTANDARD = LVDCI_33;
|
658 |
|
|
#NET tft_lcd_reset_b LOC = A18;
|
659 |
|
|
#NET tft_lcd_reset_b IOSTANDARD = LVCMOS33;
|
660 |
|
|
#
|
661 |
|
|
#NET "tft_clk" TNM_NET = "tft_clk";
|
662 |
|
|
#TIMESPEC "TSPLB_TFT" = FROM "sys_clk" TO "tft_clk" TIG;
|
663 |
|
|
#TIMESPEC "TSTFT_PLB" = FROM "tft_clk" TO "sys_clk" TIG;
|
664 |
|
|
|
665 |
|
|
#------------------------------------------------------------------------------
|
666 |
|
|
# IO Pad Location Constraints / Properties for Ethernet
|
667 |
|
|
#------------------------------------------------------------------------------
|
668 |
|
|
|
669 |
|
|
NET phy_col LOC = G20 | IOSTANDARD = LVCMOS25;
|
670 |
|
|
NET phy_crs LOC = H22 | IOSTANDARD = LVCMOS25;
|
671 |
|
|
NET phy_dv LOC = J19 | IOSTANDARD = LVCMOS25;
|
672 |
|
|
NET phy_rx_clk LOC = F14 | IOSTANDARD = LVCMOS25;
|
673 |
|
|
NET phy_rx_data(7) LOC = H21 | IOSTANDARD = LVCMOS25;
|
674 |
|
|
NET phy_rx_data(6) LOC = F23 | IOSTANDARD = LVCMOS25;
|
675 |
|
|
NET phy_rx_data(5) LOC = F22 | IOSTANDARD = LVCMOS25;
|
676 |
|
|
NET phy_rx_data(4) LOC = E23 | IOSTANDARD = LVCMOS25;
|
677 |
|
|
NET phy_rx_data(3) LOC = E22 | IOSTANDARD = LVCMOS25;
|
678 |
|
|
NET phy_rx_data(2) LOC = E20 | IOSTANDARD = LVCMOS25;
|
679 |
|
|
NET phy_rx_data(1) LOC = E21 | IOSTANDARD = LVCMOS25;
|
680 |
|
|
NET phy_rx_data(0) LOC = F20 | IOSTANDARD = LVCMOS25;
|
681 |
|
|
|
682 |
|
|
NET phy_rx_er LOC = H19 | IOSTANDARD = LVCMOS25;
|
683 |
|
|
NET phy_tx_clk LOC = D13 | IOSTANDARD = LVCMOS25;
|
684 |
|
|
NET phy_mii_clk LOC = F18 | IOSTANDARD = LVCMOS25;
|
685 |
|
|
#NET phy_mii_int_n LOC = F17 | IOSTANDARD = LVCMOS25;
|
686 |
|
|
NET phy_rst_n LOC = F8 | IOSTANDARD = LVCMOS25;
|
687 |
|
|
NET phy_tx_data(7) LOC = D25 | IOSTANDARD = LVDCI_33;
|
688 |
|
|
NET phy_tx_data(6) LOC = C26 | IOSTANDARD = LVDCI_33;
|
689 |
|
|
NET phy_tx_data(5) LOC = B26 | IOSTANDARD = LVDCI_33;
|
690 |
|
|
NET phy_tx_data(4) LOC = A25 | IOSTANDARD = LVDCI_33;
|
691 |
|
|
NET phy_tx_data(3) LOC = B25 | IOSTANDARD = LVDCI_33;
|
692 |
|
|
NET phy_tx_data(2) LOC = C24 | IOSTANDARD = LVDCI_33;
|
693 |
|
|
NET phy_tx_data(1) LOC = D24 | IOSTANDARD = LVDCI_33;
|
694 |
|
|
NET phy_tx_data(0) LOC = C23 | IOSTANDARD = LVDCI_33;
|
695 |
|
|
NET phy_tx_en LOC = B24 | IOSTANDARD = LVDCI_33;
|
696 |
|
|
NET phy_tx_er LOC = A24 | IOSTANDARD = LVDCI_33;
|
697 |
|
|
NET phy_gtx_clk LOC = D26 | IOSTANDARD = LVDCI_33;
|
698 |
|
|
NET phy_mii_data LOC = E8 | IOSTANDARD = LVCMOS25;
|
699 |
|
|
|
700 |
|
|
#NET phy_mii_int_n PULLUP;
|
701 |
|
|
|
702 |
|
|
#NET phy_mii_int_n TIG;
|
703 |
|
|
#NET phy_rst_n TIG;
|
704 |
|
|
|
705 |
|
|
# Timing Constraints (these are recommended in documentation and
|
706 |
|
|
# are unaltered except for the TIG)
|
707 |
|
|
NET "phy_rx_clk" TNM_NET = "RXCLK_GRP";
|
708 |
|
|
NET "phy_tx_clk" TNM_NET = "TXCLK_GRP";
|
709 |
|
|
TIMESPEC "TSTXOUT" = FROM "TXCLK_GRP" TO "PADS" 10 ns;
|
710 |
|
|
TIMESPEC "TSRXIN" = FROM "PADS" TO "RXCLK_GRP" 6 ns;
|
711 |
|
|
|
712 |
|
|
NET "phy_rx_data(7)" IOBDELAY=NONE;
|
713 |
|
|
NET "phy_rx_data(6)" IOBDELAY=NONE;
|
714 |
|
|
NET "phy_rx_data(5)" IOBDELAY=NONE;
|
715 |
|
|
NET "phy_rx_data(4)" IOBDELAY=NONE;
|
716 |
|
|
NET "phy_rx_data(3)" IOBDELAY=NONE;
|
717 |
|
|
NET "phy_rx_data(2)" IOBDELAY=NONE;
|
718 |
|
|
NET "phy_rx_data(1)" IOBDELAY=NONE;
|
719 |
|
|
NET "phy_rx_data(0)" IOBDELAY=NONE;
|
720 |
|
|
NET "phy_dv" IOBDELAY=NONE;
|
721 |
|
|
NET "phy_rx_er" IOBDELAY=NONE;
|
722 |
|
|
NET "phy_crs" IOBDELAY=NONE;
|
723 |
|
|
NET "phy_col" IOBDELAY=NONE;
|
724 |
|
|
|
725 |
|
|
# Timing ignores (to specify unconstrained paths)
|
726 |
|
|
TIMESPEC "TS_PHYTX_OPB" = FROM "TXCLK_GRP" TO "clkm" TIG;
|
727 |
|
|
TIMESPEC "TS_OPB_PHYTX" = FROM "clkm" TO "TXCLK_GRP" TIG;
|
728 |
|
|
TIMESPEC "TS_PHYRX_OPB" = FROM "RXCLK_GRP" TO "clkm" TIG;
|
729 |
|
|
TIMESPEC "TS_OPB_PHYRX" = FROM "clkm" TO "RXCLK_GRP" TIG;
|
730 |
|
|
|
731 |
|
|
#------------------------------------------------------------------------------
|
732 |
|
|
# IO Pad Location Constraints / Properties for AC97 Sound Controller
|
733 |
|
|
#------------------------------------------------------------------------------
|
734 |
|
|
|
735 |
|
|
#NET ac97_bit_clk LOC = AC13;
|
736 |
|
|
#NET ac97_bit_clk IOSTANDARD = LVCMOS33;
|
737 |
|
|
#NET ac97_bit_clk PERIOD = 80;
|
738 |
|
|
#NET ac97_sdata_in LOC = AC12;
|
739 |
|
|
#NET ac97_sdata_in IOSTANDARD = LVCMOS33;
|
740 |
|
|
#NET ac97_sdata_out LOC = AC11;
|
741 |
|
|
#NET ac97_sdata_out IOSTANDARD = LVCMOS33;
|
742 |
|
|
#NET ac97_sync LOC = AD11;
|
743 |
|
|
#NET ac97_sync IOSTANDARD = LVCMOS33;
|
744 |
|
|
|
745 |
|
|
|