URL
https://opencores.org/ocsvn/mips_enhanced/mips_enhanced/trunk
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| 1 |
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dimamali |
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| 2 |
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NET sram_clk FEEDBACK = 1.0 NET sram_clk_fb;
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| 3 |
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NET "clkm" TNM_NET = "clkm";
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| 4 |
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NET "clkml" TNM_NET = "clkml";
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| 5 |
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TIMESPEC "TS_clkm_clkml" = FROM "clkm" TO "clkml" TIG;
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| 6 |
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TIMESPEC "TS_clkml_clkm" = FROM "clkml" TO "clkm" TIG;
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| 7 |
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#NET "lock" TIG;
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| 8 |
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| 9 |
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NET phy_tx_data(*) TNM = gtxphypads;
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| 10 |
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NET "egtx_clk" TNM_NET = "egtx_clk";
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| 11 |
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TIMESPEC "TS_clkm_egtx_clk" = FROM "clkm" TO "egtx_clk" TIG;
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| 12 |
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TIMESPEC "TS_egtx_clk_clkm" = FROM "egtx_clk" TO "clkm" TIG;
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| 13 |
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#TIMESPEC "TSGTXOUT" = FROM "egtx_clk" TO "gtxphypads" 4.3 ns;
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| 14 |
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#TIMESPEC "TSGRXIN" = FROM "gtxphypads" TO "eth1_e1_m1000_u0_rxclk" 10 ns;
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| 15 |
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NET clk_100 period = 10.000 ;
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| 17 |
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NET clk_200 period = 5.000;
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| 18 |
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| 19 |
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INST "ddrsp0.ddrc0/ddr_phy0/ddr_phy0/xc4v.ddr_phy0/idelctrl[0].u" LOC = "IDELAYCTRL_X0Y0";
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| 20 |
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INST "ddrsp0.ddrc0/ddr_phy0/ddr_phy0/xc4v.ddr_phy0/idelctrl[1].u" LOC = "IDELAYCTRL_X0Y1";
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| 21 |
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INST "ddrsp0.ddrc0/ddr_phy0/ddr_phy0/xc4v.ddr_phy0/idelctrl[2].u" LOC = "IDELAYCTRL_X0Y5";
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| 22 |
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| 23 |
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NET sys_rst_in PULLUP;
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| 24 |
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NET sys_rst_in TIG;
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