1 |
2 |
dimamali |
------------------------------------------------------------------------------
|
2 |
|
|
-- LEON3 Demonstration design test bench
|
3 |
|
|
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
|
4 |
|
|
--
|
5 |
|
|
-- This program is free software; you can redistribute it and/or modify
|
6 |
|
|
-- it under the terms of the GNU General Public License as published by
|
7 |
|
|
-- the Free Software Foundation; either version 2 of the License, or
|
8 |
|
|
-- (at your option) any later version.
|
9 |
|
|
--
|
10 |
|
|
-- This program is distributed in the hope that it will be useful,
|
11 |
|
|
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
12 |
|
|
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
13 |
|
|
-- GNU General Public License for more details.
|
14 |
|
|
------------------------------------------------------------------------------
|
15 |
|
|
|
16 |
|
|
library ieee;
|
17 |
|
|
use ieee.std_logic_1164.all;
|
18 |
|
|
library grlib;
|
19 |
|
|
use grlib.stdlib.all;
|
20 |
|
|
library gaisler;
|
21 |
|
|
use gaisler.libdcom.all;
|
22 |
|
|
use gaisler.sim.all;
|
23 |
|
|
use gaisler.jtagtst.all;
|
24 |
|
|
library techmap;
|
25 |
|
|
use techmap.gencomp.all;
|
26 |
|
|
library micron;
|
27 |
|
|
use micron.components.all;
|
28 |
|
|
use work.debug.all;
|
29 |
|
|
|
30 |
|
|
use work.config.all; -- configuration
|
31 |
|
|
|
32 |
|
|
entity testbench is
|
33 |
|
|
generic (
|
34 |
|
|
fabtech : integer := CFG_FABTECH;
|
35 |
|
|
memtech : integer := CFG_MEMTECH;
|
36 |
|
|
padtech : integer := CFG_PADTECH;
|
37 |
|
|
clktech : integer := CFG_CLKTECH;
|
38 |
|
|
ncpu : integer := CFG_NCPU;
|
39 |
|
|
disas : integer := CFG_DISAS; -- Enable disassembly to console
|
40 |
|
|
dbguart : integer := CFG_DUART; -- Print UART on console
|
41 |
|
|
pclow : integer := CFG_PCLOW;
|
42 |
|
|
|
43 |
|
|
clkperiod : integer := 20; -- system clock period
|
44 |
|
|
romwidth : integer := 32; -- rom data width (8/32)
|
45 |
|
|
romdepth : integer := 16; -- rom address depth
|
46 |
|
|
sramwidth : integer := 32; -- ram data width (8/16/32)
|
47 |
|
|
sramdepth : integer := 18; -- ram address depth
|
48 |
|
|
srambanks : integer := 2 -- number of ram banks
|
49 |
|
|
);
|
50 |
|
|
port (
|
51 |
|
|
pci_rst : inout std_logic; -- PCI bus
|
52 |
|
|
pci_clk : in std_ulogic;
|
53 |
|
|
pci_gnt : in std_ulogic;
|
54 |
|
|
pci_idsel : in std_ulogic;
|
55 |
|
|
pci_lock : inout std_ulogic;
|
56 |
|
|
pci_ad : inout std_logic_vector(31 downto 0);
|
57 |
|
|
pci_cbe : inout std_logic_vector(3 downto 0);
|
58 |
|
|
pci_frame : inout std_ulogic;
|
59 |
|
|
pci_irdy : inout std_ulogic;
|
60 |
|
|
pci_trdy : inout std_ulogic;
|
61 |
|
|
pci_devsel : inout std_ulogic;
|
62 |
|
|
pci_stop : inout std_ulogic;
|
63 |
|
|
pci_perr : inout std_ulogic;
|
64 |
|
|
pci_par : inout std_ulogic;
|
65 |
|
|
pci_req : inout std_ulogic;
|
66 |
|
|
pci_serr : inout std_ulogic;
|
67 |
|
|
pci_host : in std_ulogic;
|
68 |
|
|
pci_66 : in std_ulogic
|
69 |
|
|
);
|
70 |
|
|
end;
|
71 |
|
|
|
72 |
|
|
architecture behav of testbench is
|
73 |
|
|
|
74 |
|
|
constant promfile : string := "prom.srec"; -- rom contents
|
75 |
|
|
constant sramfile : string := "sram.srec"; -- ram contents
|
76 |
|
|
constant sdramfile : string := "sdram.srec"; -- sdram contents
|
77 |
|
|
|
78 |
|
|
component leon3mp
|
79 |
|
|
generic (
|
80 |
|
|
fabtech : integer := CFG_FABTECH;
|
81 |
|
|
memtech : integer := CFG_MEMTECH;
|
82 |
|
|
padtech : integer := CFG_PADTECH;
|
83 |
|
|
clktech : integer := CFG_CLKTECH;
|
84 |
|
|
disas : integer := CFG_DISAS; -- Enable disassembly to console
|
85 |
|
|
dbguart : integer := CFG_DUART; -- Print UART on console
|
86 |
|
|
pclow : integer := CFG_PCLOW
|
87 |
|
|
);
|
88 |
|
|
port (
|
89 |
|
|
resetn : in std_ulogic;
|
90 |
|
|
clk : in std_ulogic;
|
91 |
|
|
pllref : in std_ulogic;
|
92 |
|
|
errorn : out std_ulogic;
|
93 |
|
|
address : out std_logic_vector(27 downto 0);
|
94 |
|
|
data : inout std_logic_vector(31 downto 0);
|
95 |
|
|
sa : out std_logic_vector(14 downto 0);
|
96 |
|
|
sd : inout std_logic_vector(63 downto 0);
|
97 |
|
|
sdclk : out std_ulogic;
|
98 |
|
|
sdcke : out std_logic_vector (1 downto 0); -- sdram clock enable
|
99 |
|
|
sdcsn : out std_logic_vector (1 downto 0); -- sdram chip select
|
100 |
|
|
sdwen : out std_ulogic; -- sdram write enable
|
101 |
|
|
sdrasn : out std_ulogic; -- sdram ras
|
102 |
|
|
sdcasn : out std_ulogic; -- sdram cas
|
103 |
|
|
sddqm : out std_logic_vector (7 downto 0); -- sdram dqm
|
104 |
|
|
dsutx : out std_ulogic; -- DSU tx data
|
105 |
|
|
dsurx : in std_ulogic; -- DSU rx data
|
106 |
|
|
dsuen : in std_ulogic;
|
107 |
|
|
dsubre : in std_ulogic;
|
108 |
|
|
dsuact : out std_ulogic;
|
109 |
|
|
txd1 : out std_ulogic; -- UART1 tx data
|
110 |
|
|
rxd1 : in std_ulogic; -- UART1 rx data
|
111 |
|
|
txd2 : out std_ulogic; -- UART1 tx data
|
112 |
|
|
rxd2 : in std_ulogic; -- UART1 rx data
|
113 |
|
|
ramsn : out std_logic_vector (4 downto 0);
|
114 |
|
|
ramoen : out std_logic_vector (4 downto 0);
|
115 |
|
|
rwen : out std_logic_vector (3 downto 0);
|
116 |
|
|
oen : out std_ulogic;
|
117 |
|
|
writen : out std_ulogic;
|
118 |
|
|
read : out std_ulogic;
|
119 |
|
|
iosn : out std_ulogic;
|
120 |
|
|
romsn : out std_logic_vector (1 downto 0);
|
121 |
|
|
gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
|
122 |
|
|
|
123 |
|
|
emdio : inout std_logic; -- ethernet PHY interface
|
124 |
|
|
etx_clk : in std_logic;
|
125 |
|
|
erx_clk : in std_logic;
|
126 |
|
|
erxd : in std_logic_vector(3 downto 0);
|
127 |
|
|
erx_dv : in std_logic;
|
128 |
|
|
erx_er : in std_logic;
|
129 |
|
|
erx_col : in std_logic;
|
130 |
|
|
erx_crs : in std_logic;
|
131 |
|
|
etxd : out std_logic_vector(3 downto 0);
|
132 |
|
|
etx_en : out std_logic;
|
133 |
|
|
etx_er : out std_logic;
|
134 |
|
|
emdc : out std_logic;
|
135 |
|
|
|
136 |
|
|
emddis : out std_logic;
|
137 |
|
|
epwrdwn : out std_logic;
|
138 |
|
|
ereset : out std_logic;
|
139 |
|
|
esleep : out std_logic;
|
140 |
|
|
epause : out std_logic;
|
141 |
|
|
|
142 |
|
|
pci_rst : inout std_logic; -- PCI bus
|
143 |
|
|
pci_clk : in std_ulogic;
|
144 |
|
|
pci_gnt : in std_ulogic;
|
145 |
|
|
pci_idsel : in std_ulogic;
|
146 |
|
|
pci_lock : inout std_ulogic;
|
147 |
|
|
pci_ad : inout std_logic_vector(31 downto 0);
|
148 |
|
|
pci_cbe : inout std_logic_vector(3 downto 0);
|
149 |
|
|
pci_frame : inout std_ulogic;
|
150 |
|
|
pci_irdy : inout std_ulogic;
|
151 |
|
|
pci_trdy : inout std_ulogic;
|
152 |
|
|
pci_devsel : inout std_ulogic;
|
153 |
|
|
pci_stop : inout std_ulogic;
|
154 |
|
|
pci_perr : inout std_ulogic;
|
155 |
|
|
pci_par : inout std_ulogic;
|
156 |
|
|
pci_req : inout std_ulogic;
|
157 |
|
|
pci_serr : inout std_ulogic;
|
158 |
|
|
pci_host : in std_ulogic;
|
159 |
|
|
pci_66 : in std_ulogic;
|
160 |
|
|
pci_arb_req : in std_logic_vector(0 to 3);
|
161 |
|
|
pci_arb_gnt : out std_logic_vector(0 to 3);
|
162 |
|
|
|
163 |
|
|
can_txd : out std_ulogic;
|
164 |
|
|
can_rxd : in std_ulogic;
|
165 |
|
|
can_stb : out std_ulogic;
|
166 |
|
|
|
167 |
|
|
spw_clk : in std_ulogic;
|
168 |
|
|
spw_rxd : in std_logic_vector(0 to 2);
|
169 |
|
|
spw_rxdn : in std_logic_vector(0 to 2);
|
170 |
|
|
spw_rxs : in std_logic_vector(0 to 2);
|
171 |
|
|
spw_rxsn : in std_logic_vector(0 to 2);
|
172 |
|
|
spw_txd : out std_logic_vector(0 to 2);
|
173 |
|
|
spw_txdn : out std_logic_vector(0 to 2);
|
174 |
|
|
spw_txs : out std_logic_vector(0 to 2);
|
175 |
|
|
spw_txsn : out std_logic_vector(0 to 2);
|
176 |
|
|
tck, tms, tdi : in std_ulogic;
|
177 |
|
|
tdo : out std_ulogic
|
178 |
|
|
|
179 |
|
|
);
|
180 |
|
|
end component;
|
181 |
|
|
|
182 |
|
|
signal clk : std_logic := '0';
|
183 |
|
|
signal Rst : std_logic := '0'; -- Reset
|
184 |
|
|
constant ct : integer := clkperiod/2;
|
185 |
|
|
|
186 |
|
|
signal address : std_logic_vector(27 downto 0);
|
187 |
|
|
signal data : std_logic_vector(31 downto 0);
|
188 |
|
|
|
189 |
|
|
signal ramsn : std_logic_vector(4 downto 0);
|
190 |
|
|
signal ramoen : std_logic_vector(4 downto 0);
|
191 |
|
|
signal rwen : std_logic_vector(3 downto 0);
|
192 |
|
|
signal rwenx : std_logic_vector(3 downto 0);
|
193 |
|
|
signal romsn : std_logic_vector(1 downto 0);
|
194 |
|
|
signal iosn : std_ulogic;
|
195 |
|
|
signal oen : std_ulogic;
|
196 |
|
|
signal read : std_ulogic;
|
197 |
|
|
signal writen : std_ulogic;
|
198 |
|
|
signal brdyn : std_ulogic;
|
199 |
|
|
signal bexcn : std_ulogic;
|
200 |
|
|
signal wdog : std_ulogic;
|
201 |
|
|
signal dsuen, dsutx, dsurx, dsubre, dsuact : std_ulogic;
|
202 |
|
|
signal dsurst : std_ulogic;
|
203 |
|
|
signal test : std_ulogic;
|
204 |
|
|
signal error : std_logic;
|
205 |
|
|
signal gpio : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
|
206 |
|
|
signal GND : std_ulogic := '0';
|
207 |
|
|
signal VCC : std_ulogic := '1';
|
208 |
|
|
signal NC : std_ulogic := 'Z';
|
209 |
|
|
signal clk2 : std_ulogic := '1';
|
210 |
|
|
|
211 |
|
|
signal sdcke : std_logic_vector ( 1 downto 0); -- clk en
|
212 |
|
|
signal sdcsn : std_logic_vector ( 1 downto 0); -- chip sel
|
213 |
|
|
signal sdwen : std_ulogic; -- write en
|
214 |
|
|
signal sdrasn : std_ulogic; -- row addr stb
|
215 |
|
|
signal sdcasn : std_ulogic; -- col addr stb
|
216 |
|
|
signal sddqm : std_logic_vector ( 7 downto 0); -- data i/o mask
|
217 |
|
|
signal sdclk : std_ulogic;
|
218 |
|
|
signal plllock : std_ulogic;
|
219 |
|
|
signal txd1, rxd1 : std_ulogic;
|
220 |
|
|
signal txd2, rxd2 : std_ulogic;
|
221 |
|
|
|
222 |
|
|
signal etx_clk, erx_clk, erx_dv, erx_er, erx_col, erx_crs, etx_en, etx_er : std_logic:='0';
|
223 |
|
|
signal erxd, etxd: std_logic_vector(3 downto 0):=(others=>'0');
|
224 |
|
|
signal erxdt, etxdt: std_logic_vector(7 downto 0):=(others=>'0');
|
225 |
|
|
signal emdc, emdio: std_logic;
|
226 |
|
|
signal gtx_clk : std_ulogic;
|
227 |
|
|
|
228 |
|
|
signal emddis : std_logic;
|
229 |
|
|
signal epwrdwn : std_logic;
|
230 |
|
|
signal ereset : std_logic;
|
231 |
|
|
signal esleep : std_logic;
|
232 |
|
|
signal epause : std_logic;
|
233 |
|
|
|
234 |
|
|
constant lresp : boolean := false;
|
235 |
|
|
|
236 |
|
|
signal sa : std_logic_vector(14 downto 0);
|
237 |
|
|
signal sd : std_logic_vector(63 downto 0);
|
238 |
|
|
|
239 |
|
|
signal pci_arb_req, pci_arb_gnt : std_logic_vector(0 to 3);
|
240 |
|
|
|
241 |
|
|
signal can_txd : std_ulogic;
|
242 |
|
|
signal can_rxd : std_ulogic;
|
243 |
|
|
signal can_stb : std_ulogic;
|
244 |
|
|
|
245 |
|
|
signal spw_clk : std_ulogic := '0';
|
246 |
|
|
signal spw_rxd : std_logic_vector(0 to 2) := "000";
|
247 |
|
|
signal spw_rxdn : std_logic_vector(0 to 2) := "000";
|
248 |
|
|
signal spw_rxs : std_logic_vector(0 to 2) := "000";
|
249 |
|
|
signal spw_rxsn : std_logic_vector(0 to 2) := "000";
|
250 |
|
|
signal spw_txd : std_logic_vector(0 to 2);
|
251 |
|
|
signal spw_txdn : std_logic_vector(0 to 2);
|
252 |
|
|
signal spw_txs : std_logic_vector(0 to 2);
|
253 |
|
|
signal spw_txsn : std_logic_vector(0 to 2);
|
254 |
|
|
|
255 |
|
|
signal tck, tms, tdi, tdo : std_ulogic;
|
256 |
|
|
|
257 |
|
|
constant CFG_SDEN : integer := CFG_SDCTRL + CFG_MCTRL_SDEN ;
|
258 |
|
|
constant CFG_SD64 : integer := CFG_SDCTRL_SD64 + CFG_MCTRL_SD64;
|
259 |
|
|
|
260 |
|
|
begin
|
261 |
|
|
|
262 |
|
|
-- clock and reset
|
263 |
|
|
|
264 |
|
|
spw_clk <= not spw_clk after 20 ns;
|
265 |
|
|
spw_rxd(0) <= spw_txd(0); spw_rxdn(0) <= spw_txdn(0);
|
266 |
|
|
spw_rxs(0) <= spw_txs(0); spw_rxsn(0) <= spw_txsn(0);
|
267 |
|
|
spw_rxd(1) <= spw_txd(1); spw_rxdn(1) <= spw_txdn(1);
|
268 |
|
|
spw_rxs(1) <= spw_txs(1); spw_rxsn(1) <= spw_txsn(1);
|
269 |
|
|
spw_rxd(2) <= spw_txd(0); spw_rxdn(2) <= spw_txdn(2);
|
270 |
|
|
spw_rxs(2) <= spw_txs(0); spw_rxsn(2) <= spw_txsn(2);
|
271 |
|
|
clk <= not clk after ct * 1 ns;
|
272 |
|
|
rst <= dsurst;
|
273 |
|
|
dsuen <= '1'; dsubre <= '0'; rxd1 <= '1';
|
274 |
|
|
--## can_rxd <= '1';
|
275 |
|
|
can_rxd <= can_txd; -- CAN LOOP BACK ##
|
276 |
|
|
|
277 |
|
|
d3 : leon3mp
|
278 |
|
|
generic map ( fabtech, memtech, padtech, clktech,
|
279 |
|
|
disas, dbguart, pclow )
|
280 |
|
|
port map (rst, clk, sdclk, error, address(27 downto 0), data,
|
281 |
|
|
sa, sd, sdclk, sdcke, sdcsn, sdwen, sdrasn, sdcasn, sddqm,
|
282 |
|
|
dsutx, dsurx, dsuen, dsubre, dsuact, txd1, rxd1, txd2, rxd2,
|
283 |
|
|
ramsn, ramoen, rwen, oen, writen, read, iosn, romsn, gpio,
|
284 |
|
|
emdio, etx_clk, erx_clk, erxd, erx_dv, erx_er, erx_col, erx_crs,
|
285 |
|
|
etxd, etx_en, etx_er, emdc, emddis, epwrdwn, ereset, esleep, epause,
|
286 |
|
|
pci_rst, pci_clk, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe,
|
287 |
|
|
pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr, pci_par,
|
288 |
|
|
pci_req, pci_serr, pci_host, pci_66, pci_arb_req, pci_arb_gnt,
|
289 |
|
|
can_txd, can_rxd, can_stb, spw_clk, spw_rxd, spw_rxdn, spw_rxs,
|
290 |
|
|
spw_rxsn, spw_txd, spw_txdn, spw_txs, spw_txsn, tck, tms, tdi, tdo);
|
291 |
|
|
|
292 |
|
|
-- optional sdram
|
293 |
|
|
|
294 |
|
|
sd0 : if (CFG_SDEN /= 0) and (CFG_MCTRL_SEPBUS = 0) generate
|
295 |
|
|
u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
|
296 |
|
|
PORT MAP(
|
297 |
|
|
Dq => data(31 downto 16), Addr => address(14 downto 2),
|
298 |
|
|
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
|
299 |
|
|
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
|
300 |
|
|
Dqm => sddqm(3 downto 2));
|
301 |
|
|
u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
|
302 |
|
|
PORT MAP(
|
303 |
|
|
Dq => data(15 downto 0), Addr => address(14 downto 2),
|
304 |
|
|
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
|
305 |
|
|
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
|
306 |
|
|
Dqm => sddqm(1 downto 0));
|
307 |
|
|
u2: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
|
308 |
|
|
PORT MAP(
|
309 |
|
|
Dq => data(31 downto 16), Addr => address(14 downto 2),
|
310 |
|
|
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
|
311 |
|
|
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
|
312 |
|
|
Dqm => sddqm(3 downto 2));
|
313 |
|
|
u3: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
|
314 |
|
|
PORT MAP(
|
315 |
|
|
Dq => data(15 downto 0), Addr => address(14 downto 2),
|
316 |
|
|
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
|
317 |
|
|
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
|
318 |
|
|
Dqm => sddqm(1 downto 0));
|
319 |
|
|
end generate;
|
320 |
|
|
|
321 |
|
|
sd1 : if (CFG_SDEN /= 0) and (CFG_MCTRL_SEPBUS = 1) generate
|
322 |
|
|
u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
|
323 |
|
|
PORT MAP(
|
324 |
|
|
Dq => sd(31 downto 16), Addr => sa(12 downto 0),
|
325 |
|
|
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
|
326 |
|
|
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
|
327 |
|
|
Dqm => sddqm(3 downto 2));
|
328 |
|
|
u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
|
329 |
|
|
PORT MAP(
|
330 |
|
|
Dq => sd(15 downto 0), Addr => sa(12 downto 0),
|
331 |
|
|
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
|
332 |
|
|
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
|
333 |
|
|
Dqm => sddqm(1 downto 0));
|
334 |
|
|
u2: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
|
335 |
|
|
PORT MAP(
|
336 |
|
|
Dq => sd(31 downto 16), Addr => sa(12 downto 0),
|
337 |
|
|
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
|
338 |
|
|
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
|
339 |
|
|
Dqm => sddqm(3 downto 2));
|
340 |
|
|
u3: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
|
341 |
|
|
PORT MAP(
|
342 |
|
|
Dq => sd(15 downto 0), Addr => sa(12 downto 0),
|
343 |
|
|
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
|
344 |
|
|
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
|
345 |
|
|
Dqm => sddqm(1 downto 0));
|
346 |
|
|
sd64 : if (CFG_SD64 /= 0) generate
|
347 |
|
|
u4: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
|
348 |
|
|
PORT MAP(
|
349 |
|
|
Dq => sd(63 downto 48), Addr => sa(12 downto 0),
|
350 |
|
|
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
|
351 |
|
|
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
|
352 |
|
|
Dqm => sddqm(7 downto 6));
|
353 |
|
|
u5: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
|
354 |
|
|
PORT MAP(
|
355 |
|
|
Dq => sd(47 downto 32), Addr => sa(12 downto 0),
|
356 |
|
|
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
|
357 |
|
|
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
|
358 |
|
|
Dqm => sddqm(5 downto 4));
|
359 |
|
|
u6: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
|
360 |
|
|
PORT MAP(
|
361 |
|
|
Dq => sd(63 downto 48), Addr => sa(12 downto 0),
|
362 |
|
|
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
|
363 |
|
|
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
|
364 |
|
|
Dqm => sddqm(7 downto 6));
|
365 |
|
|
u7: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
|
366 |
|
|
PORT MAP(
|
367 |
|
|
Dq => sd(47 downto 32), Addr => sa(12 downto 0),
|
368 |
|
|
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
|
369 |
|
|
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
|
370 |
|
|
Dqm => sddqm(5 downto 4));
|
371 |
|
|
end generate;
|
372 |
|
|
end generate;
|
373 |
|
|
|
374 |
|
|
prom0 : for i in 0 to (romwidth/8)-1 generate
|
375 |
|
|
sr0 : sram generic map (index => i, abits => romdepth, fname => promfile)
|
376 |
|
|
port map (address(romdepth+1 downto 2), data(31-i*8 downto 24-i*8), romsn(0),
|
377 |
|
|
rwen(i), oen);
|
378 |
|
|
end generate;
|
379 |
|
|
|
380 |
|
|
sbanks : for k in 0 to srambanks-1 generate
|
381 |
|
|
sram0 : for i in 0 to (sramwidth/8)-1 generate
|
382 |
|
|
sr0 : sram generic map (index => i, abits => sramdepth, fname => sramfile)
|
383 |
|
|
port map (address(sramdepth+1 downto 2), data(31-i*8 downto 24-i*8),
|
384 |
|
|
ramsn(k), rwen(i), ramoen(k));
|
385 |
|
|
end generate;
|
386 |
|
|
end generate;
|
387 |
|
|
|
388 |
|
|
phy0 : if (CFG_GRETH = 1) generate
|
389 |
|
|
emdio <= 'H';
|
390 |
|
|
erxd <= erxdt(3 downto 0);
|
391 |
|
|
etxdt <= "0000" & etxd;
|
392 |
|
|
|
393 |
|
|
p0: phy
|
394 |
|
|
generic map(base1000_t_fd => 0, base1000_t_hd => 0)
|
395 |
|
|
port map(rst, emdio, etx_clk, erx_clk, erxdt, erx_dv,
|
396 |
|
|
erx_er, erx_col, erx_crs, etxdt, etx_en, etx_er, emdc, gtx_clk);
|
397 |
|
|
end generate;
|
398 |
|
|
error <= 'H'; -- ERROR pull-up
|
399 |
|
|
|
400 |
|
|
iuerr : process
|
401 |
|
|
begin
|
402 |
|
|
wait for 2500 ns;
|
403 |
|
|
if to_x01(error) = '1' then wait on error; end if;
|
404 |
|
|
assert (to_x01(error) = '1')
|
405 |
|
|
report "*** IU in error mode, simulation halted ***"
|
406 |
|
|
severity failure ;
|
407 |
|
|
end process;
|
408 |
|
|
|
409 |
|
|
data <= buskeep(data), (others => 'H') after 250 ns;
|
410 |
|
|
sd <= buskeep(sd), (others => 'H') after 250 ns;
|
411 |
|
|
|
412 |
|
|
test0 : grtestmod
|
413 |
|
|
port map ( rst, clk, error, address(21 downto 2), data,
|
414 |
|
|
iosn, oen, writen, brdyn);
|
415 |
|
|
|
416 |
|
|
|
417 |
|
|
dsucom : process
|
418 |
|
|
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
|
419 |
|
|
variable w32 : std_logic_vector(31 downto 0);
|
420 |
|
|
variable c8 : std_logic_vector(7 downto 0);
|
421 |
|
|
constant txp : time := 160 * 1 ns;
|
422 |
|
|
begin
|
423 |
|
|
dsutx <= '1';
|
424 |
|
|
dsurst <= '0';
|
425 |
|
|
wait for 500 ns;
|
426 |
|
|
dsurst <= '1';
|
427 |
|
|
wait;
|
428 |
|
|
wait for 5000 ns;
|
429 |
|
|
txc(dsutx, 16#55#, txp); -- sync uart
|
430 |
|
|
|
431 |
|
|
-- txc(dsutx, 16#c0#, txp);
|
432 |
|
|
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
|
433 |
|
|
-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp);
|
434 |
|
|
-- txc(dsutx, 16#c0#, txp);
|
435 |
|
|
-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
|
436 |
|
|
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
|
437 |
|
|
-- txc(dsutx, 16#c0#, txp);
|
438 |
|
|
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
|
439 |
|
|
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
|
440 |
|
|
-- txc(dsutx, 16#c0#, txp);
|
441 |
|
|
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
|
442 |
|
|
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
|
443 |
|
|
|
444 |
|
|
txc(dsutx, 16#c0#, txp);
|
445 |
|
|
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
|
446 |
|
|
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
|
447 |
|
|
txc(dsutx, 16#c0#, txp);
|
448 |
|
|
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
|
449 |
|
|
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#6f#, txp);
|
450 |
|
|
txc(dsutx, 16#c0#, txp);
|
451 |
|
|
txa(dsutx, 16#90#, 16#11#, 16#00#, 16#00#, txp);
|
452 |
|
|
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
|
453 |
|
|
txc(dsutx, 16#c0#, txp);
|
454 |
|
|
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#04#, txp);
|
455 |
|
|
txa(dsutx, 16#00#, 16#02#, 16#20#, 16#01#, txp);
|
456 |
|
|
txc(dsutx, 16#c0#, txp);
|
457 |
|
|
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
|
458 |
|
|
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
|
459 |
|
|
|
460 |
|
|
txc(dsutx, 16#c0#, txp);
|
461 |
|
|
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
|
462 |
|
|
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
|
463 |
|
|
|
464 |
|
|
txc(dsutx, 16#c0#, txp);
|
465 |
|
|
txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
|
466 |
|
|
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
|
467 |
|
|
|
468 |
|
|
txc(dsutx, 16#c0#, txp);
|
469 |
|
|
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
|
470 |
|
|
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
|
471 |
|
|
txc(dsutx, 16#c0#, txp);
|
472 |
|
|
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
|
473 |
|
|
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
|
474 |
|
|
|
475 |
|
|
|
476 |
|
|
|
477 |
|
|
|
478 |
|
|
|
479 |
|
|
txc(dsutx, 16#c0#, txp);
|
480 |
|
|
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
|
481 |
|
|
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
|
482 |
|
|
|
483 |
|
|
txc(dsutx, 16#c0#, txp);
|
484 |
|
|
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
|
485 |
|
|
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
|
486 |
|
|
|
487 |
|
|
txc(dsutx, 16#c0#, txp);
|
488 |
|
|
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
|
489 |
|
|
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
|
490 |
|
|
|
491 |
|
|
txc(dsutx, 16#80#, txp);
|
492 |
|
|
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
|
493 |
|
|
rxi(dsurx, w32, txp, lresp);
|
494 |
|
|
|
495 |
|
|
txc(dsutx, 16#a0#, txp);
|
496 |
|
|
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
|
497 |
|
|
rxi(dsurx, w32, txp, lresp);
|
498 |
|
|
|
499 |
|
|
end;
|
500 |
|
|
|
501 |
|
|
begin
|
502 |
|
|
|
503 |
|
|
dsucfg(dsutx, dsurx);
|
504 |
|
|
|
505 |
|
|
wait;
|
506 |
|
|
end process;
|
507 |
|
|
|
508 |
|
|
jtagproc : process
|
509 |
|
|
begin
|
510 |
|
|
wait;
|
511 |
|
|
jtagcom(tdo, tck, tms, tdi, 100, 20, 16#40000000#, true);
|
512 |
|
|
wait;
|
513 |
|
|
end process;
|
514 |
|
|
|
515 |
|
|
end;
|