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Leon2 memory controller

CONFIG_MCTRL_LEON2

  Say Y here to enable the LEON2 memory controller. The controller

  can access PROM, I/O, SRAM and SDRAM. The bus width for PROM

  and SRAM is programmable to 8-, 16- or 32-bits.

8-bit memory support

CONFIG_MCTRL_8BIT

  If you say Y here, the PROM/SRAM memory controller will support

  8-bit mode, i.e. operate from 8-bit devices as if they were 32-bit.

  Say N to save a few hundred gates.

16-bit memory support

CONFIG_MCTRL_16BIT

  If you say Y here, the PROM/SRAM memory controller will support

  16-bit mode, i.e. operate from 16-bit devices as if they were 32-bit.

  Say N to save a few hundred gates.

Write strobe feedback

CONFIG_MCTRL_WFB

  If you say Y here, the PROM/SRAM write strobes (WRITEN, WEN) will

  be used to enable the data bus drivers during write cycles. This

  will guarantee that the data is still valid on the rising edge of

  the write strobe. If you say N, the write strobes and the data bus

  drivers will be clocked on the rising edge, potentially creating

  a hold time problem in external memory or I/O. However, in all

  practical cases, there is enough capacitance in the data bus lines

  to keep the value stable for a few (many?) nano-seconds after the

  buffers have been disabled, making it safe to say N and remove a

  combinational path in the netlist that might be difficult to

  analyze.

Write strobe feedback

CONFIG_MCTRL_5CS

  If you say Y here, the 5th (RAMSN[4]) SRAM chip select signal will

  be enabled. If you don't intend to use it, say N and save some gates.

SDRAM controller enable

CONFIG_MCTRL_SDRAM

  Say Y here to enabled the PC100/PC133 SDRAM controller. If you don't

  intend to use SDRAM, say N and save about 1 kgates.

SDRAM controller inverted clock

CONFIG_MCTRL_SDRAM_INVCLK

  If you say Y here, the SDRAM controller output signals will be delayed

  with 1/2 clock in respect to the SDRAM clock. This will allow the used

  of an SDRAM clock which in not strictly in phase with the internal

  clock. This option will limit the SDRAM frequency to 40 - 50 MHz.

  On FPGA targets without SDRAM clock synchronizations through PLL/DLL,

  say Y. On ASIC targets, say N and tell your foundry to balance the

  SDRAM clock output.

SDRAM separate address buses

CONFIG_MCTRL_SDRAM_SEPBUS

  Say Y here if your SDRAM is connected through separate address

  and data buses (SA & SD). This is the case on the GR-CPCI-XC2V6000

  board, but not on the GR-PCI-XC2V3000 or Avnet XCV1500E boards.

64-bit data bus

CONFIG_MCTRL_SDRAM_BUS64

  Say Y here to enable 64-bit SDRAM data bus.

Page burst enable

CONFIG_MCTRL_PAGE

  Say Y here to enable SDRAM page burst operation. This will implement

  read operations using page bursts rather than 8-word bursts and save

  about 500 gates (100 LUTs). Note that not all SDRAM supports page

  burst, so use this option with care.

Programmable page burst enable

CONFIG_MCTRL_PROGPAGE

  Say Y here to enable programmable SDRAM page burst operation. This

  will allow to dynamically enable/disable page burst by setting

  bit 17 in MCFG2.