URL https://opencores.org/ocsvn/mips_enhanced/mips_enhanced/trunk

Subversion Repositories mips_enhanced

[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [lib/] [gaisler/] [ambatest/] [README_ahbtbp.txt] - Blame information for rev 2

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################################################################################
AHB testbench Master example instantiation
################################################################################
 
ctrl  : ahbtb_ctrl_type. Used to control the AHB master using procedures.
 
ahbtbm0 : ahbtbm
generic map(hindex => 0) -- AMBA master index 0
port map(amba_reset, amba_clk, ctrl.i, ctrl.o, ahbmi, ahbmo(0));
 
 
################################################################################
Control procedures
################################################################################
 
ahbtbminit(ctrl);
  Function: Initialize control signals. Prints init message
  Input   : ctrl  : ahbtb_ctrl_type - control signals
 
--------------------------------------------------------------------------------
 
ahbtbmdone(stop, ctrl);
  Function: Prints done message. May stop simulation
  Input   : stop  : integer - (0/1) 1 = stop simulation
            ctrl  : ahbtb_ctrl_type - control signals
 
--------------------------------------------------------------------------------
 
ahbtbmidle(sync, ctrl);
  Function: Inserts idle cycle.
  Input   : sync  : integer - (0/1) 1 = Return then idle cycle has been executed.
            ctrl  : ahbtb_ctrl_type - control signals
 
--------------------------------------------------------------------------------
 
ahbwrite(address, data, size, debug, appidle , ctrl);
  Function: Execute a non-sequential AHB write cycle.
  Input   : address : std_logic_vector[31:0] - AHB address.
            data    : std_logic_vector[31:0] - Data to write.
            size    : std_logic_vector[1:0] - "00" = byte, "01" = half word,
                      "10" = word.
            debug   : integer - Sets the debug level.
            appidle : boolean - If true, append idle cycle.
            ctrl  : ahbtb_ctrl_type - control signals
 
--------------------------------------------------------------------------------
 
ahbwrite(address, data, size, htrans, hburst, debug, appidle , ctrl);
  Function: Execute a AHB write cycle.
  Input   : address : std_logic_vector[31:0] - AHB address.
            data    : std_logic_vector[31:0] - Data to write.
            size    : std_logic_vector[1:0] - "00" = byte, "01" = half word,
                      "10" = word.
            htrans  : std_logic_vector[1:0] - Sets transfer type "10" = non-seq,
                      "11" = seq.
            hburst  : std_logic - Controls the burst signal.
            debug   : integer - Sets the debug level.
            appidle : boolean - If true, append idle cycle.
            ctrl  : ahbtb_ctrl_type - control signals
 
--------------------------------------------------------------------------------
 
ahbwrite(address, data, size, count, debug, ctrl);
  Function: Execute a incremental AHB burst write.
  Input   : address : std_logic_vector[31:0] - Start AHB address.
            data    : std_logic_vector[31:0] - Initial data.
            size    : std_logic_vector[1:0] - "00" = byte, "01" = half word,
                      "10" = word.
            count   : integer - Sets the burst length.
            debug   : integer - Sets the debug level.
            ctrl  : ahbtb_ctrl_type - control signals
 
--------------------------------------------------------------------------------
 
ahbread (address, data, size, debug, appidle , ctrl);
  Function: Execute a non-sequential AHB write cycle.
  Input   : address : std_logic_vector[31:0] - AHB address.
            data    : std_logic_vector[31:0] - Data to compare with read result.
            size    : std_logic_vector[1:0] - "00" = byte, "01" = half word,
                      "10" = word.
            debug   : integer - Sets the debug level.
            appidle : boolean - If true, append idle cycle.
            ctrl  : ahbtb_ctrl_type - control signals
 
--------------------------------------------------------------------------------
 
ahbread (address, data, size, htrans, hburst, debug, appidle , ctrl);
  Function: Execute a AHB write cycle.
  Input   : address : std_logic_vector[31:0] - AHB address.
            data    : std_logic_vector[31:0] - Data to compare with read result.
            size    : std_logic_vector[1:0] - "00" = byte, "01" = half word,
                      "10" = word.
            htrans  : std_logic_vector[1:0] - Sets transfer type "10" = non-seq,
                      "11" = seq.
            hburst  : std_logic - Controls the burst signal.
            debug   : integer - Sets the debug level.
            appidle : boolean - If true, append idle cycle.
            ctrl  : ahbtb_ctrl_type - control signals
 
--------------------------------------------------------------------------------
 
ahbread (address, data, size, count, debug, ctrl);
  Function: Execute a incremental AHB burst write.
  Input   : address : std_logic_vector[31:0] - Start AHB address.
            data    : std_logic_vector[31:0] - initial Data to compare with read
                      result.
            size    : std_logic_vector[1:0] - "00" = byte, "01" = half word,
                      "10" = word.
            count   : integer - Sets the burst length.
            debug   : integer - Sets the debug level.
            ctrl  : ahbtb_ctrl_type - control signals
 
 
################################################################################
Debug levels
################################################################################
 
 
1 = Print on error
2 = Print all accesses
 
################################################################################
Template stimuli process
################################################################################
 
process
begin
 
  -- Initialize the control signals
  ahbtbminit(ctrl);
 
  -- Write 0x12345678 to address 0x40000000. Print access.
  ahbwrite(x"40000000", x"12345678", "10", "10", '1', 2, true , ctrl);
 
  -- Read address 0x40000000 and compare with 0x12345678. Print access.
  ahbread (x"40000000", x"12345678", "10", "11", '1', 2, true , ctrl);
 
  -- Burst write with start address 0x40000000. Data is 0xdead0000 - 0xdead0020
     No output in printed.
  ahbwrite(x"40000000", x"dead0000", "10", 32, 0, ctrl);
 
  -- Burst read with start address 0x40000000. Compare data is
     0xdead0000 - 0xdead0020. Print result if not equal.
  ahbread (x"40000000", x"dead0000", "10", 32, 1, ctrl);
 
  -- Stop simulation
  ahbtbdone(1, ctrl);
 
end process;
 

Line No.	Rev	Author	Line
1	2	dimamali	`################################################################################`
2			`AHB testbench Master example instantiation`
3			`################################################################################`
4
5			`ctrl : ahbtb_ctrl_type. Used to control the AHB master using procedures.`
6
7			`ahbtbm0 : ahbtbm`
8			`generic map(hindex => 0) -- AMBA master index 0`
9			`port map(amba_reset, amba_clk, ctrl.i, ctrl.o, ahbmi, ahbmo(0));`
10
11
12			`################################################################################`
13			`Control procedures`
14			`################################################################################`
15
16			`ahbtbminit(ctrl);`
17			`Function: Initialize control signals. Prints init message`
18			`Input : ctrl : ahbtb_ctrl_type - control signals`
19
20			`--------------------------------------------------------------------------------`
21
22			`ahbtbmdone(stop, ctrl);`
23			`Function: Prints done message. May stop simulation`
24			`Input : stop : integer - (0/1) 1 = stop simulation`
25			`ctrl : ahbtb_ctrl_type - control signals`
26
27			`--------------------------------------------------------------------------------`
28
29			`ahbtbmidle(sync, ctrl);`
30			`Function: Inserts idle cycle.`
31			`Input : sync : integer - (0/1) 1 = Return then idle cycle has been executed.`
32			`ctrl : ahbtb_ctrl_type - control signals`
33
34			`--------------------------------------------------------------------------------`
35
36			`ahbwrite(address, data, size, debug, appidle , ctrl);`
37			`Function: Execute a non-sequential AHB write cycle.`
38			`Input : address : std_logic_vector[31:0] - AHB address.`
39			`data : std_logic_vector[31:0] - Data to write.`
40			`size : std_logic_vector[1:0] - "00" = byte, "01" = half word,`
41			`"10" = word.`
42			`debug : integer - Sets the debug level.`
43			`appidle : boolean - If true, append idle cycle.`
44			`ctrl : ahbtb_ctrl_type - control signals`
45
46			`--------------------------------------------------------------------------------`
47
48			`ahbwrite(address, data, size, htrans, hburst, debug, appidle , ctrl);`
49			`Function: Execute a AHB write cycle.`
50			`Input : address : std_logic_vector[31:0] - AHB address.`
51			`data : std_logic_vector[31:0] - Data to write.`
52			`size : std_logic_vector[1:0] - "00" = byte, "01" = half word,`
53			`"10" = word.`
54			`htrans : std_logic_vector[1:0] - Sets transfer type "10" = non-seq,`
55			`"11" = seq.`
56			`hburst : std_logic - Controls the burst signal.`
57			`debug : integer - Sets the debug level.`
58			`appidle : boolean - If true, append idle cycle.`
59			`ctrl : ahbtb_ctrl_type - control signals`
60
61			`--------------------------------------------------------------------------------`
62
63			`ahbwrite(address, data, size, count, debug, ctrl);`
64			`Function: Execute a incremental AHB burst write.`
65			`Input : address : std_logic_vector[31:0] - Start AHB address.`
66			`data : std_logic_vector[31:0] - Initial data.`
67			`size : std_logic_vector[1:0] - "00" = byte, "01" = half word,`
68			`"10" = word.`
69			`count : integer - Sets the burst length.`
70			`debug : integer - Sets the debug level.`
71			`ctrl : ahbtb_ctrl_type - control signals`
72
73			`--------------------------------------------------------------------------------`
74
75			`ahbread (address, data, size, debug, appidle , ctrl);`
76			`Function: Execute a non-sequential AHB write cycle.`
77			`Input : address : std_logic_vector[31:0] - AHB address.`
78			`data : std_logic_vector[31:0] - Data to compare with read result.`
79			`size : std_logic_vector[1:0] - "00" = byte, "01" = half word,`
80			`"10" = word.`
81			`debug : integer - Sets the debug level.`
82			`appidle : boolean - If true, append idle cycle.`
83			`ctrl : ahbtb_ctrl_type - control signals`
84
85			`--------------------------------------------------------------------------------`
86
87			`ahbread (address, data, size, htrans, hburst, debug, appidle , ctrl);`
88			`Function: Execute a AHB write cycle.`
89			`Input : address : std_logic_vector[31:0] - AHB address.`
90			`data : std_logic_vector[31:0] - Data to compare with read result.`
91			`size : std_logic_vector[1:0] - "00" = byte, "01" = half word,`
92			`"10" = word.`
93			`htrans : std_logic_vector[1:0] - Sets transfer type "10" = non-seq,`
94			`"11" = seq.`
95			`hburst : std_logic - Controls the burst signal.`
96			`debug : integer - Sets the debug level.`
97			`appidle : boolean - If true, append idle cycle.`
98			`ctrl : ahbtb_ctrl_type - control signals`
99
100			`--------------------------------------------------------------------------------`
101
102			`ahbread (address, data, size, count, debug, ctrl);`
103			`Function: Execute a incremental AHB burst write.`
104			`Input : address : std_logic_vector[31:0] - Start AHB address.`
105			`data : std_logic_vector[31:0] - initial Data to compare with read`
106			`result.`
107			`size : std_logic_vector[1:0] - "00" = byte, "01" = half word,`
108			`"10" = word.`
109			`count : integer - Sets the burst length.`
110			`debug : integer - Sets the debug level.`
111			`ctrl : ahbtb_ctrl_type - control signals`
112
113
114			`################################################################################`
115			`Debug levels`
116			`################################################################################`
117
118
119			`1 = Print on error`
120			`2 = Print all accesses`
121
122			`################################################################################`
123			`Template stimuli process`
124			`################################################################################`
125
126			`process`
127			`begin`
128
129			`-- Initialize the control signals`
130			`ahbtbminit(ctrl);`
131
132			`-- Write 0x12345678 to address 0x40000000. Print access.`
133			`ahbwrite(x"40000000", x"12345678", "10", "10", '1', 2, true , ctrl);`
134
135			`-- Read address 0x40000000 and compare with 0x12345678. Print access.`
136			`ahbread (x"40000000", x"12345678", "10", "11", '1', 2, true , ctrl);`
137
138			`-- Burst write with start address 0x40000000. Data is 0xdead0000 - 0xdead0020`
139			`No output in printed.`
140			`ahbwrite(x"40000000", x"dead0000", "10", 32, 0, ctrl);`
141
142			`-- Burst read with start address 0x40000000. Compare data is`
143			`0xdead0000 - 0xdead0020. Print result if not equal.`
144			`ahbread (x"40000000", x"dead0000", "10", 32, 1, ctrl);`
145
146			`-- Stop simulation`
147			`ahbtbdone(1, ctrl);`
148
149			`end process;`
150

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Subversion Repositories mips_enhanced

[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [lib/] [gaisler/] [ambatest/] [README_ahbtbp.txt] - Blame information for rev 2