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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [lib/] [gaisler/] [can/] [can_mc.in.help] - Blame information for rev 2

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Line No. Rev Author Line
1 2 dimamali
CAN interface enable
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CONFIG_CAN_ENABLE
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  Say Y here to enable one or more CAN cores. The cores has one
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  AHB slave interface for accessing the control registers. The CAN core
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  is register-compatible with the SAJ1000 core from Philips, with a
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  few exceptions. See the GRLIP IP manual for details.
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CONFIG_CAN_NUM
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  Number of CAN cores. The module allows up to 8 independent
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  CAN cores to be implemented.
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CAN register address
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CONFIG_CANIO
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  The control registers of each CAN core occupies 256 bytes, and
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  address space needed for the full module is thus 2 Kbyte. The cores
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  are mapped in the AHB bus I/O area (0xFFF00000 - 0xFFFFF000).
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  This setting defines at which address in the I/O area the registers
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  appear (HADDR[19:8]).
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CAN interrupt
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CONFIG_CANIRQ
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  Defines which interrupt number the CAN core will generate.
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CAN interrupt
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CONFIG_CANSEPIRQ
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  Say Y here to assign an individual interrupt to each CAN core,
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  starting from the base interrupt number. If set to N, all
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  CAN cores will generate the same interrupt.
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CAN FT memories
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CONFIG_CAN_FT
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  If you say Y here, the CAN FIFOs will be implemented using
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  SEU protected RAM blocks. Only applicable to the FT version
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  of grlib.
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CAN Synchronous reset
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CONFIG_CAN_SYNCRST
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  If you say Y here, the CAN core will be implemented with
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  synchronous reset rather than asynchronous. This is needed
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  when the target library does not implement registers with
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  async reset. Unless you know what you are doing, say N.
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