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dimamali |
------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003, Gaisler Research
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-----------------------------------------------------------------------------
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-- Entity: can_oc
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-- File: can_oc.vhd
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-- Author: Jiri Gaisler - Gaisler Research
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-- Description: AHB interface for the OpenCores CAN MAC
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library grlib;
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use grlib.amba.all;
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use grlib.stdlib.all;
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use grlib.devices.all;
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library techmap;
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use techmap.gencomp.all;
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library gaisler;
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use gaisler.can.all;
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entity can_rd is
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generic (
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slvndx : integer := 0;
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ioaddr : integer := 16#000#;
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iomask : integer := 16#FF0#;
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irq : integer := 0;
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memtech : integer := DEFMEMTECH;
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syncrst : integer := 0;
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dmap : integer := 0);
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port (
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resetn : in std_logic;
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clk : in std_logic;
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ahbsi : in ahb_slv_in_type;
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ahbso : out ahb_slv_out_type;
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can_rxi : in std_logic_vector(1 downto 0);
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can_txo : out std_logic_vector(1 downto 0)
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);
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end;
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architecture rtl of can_rd is
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constant ncores : integer := 1;
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constant sepirq : integer := 0;
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constant REVISION : amba_version_type := ncores-1;
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constant hconfig : ahb_config_type := (
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4 => ahb_iobar(ioaddr, iomask), others => zero32);
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type ahbregs is record
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hsel : std_ulogic;
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hwrite : std_ulogic;
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hwrite2 : std_ulogic;
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htrans : std_logic_vector(1 downto 0);
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haddr : std_logic_vector(10 downto 0);
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hwdata : std_logic_vector(7 downto 0);
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herr : std_ulogic;
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hready : std_ulogic;
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ws : std_logic_vector(1 downto 0);
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irqi : std_logic_vector(ncores-1 downto 0);
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irqo : std_logic_vector(ncores-1 downto 0);
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muxsel : std_logic;
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writemux : std_logic;
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end record;
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subtype cdata is std_logic_vector(7 downto 0);
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type cdataarr is array (0 to 7) of cdata;
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signal data_out : cdataarr;
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signal reset : std_logic;
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signal irqo : std_logic_vector(ncores-1 downto 0);
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signal addr : std_logic_vector(7 downto 0);
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signal vcc, gnd : std_ulogic;
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signal r, rin : ahbregs;
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signal can_lrxi, can_ltxo : std_logic;
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begin
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gnd <= '0'; vcc <= '1'; reset <= not resetn;
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comb : process(ahbsi, r, resetn, data_out, irqo)
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variable v : ahbregs;
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variable hresp : std_logic_vector(1 downto 0);
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variable dataout : std_logic_vector(7 downto 0);
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variable irqvec : std_logic_vector(NAHBIRQ-1 downto 0);
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variable vmuxreg : std_logic;
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begin
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v := r;
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if (r.hsel = '1' ) and (r.ws /= "11") then v.ws := r.ws + 1; end if;
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if ahbsi.hready = '1' then
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v.hsel := ahbsi.hsel(slvndx);
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v.haddr := ahbsi.haddr(10 downto 0);
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v.htrans := ahbsi.htrans;
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v.hwrite := ahbsi.hwrite;
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v.herr := orv(ahbsi.hsize) and ahbsi.hwrite;
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v.ws := "00";
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end if;
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v.hready := (r.hsel and r.ws(1) and not r.ws(0)) or not resetn
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or (ahbsi.hready and not ahbsi.htrans(1));
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vmuxreg := not r.haddr(7) and r.haddr(6);
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--v.hwrite2 := r.hwrite and r.hsel and r.htrans(1) and r.ws(1)
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-- and not r.ws(0) and not r.herr;
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v.hwrite2 := r.hwrite and r.hsel and r.htrans(1) and r.ws(1)
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and not r.ws(0) and not r.herr and not vmuxreg;
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v.writemux := r.hwrite and r.hsel and r.htrans(1) and r.ws(1)
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and not r.ws(0) and vmuxreg;
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if (r.herr and r.ws(1)) = '1' then hresp := HRESP_ERROR;
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else hresp := HRESP_OKAY; end if;
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case r.haddr(1 downto 0) is
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when "00" => v.hwdata := ahbsi.hwdata(31 downto 24);
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when "01" => v.hwdata := ahbsi.hwdata(23 downto 16);
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when "10" => v.hwdata := ahbsi.hwdata(15 downto 8);
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when others => v.hwdata := ahbsi.hwdata(7 downto 0);
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end case;
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--dataout := data_out(0);
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if r.haddr(7 downto 6) = "01" then
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dataout := (others => r.muxsel);
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if r.writemux = '1' then
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v.muxsel := r.hwdata(0);
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end if;
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else
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dataout := data_out(0);
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end if;
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-- Interrupt goes to low when appeard and is normal high
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-- but the irq controller from leon is active high and the interrupt should appear only
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-- for 1 Clk cycle,
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v.irqi := irqo; v.irqo:= (r.irqi and not irqo);
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irqvec := (others => '0');
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if sepirq = 1 then irqvec(ncores-1+irq downto irq) := r.irqo;
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else irqvec(irq) := orv(r.irqo); end if;
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ahbso.hirq <= irqvec;
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ahbso.hrdata <= dataout & dataout & dataout & dataout;
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ahbso.hresp <= hresp; rin <= v;
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end process;
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-- Double mapping of registers [byte (offset 0), word (offset 0x80)]
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dmap0 : if dmap = 0 generate
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addr <= r.haddr(7 downto 0);
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end generate;
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dmap1 : if dmap = 1 generate
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addr <= "000"&r.haddr(6 downto 2) when r.haddr(7) = '1' else
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r.haddr(7 downto 0);
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end generate;
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reg : process(clk)
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begin if clk'event and clk = '1' then r <= rin; end if; end process;
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cmod : can_mod generic map (memtech, syncrst)
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--port map (reset, clk, r.hsel, r.hwrite2, r.haddr(7 downto 0), r.hwdata,
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port map (reset, clk, r.hsel, r.hwrite2, addr, r.hwdata,
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data_out(0), irqo(0), can_lrxi, can_ltxo, ahbsi.testen);
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cmux : canmux port map (r.muxsel, can_lrxi, can_ltxo, can_rxi, can_txo);
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ahbso.hconfig <= hconfig;
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ahbso.hindex <= slvndx;
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ahbso.hsplit <= (others => '0');
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ahbso.hcache <= '0';
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ahbso.hready <= r.hready;
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-- pragma translate_off
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bootmsg : report_version
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generic map (
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"can_oc" & tost(slvndx) &
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": SJA1000 Compatible CAN MAC, revision " & tost(REVISION) &
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", irq " & tost(irq));
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-- pragma translate_on
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end;
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