Subversion Repositories mips_enhanced

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  comment 'DDR2 SDRAM controller             '

    bool 'Enable DDR2 SDRAM controller       ' CONFIG_DDR2SP

    if [ "$CONFIG_DDR2SP" = "y" ]; then

      bool 'Enable power-on initialization       ' CONFIG_DDR2SP_INIT

      int 'Memory frequency (MHz)  ' CONFIG_DDR2SP_FREQ 100

      int 'Refresh to Activate (tRFC) in ns  ' CONFIG_DDR2SP_TRFC 130

      if [ "$CONFIG_DDR2SP_INIT" = "y" ]; then

        int 'Column address bits (9 - 12)  ' CONFIG_DDR2SP_COL 9

        int 'Chip select bank size (Mbyte) ' CONFIG_DDR2SP_MBYTE 16

      fi

        int 'Data width (64, 32, 16) bit ' CONFIG_DDR2SP_DATAWIDTH 64

        int 'Input pad delay for byte 0 (0 - 63)' CONFIG_DDR2SP_DELAY0 0

        int 'Input pad delay for byte 1 (0 - 63)' CONFIG_DDR2SP_DELAY1 0

        int 'Input pad delay for byte 2 (0 - 63)' CONFIG_DDR2SP_DELAY2 0

        int 'Input pad delay for byte 3 (0 - 63)' CONFIG_DDR2SP_DELAY3 0

        int 'Input pad delay for byte 4 (0 - 63)' CONFIG_DDR2SP_DELAY4 0

        int 'Input pad delay for byte 5 (0 - 63)' CONFIG_DDR2SP_DELAY5 0

        int 'Input pad delay for byte 6 (0 - 63)' CONFIG_DDR2SP_DELAY6 0

        int 'Input pad delay for byte 7 (0 - 63)' CONFIG_DDR2SP_DELAY7 0

    fi

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