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dimamali |
------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003, Gaisler Research
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-----------------------------------------------------------------------------
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-- Entity: ddrsp64a
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-- File: ddrsp64a.vhd
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-- Author: Jiri Gaisler - Gaisler Research
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-- Description: 64-bit DDR266 memory controller with asych AHB interface
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library grlib;
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use grlib.amba.all;
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use grlib.stdlib.all;
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library gaisler;
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use grlib.devices.all;
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use gaisler.memctrl.all;
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library techmap;
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use techmap.gencomp.all;
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entity ddrsp64a is
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generic (
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memtech : integer := 0;
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hindex : integer := 0;
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haddr : integer := 0;
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hmask : integer := 16#f00#;
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ioaddr : integer := 16#000#;
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iomask : integer := 16#fff#;
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MHz : integer := 100;
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col : integer := 9;
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Mbyte : integer := 8;
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fast : integer := 0;
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pwron : integer := 0;
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oepol : integer := 0;
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mobile : integer := 0;
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confapi : integer := 0;
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conf0 : integer := 0;
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conf1 : integer := 0;
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regoutput : integer := 0
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);
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port (
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rst : in std_ulogic;
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clk_ddr : in std_ulogic;
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clk_ahb : in std_ulogic;
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ahbsi : in ahb_slv_in_type;
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ahbso : out ahb_slv_out_type;
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sdi : in sdctrl_in_type;
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sdo : out sdctrl_out_type
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);
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end;
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architecture rtl of ddrsp64a is
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constant REVISION : integer := 0;
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constant CMD_PRE : std_logic_vector(2 downto 0) := "010";
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constant CMD_REF : std_logic_vector(2 downto 0) := "100";
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constant CMD_LMR : std_logic_vector(2 downto 0) := "110";
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constant CMD_EMR : std_logic_vector(2 downto 0) := "111";
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constant PM_PD : std_logic_vector(2 downto 0) := "001";
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constant PM_SR : std_logic_vector(2 downto 0) := "010";
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constant PM_CKS : std_logic_vector(2 downto 0) := "100";
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constant PM_DPD : std_logic_vector(2 downto 0) := "101";
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constant abuf : integer := 6;
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constant hconfig : ahb_config_type := (
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4 => ahb_membar(haddr, '1', '1', hmask),
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5 => ahb_iobar(ioaddr, iomask),
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others => zero32);
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type mcycletype is (midle, active, ext, leadout);
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type ahb_state_type is (midle, rhold, dread, dwrite, whold1, whold2);
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type sdcycletype is (act1, act2, act3, rd1, rd2, rd2a, rd3, rd3a, rd4, rd5, rd6, rd7, rd8,
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wr1, wr2, wr3, wr4a, wr4, wr5, sidle, ioreg1, ioreg2,
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sref, cks, pd, dpd, srr1, srr2, srr3);
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type icycletype is (iidle, pre, ref1, ref2, emode, lmode, finish);
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-- sdram configuration register
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type sdram_cfg_type is record
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command : std_logic_vector(2 downto 0);
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csize : std_logic_vector(1 downto 0);
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bsize : std_logic_vector(2 downto 0);
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trcd : std_ulogic; -- tCD : 2/3 clock cycles
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trfc : std_logic_vector(2 downto 0);
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trp : std_ulogic; -- precharge to activate: 2/3 clock cycles
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refresh : std_logic_vector(11 downto 0);
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renable : std_ulogic;
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dllrst : std_ulogic;
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refon : std_ulogic;
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cke : std_ulogic;
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pasr : std_logic_vector(5 downto 0); -- pasr(2:0) (pasr(5:3) used to detect update)
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tcsr : std_logic_vector(3 downto 0); -- tcrs(1:0) (tcrs(3:2) used to detect update)
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ds : std_logic_vector(5 downto 0); -- ds(1:0) (ds(3:2) used to detect update)
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pmode : std_logic_vector(2 downto 0); -- Power-Saving mode
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mobileen : std_logic_vector(1 downto 0); -- Mobile SD support, Mobile SD enabled
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txsr : std_logic_vector(3 downto 0); -- Exit Self Refresh timing
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txp : std_logic; -- Exit Power-Down timing
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tcke : std_logic; -- Clock enable timing
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cl : std_logic; -- CAS latency 2/3 (0/1)
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conf : std_logic_vector(63 downto 0); -- PHY control
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end record;
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type access_param is record
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haddr : std_logic_vector(31 downto 0);
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size : std_logic_vector(1 downto 0);
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hwrite : std_ulogic;
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hio : std_ulogic;
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end record;
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-- local registers
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type ahb_reg_type is record
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hready : std_ulogic;
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hsel : std_ulogic;
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hio : std_ulogic;
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startsd : std_ulogic;
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ready : std_ulogic;
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ready2 : std_ulogic;
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write : std_logic_vector(3 downto 0);
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state : ahb_state_type;
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haddr : std_logic_vector(31 downto 0);
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hrdata : std_logic_vector(31 downto 0);
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hwdata : std_logic_vector(31 downto 0);
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hwrite : std_ulogic;
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htrans : std_logic_vector(1 downto 0);
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hresp : std_logic_vector(1 downto 0);
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raddr : std_logic_vector(abuf-1 downto 0);
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size : std_logic_vector(1 downto 0);
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acc : access_param;
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end record;
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type ddr_reg_type is record
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startsd : std_ulogic;
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startsdold : std_ulogic;
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burst : std_ulogic;
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hready : std_ulogic;
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bdrive : std_ulogic;
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qdrive : std_ulogic;
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nbdrive : std_ulogic;
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mstate : mcycletype;
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sdstate : sdcycletype;
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cmstate : mcycletype;
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istate : icycletype;
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trfc : std_logic_vector(3 downto 0);
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refresh : std_logic_vector(11 downto 0);
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sdcsn : std_logic_vector(1 downto 0);
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sdwen : std_ulogic;
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rasn : std_ulogic;
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casn : std_ulogic;
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dqm : std_logic_vector(15 downto 0);
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dqm_dly : std_logic_vector(15 downto 0); -- *** ??? delay ctrl
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wdata : std_logic_vector(127 downto 0); -- *** ??? delay ctrl
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address : std_logic_vector(15 downto 2); -- memory address
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ba : std_logic_vector( 1 downto 0);
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waddr : std_logic_vector(abuf-1 downto 0);
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cfg : sdram_cfg_type;
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hrdata : std_logic_vector(127 downto 0);
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idlecnt : std_logic_vector(3 downto 0); -- Counter, 16 idle clock sycles before entering Power-Saving mode
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ck : std_logic_vector(2 downto 0); -- Clock stop signal, 0 = clock stoped, 1 = clock running
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txp : std_logic;
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tcke : std_logic;
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sref_tmpcom : std_logic_vector(2 downto 0); -- Save SD command when exit sref
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sdo_bdrive : std_logic; -- *** ??? delay ctrl
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sdo_qdrive : std_logic; -- *** ??? delay ctrl
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ck_dly : std_logic_vector(2 downto 0); -- *** ??? delay ctrl
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cke_dly : std_logic; -- *** ??? delay ctrl
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end record;
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signal vcc : std_ulogic;
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signal r, ri : ddr_reg_type;
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signal ra, rai : ahb_reg_type;
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signal rbdrive, ribdrive : std_logic_vector(31 downto 0);
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signal rdata, wdata : std_logic_vector(127 downto 0);
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signal ddr_rst : std_logic;
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signal ddr_rst_gen : std_logic_vector(3 downto 0);
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attribute syn_preserve : boolean;
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attribute syn_preserve of rbdrive : signal is true;
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begin
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vcc <= '1';
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ddr_rst <= (ddr_rst_gen(3) and ddr_rst_gen(2) and ddr_rst_gen(1) and rst); -- Reset signal in DDR clock domain
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ahb_ctrl : process(rst, ahbsi, r, ra, rdata)
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variable v : ahb_reg_type; -- local variables for registers
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variable startsd : std_ulogic;
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variable dout : std_logic_vector(31 downto 0);
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begin
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v := ra; v.hresp := HRESP_OKAY; v.write := "0000";
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case ra.raddr(1 downto 0) is
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when "00" => v.hrdata := rdata(127 downto 96);
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when "01" => v.hrdata := rdata(95 downto 64);
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when "10" => v.hrdata := rdata(63 downto 32);
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when others => v.hrdata := rdata(31 downto 0);
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end case;
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v.ready := not (ra.startsd xor r.startsdold);
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v.ready2 := ra.ready;
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if ((ahbsi.hready and ahbsi.hsel(hindex)) = '1') then
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v.htrans := ahbsi.htrans; v.haddr := ahbsi.haddr;
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v.size := ahbsi.hsize(1 downto 0); v.hwrite := ahbsi.hwrite;
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if ahbsi.htrans(1) = '1' then
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v.hio := ahbsi.hmbsel(1);
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v.hsel := '1'; v.hready := '0';
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end if;
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end if;
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if ahbsi.hready = '1' then v.hsel := ahbsi.hsel(hindex); end if;
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-- if (ra.hsel and ra.hio and not ra.hready) = '1' then v.hready := '1'; end if;
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case ra.state is
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when midle =>
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if ((v.hsel and v.htrans(1)) = '1') then
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if v.hwrite = '0' then
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v.state := rhold; v.startsd := not ra.startsd;
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else
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v.state := dwrite; v.hready := '1';
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-- v.write(0) := not v.haddr(2); v.write(1) := v.haddr(2);
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v.write := decode(v.haddr(3 downto 2));
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end if;
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end if;
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v.raddr := ra.haddr(7 downto 2);
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v.ready := '0'; v.ready2 := '0';
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-- if not ((ra.hsel and ra.htrans(1) and not ra.htrans(0)) = '1') then
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if ahbsi.hready = '1' then
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v.acc := (v.haddr, v.size, v.hwrite, v.hio);
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end if;
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when rhold =>
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v.raddr := ra.haddr(7 downto 2);
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if ra.ready2 = '1' then
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v.state := dread; v.hready := '1'; v.raddr := ra.raddr + 1;
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end if;
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when dread =>
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v.raddr := ra.raddr + 1; v.hready := '1';
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if ((v.hsel and v.htrans(1) and v.htrans(0)) = '0') or
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256 |
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(ra.raddr(2 downto 0) = "000")
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then v.state := midle; v.hready := '0'; end if;
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258 |
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v.acc := (v.haddr, v.size, v.hwrite, v.hio);
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259 |
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when dwrite =>
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260 |
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v.raddr := ra.haddr(7 downto 2); v.hready := '1';
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-- v.write(0) := not v.haddr(2); v.write(1) := v.haddr(2);
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262 |
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v.write := decode(v.haddr(3 downto 2));
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263 |
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if ((v.hsel and v.htrans(1) and v.htrans(0)) = '0') or
|
264 |
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(ra.haddr(4 downto 2) = "111")
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265 |
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then
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266 |
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v.startsd := not ra.startsd; v.state := whold1;
|
267 |
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v.write := "0000"; v.hready := '0';
|
268 |
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end if;
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269 |
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when whold1 =>
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270 |
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v.state := whold2; v.ready := '0';
|
271 |
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when whold2 =>
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272 |
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if ra.ready = '1' then
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273 |
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v.state := midle; v.acc := (v.haddr, v.size, v.hwrite, v.hio);
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274 |
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end if;
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275 |
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end case;
|
276 |
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|
277 |
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v.hwdata := ahbsi.hwdata;
|
278 |
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|
279 |
|
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if (ahbsi.hready and ahbsi.hsel(hindex) ) = '1' then
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280 |
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if ahbsi.htrans(1) = '0' then v.hready := '1'; end if;
|
281 |
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end if;
|
282 |
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|
283 |
|
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dout := ra.hrdata(31 downto 0);
|
284 |
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|
285 |
|
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if rst = '0' then
|
286 |
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v.hsel := '0';
|
287 |
|
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v.hready := '1';
|
288 |
|
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v.state := midle;
|
289 |
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v.startsd := '0';
|
290 |
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v.hio := '0';
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291 |
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end if;
|
292 |
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|
293 |
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rai <= v;
|
294 |
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ahbso.hready <= ra.hready;
|
295 |
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ahbso.hresp <= ra.hresp;
|
296 |
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ahbso.hrdata <= dout;
|
297 |
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ahbso.hcache <= not ra.hio;
|
298 |
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|
299 |
|
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end process;
|
300 |
|
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|
301 |
|
|
ddr_ctrl : process(ddr_rst, r, ra, sdi, rbdrive, wdata)
|
302 |
|
|
variable v : ddr_reg_type; -- local variables for registers
|
303 |
|
|
variable startsd : std_ulogic;
|
304 |
|
|
variable dqm : std_logic_vector(15 downto 0);
|
305 |
|
|
variable raddr : std_logic_vector(13 downto 0);
|
306 |
|
|
variable adec : std_ulogic;
|
307 |
|
|
variable rams : std_logic_vector(1 downto 0);
|
308 |
|
|
variable ba : std_logic_vector(1 downto 0);
|
309 |
|
|
variable haddr : std_logic_vector(31 downto 0);
|
310 |
|
|
variable hsize : std_logic_vector(1 downto 0);
|
311 |
|
|
variable hwrite : std_ulogic;
|
312 |
|
|
variable htrans : std_logic_vector(1 downto 0);
|
313 |
|
|
variable hready : std_ulogic;
|
314 |
|
|
variable vbdrive : std_logic_vector(31 downto 0);
|
315 |
|
|
variable bdrive : std_ulogic;
|
316 |
|
|
variable writecfg: std_ulogic;
|
317 |
|
|
variable regsd1 : std_logic_vector(31 downto 0); -- data from registers
|
318 |
|
|
variable regsd2 : std_logic_vector(31 downto 0); -- data from registers
|
319 |
|
|
variable regsd3 : std_logic_vector(31 downto 0); -- data from registers
|
320 |
|
|
variable arefresh : std_logic;
|
321 |
|
|
begin
|
322 |
|
|
|
323 |
|
|
-- Variable default settings to avoid latches
|
324 |
|
|
|
325 |
|
|
v := r; v.hready := '0'; writecfg := '0'; vbdrive := rbdrive;
|
326 |
|
|
v.hrdata := sdi.data; v.qdrive :='0'; v.txp := '0'; v.tcke := '0';
|
327 |
|
|
arefresh := '0';
|
328 |
|
|
v.wdata := wdata; -- *** ??? delay ctrl
|
329 |
|
|
v.dqm_dly := r.dqm; -- *** ??? delay ctrl
|
330 |
|
|
v.ck_dly := r.ck; -- *** ??? delay ctrl
|
331 |
|
|
v.cke_dly := r.cfg.cke; -- *** ??? delay ctrl
|
332 |
|
|
|
333 |
|
|
regsd1 := (others => '0');
|
334 |
|
|
regsd1(31 downto 15) := r.cfg.refon & r.cfg.trp & r.cfg.trfc &
|
335 |
|
|
r.cfg.trcd & r.cfg.bsize & r.cfg.csize & r.cfg.command &
|
336 |
|
|
r.cfg.dllrst & r.cfg.renable & r.cfg.cke;
|
337 |
|
|
regsd1(11 downto 0) := r.cfg.refresh;
|
338 |
|
|
regsd2 := (others => '0');
|
339 |
|
|
regsd2(8 downto 0) := conv_std_logic_vector(MHz, 9);
|
340 |
|
|
regsd2(14 downto 12) := conv_std_logic_vector(3, 3);
|
341 |
|
|
regsd2(15) := r.cfg.mobileen(1); -- Mobile DDR support
|
342 |
|
|
regsd2(19 downto 16) := conv_std_logic_vector(confapi, 4);
|
343 |
|
|
regsd3 := (others => '0');
|
344 |
|
|
regsd3(31) := r.cfg.mobileen(0); -- Mobile DDR enable
|
345 |
|
|
regsd3(24 downto 19) := r.cfg.tcke & r.cfg.txsr & r.cfg.txp;
|
346 |
|
|
regsd3(18 downto 16) := r.cfg.pmode;
|
347 |
|
|
regsd3( 7 downto 0) := r.cfg.ds(2 downto 0) & r.cfg.tcsr(1 downto 0)
|
348 |
|
|
& r.cfg.pasr(2 downto 0);
|
349 |
|
|
|
350 |
|
|
if ra.acc.haddr(4) = '1' and confapi /= 0 then
|
351 |
|
|
regsd2(31 downto 0) := r.cfg.conf(31 downto 0);
|
352 |
|
|
regsd3(31 downto 0) := r.cfg.conf(63 downto 32);
|
353 |
|
|
end if;
|
354 |
|
|
|
355 |
|
|
|
356 |
|
|
-- generate DQM from address and write size
|
357 |
|
|
|
358 |
|
|
case ra.acc.size is
|
359 |
|
|
when "00" =>
|
360 |
|
|
case ra.acc.haddr(3 downto 0) is
|
361 |
|
|
when "0000" => dqm := "0111111111111111";
|
362 |
|
|
when "0001" => dqm := "1011111111111111";
|
363 |
|
|
when "0010" => dqm := "1101111111111111";
|
364 |
|
|
when "0011" => dqm := "1110111111111111";
|
365 |
|
|
when "0100" => dqm := "1111011111111111";
|
366 |
|
|
when "0101" => dqm := "1111101111111111";
|
367 |
|
|
when "0110" => dqm := "1111110111111111";
|
368 |
|
|
when "0111" => dqm := "1111111011111111";
|
369 |
|
|
when "1000" => dqm := "1111111101111111";
|
370 |
|
|
when "1001" => dqm := "1111111110111111";
|
371 |
|
|
when "1010" => dqm := "1111111111011111";
|
372 |
|
|
when "1011" => dqm := "1111111111101111";
|
373 |
|
|
when "1100" => dqm := "1111111111110111";
|
374 |
|
|
when "1101" => dqm := "1111111111111011";
|
375 |
|
|
when "1110" => dqm := "1111111111111101";
|
376 |
|
|
when others => dqm := "1111111111111110";
|
377 |
|
|
end case;
|
378 |
|
|
when "01" =>
|
379 |
|
|
case ra.acc.haddr(3 downto 1) is
|
380 |
|
|
when "000" => dqm := "0011111111111111";
|
381 |
|
|
when "001" => dqm := "1100111111111111";
|
382 |
|
|
when "010" => dqm := "1111001111111111";
|
383 |
|
|
when "011" => dqm := "1111110011111111";
|
384 |
|
|
when "100" => dqm := "1111111100111111";
|
385 |
|
|
when "101" => dqm := "1111111111001111";
|
386 |
|
|
when "110" => dqm := "1111111111110011";
|
387 |
|
|
when others => dqm := "1111111111111100";
|
388 |
|
|
end case;
|
389 |
|
|
when others =>
|
390 |
|
|
dqm := "0000000000000000";
|
391 |
|
|
end case;
|
392 |
|
|
v.startsd := ra.startsd;
|
393 |
|
|
|
394 |
|
|
-- main FSM
|
395 |
|
|
|
396 |
|
|
case r.mstate is
|
397 |
|
|
when midle =>
|
398 |
|
|
if r.startsd = '1' then
|
399 |
|
|
if (r.sdstate = sidle) and (r.cfg.command = "000") and
|
400 |
|
|
(r.cmstate = midle)
|
401 |
|
|
then
|
402 |
|
|
startsd := '1'; v.mstate := active;
|
403 |
|
|
end if;
|
404 |
|
|
end if;
|
405 |
|
|
when others => null;
|
406 |
|
|
end case;
|
407 |
|
|
|
408 |
|
|
startsd := r.startsd xor r.startsdold;
|
409 |
|
|
|
410 |
|
|
-- generate row and column address size
|
411 |
|
|
|
412 |
|
|
haddr := ra.acc.haddr;
|
413 |
|
|
haddr(31 downto 20) := haddr(31 downto 20) and not conv_std_logic_vector(hmask, 12);
|
414 |
|
|
|
415 |
|
|
case r.cfg.csize is
|
416 |
|
|
when "00" => raddr := haddr(25 downto 12);
|
417 |
|
|
when "01" => raddr := haddr(26 downto 13);
|
418 |
|
|
when "10" => raddr := haddr(27 downto 14);
|
419 |
|
|
when others => raddr := haddr(28 downto 15);
|
420 |
|
|
end case;
|
421 |
|
|
|
422 |
|
|
-- generate bank address
|
423 |
|
|
|
424 |
|
|
ba := genmux(r.cfg.bsize, haddr(29 downto 22)) &
|
425 |
|
|
genmux(r.cfg.bsize, haddr(28 downto 21));
|
426 |
|
|
|
427 |
|
|
-- generate chip select
|
428 |
|
|
|
429 |
|
|
adec := genmux(r.cfg.bsize, haddr(30 downto 23));
|
430 |
|
|
|
431 |
|
|
rams := adec & not adec;
|
432 |
|
|
|
433 |
|
|
-- sdram access FSM
|
434 |
|
|
|
435 |
|
|
if r.trfc /= "0000" then v.trfc := r.trfc - 1; end if;
|
436 |
|
|
|
437 |
|
|
if r.idlecnt /= "0000" then v.idlecnt := r.idlecnt - 1; end if;
|
438 |
|
|
|
439 |
|
|
case r.sdstate is
|
440 |
|
|
when sidle =>
|
441 |
|
|
if (startsd = '1') and (r.cfg.command = "000") and (r.cmstate = midle)
|
442 |
|
|
and (r.istate = finish)
|
443 |
|
|
then
|
444 |
|
|
v.address := raddr; v.ba := ba;
|
445 |
|
|
if ra.acc.hio = '0' then
|
446 |
|
|
v.sdcsn := not rams(1 downto 0); v.rasn := '0'; v.sdstate := act1;
|
447 |
|
|
elsif ra.acc.haddr(4 downto 2) = "100" and r.cfg.mobileen(0) = '1' then v.sdstate := srr1;
|
448 |
|
|
else v.sdstate := ioreg1; end if;
|
449 |
|
|
elsif (r.cfg.command = "000") and (r.cmstate = midle)
|
450 |
|
|
and (r.istate = finish) and r.idlecnt = "0000" and (r.cfg.mobileen(1) = '1') then
|
451 |
|
|
case r.cfg.pmode is
|
452 |
|
|
when PM_SR => v.cfg.cke := '0'; v.sdstate := sref;
|
453 |
|
|
when PM_CKS => v.ck := (others => '0'); v.sdstate := cks;
|
454 |
|
|
when PM_PD => v.cfg.cke := '0'; v.sdstate := pd;
|
455 |
|
|
when PM_DPD => v.cfg.cke := '0'; v.sdstate := dpd;
|
456 |
|
|
when others =>
|
457 |
|
|
end case;
|
458 |
|
|
if r.cfg.pmode /= "000" then v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc; end if; -- Extend trfc for mobile ddr
|
459 |
|
|
end if;
|
460 |
|
|
v.waddr := ra.acc.haddr(7 downto 2);
|
461 |
|
|
when act1 =>
|
462 |
|
|
v.rasn := '1'; v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc; -- Extend trfc for mobile ddr
|
463 |
|
|
if r.cfg.trcd = '1' then v.sdstate := act2; else
|
464 |
|
|
v.sdstate := act3; v.hready := ra.acc.hwrite;
|
465 |
|
|
end if;
|
466 |
|
|
v.waddr := ra.acc.haddr(7 downto 2);
|
467 |
|
|
when act2 =>
|
468 |
|
|
v.sdstate := act3; v.hready := ra.acc.hwrite;
|
469 |
|
|
when act3 =>
|
470 |
|
|
v.casn := '0';
|
471 |
|
|
v.address := ra.acc.haddr(15 downto 13) & '0' & ra.acc.haddr(12 downto 4) & '0';
|
472 |
|
|
v.dqm := dqm;
|
473 |
|
|
if ra.acc.hwrite = '1' then
|
474 |
|
|
v.waddr := r.waddr + 4; v.waddr(1 downto 0) := "00";
|
475 |
|
|
v.sdstate := wr1; v.sdwen := '0'; v.bdrive := '0'; v.qdrive := '1';
|
476 |
|
|
if (r.waddr /= ra.raddr) then v.hready := '1';
|
477 |
|
|
if (r.waddr(5 downto 2) = ra.raddr(5 downto 2)) then
|
478 |
|
|
if r.waddr(1) = '1' then v.dqm(15 downto 8) := (others => '1');
|
479 |
|
|
else
|
480 |
|
|
case ra.raddr(1 downto 0) is
|
481 |
|
|
when "01" => v.dqm(7 downto 0) := (others => '1');
|
482 |
|
|
when "10" => v.dqm(3 downto 0) := (others => '1');
|
483 |
|
|
v.dqm(15 downto 12) := (others => r.waddr(0));
|
484 |
|
|
when others => v.dqm(15 downto 12) := (others => r.waddr(0));
|
485 |
|
|
end case;
|
486 |
|
|
end if;
|
487 |
|
|
else
|
488 |
|
|
case r.waddr(1 downto 0) is
|
489 |
|
|
when "01" => v.dqm(15 downto 12) := (others => '1');
|
490 |
|
|
when "10" => v.dqm(15 downto 8) := (others => '1');
|
491 |
|
|
when "11" => v.dqm(15 downto 4) := (others => '1');
|
492 |
|
|
when others => null;
|
493 |
|
|
end case;
|
494 |
|
|
end if;
|
495 |
|
|
else
|
496 |
|
|
case r.waddr(1 downto 0) is
|
497 |
|
|
when "00" => v.dqm(11 downto 0) := (others => '1');
|
498 |
|
|
when "01" => v.dqm(15 downto 12) := (others => '1'); v.dqm(7 downto 0) := (others => '1');
|
499 |
|
|
when "10" => v.dqm(15 downto 8) := (others => '1'); v.dqm(3 downto 0) := (others => '1');
|
500 |
|
|
when others => v.dqm(15 downto 4) := (others => '1');
|
501 |
|
|
end case;
|
502 |
|
|
end if;
|
503 |
|
|
else v.sdstate := rd1; end if;
|
504 |
|
|
when wr1 =>
|
505 |
|
|
v.sdwen := '1'; v.casn := '1'; v.qdrive := '1';
|
506 |
|
|
v.waddr := r.waddr + 4; v.dqm := (others => '0');
|
507 |
|
|
v.address(8 downto 3) := r.waddr;
|
508 |
|
|
if (r.waddr <= ra.raddr) and (r.waddr(5 downto 2) /= "0000") and (r.hready = '1')
|
509 |
|
|
then
|
510 |
|
|
v.hready := '1';
|
511 |
|
|
if (r.hready = '1') and (r.waddr(2 downto 0) = "000") then
|
512 |
|
|
v.sdwen := '0'; v.casn := '0';
|
513 |
|
|
end if;
|
514 |
|
|
if (r.waddr(5 downto 2) = ra.raddr(5 downto 2)) and (r.waddr /= "000000") then
|
515 |
|
|
case ra.raddr(1 downto 0) is
|
516 |
|
|
when "00" => v.dqm(11 downto 0) := (others => '1');
|
517 |
|
|
when "01" => v.dqm(7 downto 0) := (others => '1');
|
518 |
|
|
when "10" => v.dqm(3 downto 0) := (others => '1');
|
519 |
|
|
when others => null;
|
520 |
|
|
end case;
|
521 |
|
|
end if;
|
522 |
|
|
else
|
523 |
|
|
v.sdstate := wr2;
|
524 |
|
|
v.dqm := (others => '1'); --v.bdrive := '1';
|
525 |
|
|
v.startsdold := r.startsd;
|
526 |
|
|
end if;
|
527 |
|
|
when wr2 =>
|
528 |
|
|
v.sdstate := wr3; v.qdrive := '1';
|
529 |
|
|
when wr3 =>
|
530 |
|
|
v.sdstate := wr4a; v.qdrive := '1';
|
531 |
|
|
when wr4a =>
|
532 |
|
|
v.bdrive := '1';
|
533 |
|
|
v.rasn := '0'; v.sdwen := '0'; v.sdstate := wr4; v.qdrive := '1';
|
534 |
|
|
when wr4 =>
|
535 |
|
|
v.sdcsn := "11"; v.rasn := '1'; v.sdwen := '1'; v.qdrive := '0';
|
536 |
|
|
v.sdstate := wr5;
|
537 |
|
|
when wr5 =>
|
538 |
|
|
v.sdstate := sidle;
|
539 |
|
|
v.idlecnt := (others => '1');
|
540 |
|
|
when rd1 =>
|
541 |
|
|
v.casn := '1'; v.sdstate := rd7;
|
542 |
|
|
-- if ra.acc.haddr(4 downto 2) = "011" then
|
543 |
|
|
-- v.casn := '0'; v.burst := '1'; v.address(5 downto 3) := "100";
|
544 |
|
|
-- end if;
|
545 |
|
|
when rd7 =>
|
546 |
|
|
v.casn := '1'; v.sdstate := rd2;
|
547 |
|
|
-- if ra.acc.haddr(4 downto 2) = "010" then
|
548 |
|
|
-- v.casn := '0'; v.burst := '1'; v.address(5 downto 3) := "100";
|
549 |
|
|
-- end if;
|
550 |
|
|
when rd2 =>
|
551 |
|
|
--v.casn := '1'; v.sdstate := rd3;
|
552 |
|
|
v.casn := '1';
|
553 |
|
|
if regoutput = 1 then v.sdstate := rd2a; else v.sdstate := rd3; end if; -- delay if registered output
|
554 |
|
|
-- if ra.acc.haddr(4 downto 2) = "001" then
|
555 |
|
|
-- v.casn := '0'; v.burst := '1'; v.address(5 downto 3) := "100";
|
556 |
|
|
-- end if;
|
557 |
|
|
-- if v.sdwen = '0' then v.dqm := (others => '1'); end if;
|
558 |
|
|
when rd2a =>
|
559 |
|
|
v.sdstate := rd3;
|
560 |
|
|
when rd3 =>
|
561 |
|
|
if r.cfg.cl = '0' then -- CL = 2
|
562 |
|
|
if fast = 0 then v.startsdold := r.startsd; end if;
|
563 |
|
|
v.sdstate := rd4; v.hready := '1'; v.casn := '1';
|
564 |
|
|
else -- CL = 3
|
565 |
|
|
v.sdstate := rd3a; v.hready := '0'; v.casn := '1';
|
566 |
|
|
end if;
|
567 |
|
|
-- if r.sdwen = '0' then
|
568 |
|
|
-- v.rasn := '1'; v.sdwen := '1'; v.sdcsn := "11"; v.dqm := (others => '1');
|
569 |
|
|
-- elsif ra.acc.haddr(4 downto 2) = "000" then
|
570 |
|
|
-- v.casn := '0'; v.burst := '1'; v.address(5) := '1';
|
571 |
|
|
-- v.waddr := v.address(8 downto 3);
|
572 |
|
|
-- end if;
|
573 |
|
|
if v.hready = '1' then v.waddr := r.waddr + 4; end if;
|
574 |
|
|
when rd3a =>
|
575 |
|
|
if fast = 0 then v.startsdold := r.startsd; end if;
|
576 |
|
|
v.sdstate := rd4; v.hready := '1'; v.casn := '1';
|
577 |
|
|
if v.hready = '1' then v.waddr := r.waddr + 4; end if;
|
578 |
|
|
when rd4 =>
|
579 |
|
|
v.hready := '1'; v.casn := '1';
|
580 |
|
|
-- if (r.sdcsn /= "11") and (r.waddr(1 downto 0) = "11") and (r.burst = '1')
|
581 |
|
|
-- then
|
582 |
|
|
-- v.burst := '0';
|
583 |
|
|
if (r.sdcsn = "11") or (r.waddr(2 downto 2) = "1") then
|
584 |
|
|
v.dqm := (others => '1'); v.burst := '0';
|
585 |
|
|
if fast /= 0 then v.startsdold := r.startsd; end if;
|
586 |
|
|
if (r.sdcsn /= "11") then
|
587 |
|
|
v.rasn := '0'; v.sdwen := '0'; v.sdstate := rd5;
|
588 |
|
|
else
|
589 |
|
|
if r.cfg.trp = '1' then v.sdstate := rd6;
|
590 |
|
|
else v.sdstate := sidle; v.idlecnt := (others => '1'); end if;
|
591 |
|
|
end if;
|
592 |
|
|
end if;
|
593 |
|
|
if v.hready = '1' then v.waddr := r.waddr + 4; end if;
|
594 |
|
|
when rd5 =>
|
595 |
|
|
if r.cfg.trp = '1' then v.sdstate := rd6;
|
596 |
|
|
else v.sdstate := sidle; v.idlecnt := (others => '1'); end if;
|
597 |
|
|
v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1';
|
598 |
|
|
v.dqm := (others => '1');
|
599 |
|
|
when rd6 =>
|
600 |
|
|
v.sdstate := sidle; v.dqm := (others => '1');
|
601 |
|
|
v.idlecnt := (others => '1');
|
602 |
|
|
v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1';
|
603 |
|
|
when ioreg1 =>
|
604 |
|
|
v.hrdata(127 downto 32) := regsd1 & regsd2 & regsd3; v.sdstate := ioreg2;
|
605 |
|
|
if ra.acc.hwrite = '0' then v.hready := '1'; end if;
|
606 |
|
|
when ioreg2 =>
|
607 |
|
|
--writecfg := ra.acc.hwrite and not r.waddr(0); v.startsdold := r.startsd;
|
608 |
|
|
writecfg := ra.acc.hwrite; v.startsdold := r.startsd;
|
609 |
|
|
case r.cfg.pmode is
|
610 |
|
|
when PM_SR => v.cfg.cke := '0'; v.sdstate := sref;
|
611 |
|
|
when PM_CKS => v.ck := (others => '0'); v.sdstate := cks;
|
612 |
|
|
when PM_PD => v.cfg.cke := '0'; v.sdstate := pd;
|
613 |
|
|
when PM_DPD => v.cfg.cke := '0'; v.sdstate := dpd;
|
614 |
|
|
when others => v.sdstate := sidle; v.idlecnt := (others => '1');
|
615 |
|
|
end case;
|
616 |
|
|
if r.cfg.pmode /= "000" and r.cfg.cke = '1' then v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc; end if; -- Extend trfc for mobile ddr
|
617 |
|
|
when sref =>
|
618 |
|
|
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
|
619 |
|
|
if (startsd = '1' and (ra.acc.hio = '0' or ra.acc.haddr(4 downto 2) = "100"))
|
620 |
|
|
or (r.cfg.command /= "000") or r.cfg.pmode /= PM_SR then
|
621 |
|
|
if r.trfc = "0000" then v.cfg.cke := '1'; end if;
|
622 |
|
|
if r.cfg.cke = '1' then
|
623 |
|
|
v.sdcsn := (others => '0'); v.rasn := '1'; v.casn := '1';
|
624 |
|
|
if (r.idlecnt = "0000" and r.cfg.mobileen(0) = '1') -- 120 ns (tXSR) with NOP
|
625 |
|
|
or (r.refresh(8) = '0' and r.cfg.mobileen(0) = '0') then -- 200 clock cycles
|
626 |
|
|
v.sdstate := sidle;
|
627 |
|
|
v.idlecnt := (others => '1');
|
628 |
|
|
v.sref_tmpcom := r.cfg.command;
|
629 |
|
|
v.cfg.command := CMD_REF;
|
630 |
|
|
end if;
|
631 |
|
|
else
|
632 |
|
|
v.idlecnt := r.cfg.txsr;
|
633 |
|
|
end if;
|
634 |
|
|
elsif (startsd = '1' and ra.acc.hio = '1') then
|
635 |
|
|
v.waddr := ra.acc.haddr(7 downto 2);
|
636 |
|
|
v.sdstate := ioreg1;
|
637 |
|
|
end if;
|
638 |
|
|
when cks =>
|
639 |
|
|
if (startsd = '1' and (ra.acc.hio = '0' or ra.acc.haddr(4 downto 2) = "100"))
|
640 |
|
|
or (r.cfg.command /= "000") or r.cfg.pmode /= PM_CKS then
|
641 |
|
|
v.ck := (others => '1');
|
642 |
|
|
v.sdstate := sidle; v.idlecnt := (others => '1');
|
643 |
|
|
elsif (startsd = '1' and ra.acc.hio = '1') then
|
644 |
|
|
v.waddr := ra.acc.haddr(7 downto 2);
|
645 |
|
|
v.sdstate := ioreg1;
|
646 |
|
|
end if;
|
647 |
|
|
when pd =>
|
648 |
|
|
v.tcke := '1';
|
649 |
|
|
if ((startsd = '1' and (ra.acc.hio = '0' or ra.acc.haddr(4 downto 2) = "100"))
|
650 |
|
|
or (r.cfg.command /= "000") or r.cfg.pmode /= PM_PD)
|
651 |
|
|
and (r.tcke = '1' or r.cfg.tcke = '0') then
|
652 |
|
|
v.cfg.cke := '1';
|
653 |
|
|
v.txp := r.cfg.cke;
|
654 |
|
|
if r.cfg.cke = '1' and (r.txp = '1' or r.cfg.txp = '0') then -- 1 - 2 clock cycles
|
655 |
|
|
v.sdstate := sidle;
|
656 |
|
|
v.idlecnt := (others => '1');
|
657 |
|
|
end if;
|
658 |
|
|
elsif startsd = '1' and ra.acc.hio = '1' and (r.tcke = '1' or r.cfg.tcke = '0') then
|
659 |
|
|
v.waddr := ra.acc.haddr(7 downto 2);
|
660 |
|
|
v.sdstate := ioreg1;
|
661 |
|
|
end if;
|
662 |
|
|
when dpd =>
|
663 |
|
|
v.sdcsn := (others => '0'); v.sdwen := '0'; v.rasn := '1'; v.casn := '1';
|
664 |
|
|
v.cfg.refon := '0';
|
665 |
|
|
if (startsd = '1' and ra.acc.hio = '1') then
|
666 |
|
|
v.waddr := ra.acc.haddr(7 downto 2);
|
667 |
|
|
v.sdstate := ioreg1;
|
668 |
|
|
elsif startsd = '1' then
|
669 |
|
|
v.startsdold := r.startsd; -- acc all accesses
|
670 |
|
|
elsif r.cfg.pmode /= PM_DPD then
|
671 |
|
|
v.cfg.cke := '1';
|
672 |
|
|
if r.cfg.cke = '1' then
|
673 |
|
|
v.sdcsn := (others => '0'); v.sdwen := '1'; v.rasn := '1'; v.casn := '1';
|
674 |
|
|
v.sdstate := sidle;
|
675 |
|
|
v.idlecnt := (others => '1');
|
676 |
|
|
end if;
|
677 |
|
|
end if;
|
678 |
|
|
when srr1 => -- Load Mode Register "01"
|
679 |
|
|
v.trfc := "0001";
|
680 |
|
|
v.sdcsn := (0 => '0', others => '1'); v.rasn := '0'; v.casn := '0';
|
681 |
|
|
v.sdwen := '0'; v.address := (others => '0'); v.ba := "01";
|
682 |
|
|
v.sdstate := srr2;
|
683 |
|
|
when srr2 => -- Read 0
|
684 |
|
|
v.sdcsn := (others => '1'); v.rasn := '1'; v.casn := '1'; v.sdwen := '1';
|
685 |
|
|
if r.trfc = "0000" then
|
686 |
|
|
-- if r.cfg.cl = '1' then v.trfc := "0100"; else v.trfc := "0011"; end if;
|
687 |
|
|
if regoutput = 1 then -- delay if registered output
|
688 |
|
|
if r.cfg.cl = '1' then v.trfc := "0101"; else v.trfc := "0100"; end if; -- Extend trfc for mobile ddr
|
689 |
|
|
else
|
690 |
|
|
if r.cfg.cl = '1' then v.trfc := "0100"; else v.trfc := "0011"; end if; -- Extend trfc for mobile ddr
|
691 |
|
|
end if;
|
692 |
|
|
v.sdcsn := (0 => '0', others => '1'); v.casn := '0';
|
693 |
|
|
v.sdstate := srr3;
|
694 |
|
|
end if;
|
695 |
|
|
when srr3 => -- SRR done
|
696 |
|
|
v.sdcsn := (others => '1'); v.rasn := '1'; v.casn := '1'; v.sdwen := '1';
|
697 |
|
|
if r.trfc = "0000" then
|
698 |
|
|
v.hready := '1';
|
699 |
|
|
v.startsdold := r.startsd;
|
700 |
|
|
v.sdstate := sidle;
|
701 |
|
|
v.idlecnt := (others => '1');
|
702 |
|
|
end if;
|
703 |
|
|
when others =>
|
704 |
|
|
v.sdstate := sidle;
|
705 |
|
|
v.idlecnt := (others => '1');
|
706 |
|
|
end case;
|
707 |
|
|
|
708 |
|
|
-- sdram commands
|
709 |
|
|
|
710 |
|
|
case r.cmstate is
|
711 |
|
|
when midle =>
|
712 |
|
|
if r.sdstate = sidle then
|
713 |
|
|
case r.cfg.command is
|
714 |
|
|
when CMD_PRE => -- precharge
|
715 |
|
|
v.sdcsn := (others => '0'); v.rasn := '0'; v.sdwen := '0';
|
716 |
|
|
v.address(12) := '1'; v.cmstate := active;
|
717 |
|
|
when CMD_REF => -- auto-refresh
|
718 |
|
|
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
|
719 |
|
|
v.cmstate := active;
|
720 |
|
|
when CMD_EMR => -- load-ext-mode-reg
|
721 |
|
|
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
|
722 |
|
|
v.sdwen := '0'; v.cmstate := active; v.ba := "01";
|
723 |
|
|
--v.address := "00000000000000";
|
724 |
|
|
if r.cfg.mobileen = "11" then
|
725 |
|
|
v.ba := "10";
|
726 |
|
|
v.address := "000000" & r.cfg.ds(2 downto 0) & r.cfg.tcsr(1 downto 0)
|
727 |
|
|
& r.cfg.pasr(2 downto 0);
|
728 |
|
|
else
|
729 |
|
|
v.ba := "01";
|
730 |
|
|
v.address := "00000000000000";
|
731 |
|
|
end if;
|
732 |
|
|
when CMD_LMR => -- load-mode-reg
|
733 |
|
|
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
|
734 |
|
|
v.sdwen := '0'; v.cmstate := active; v.ba := "00";
|
735 |
|
|
-- v.address := "00000" & r.cfg.dllrst & "0" & "01" & r.cfg.trcd & "0011";
|
736 |
|
|
v.address := "00000" & r.cfg.dllrst & "0" & "01" & r.cfg.cl & "0010";
|
737 |
|
|
when others => null;
|
738 |
|
|
end case;
|
739 |
|
|
end if;
|
740 |
|
|
when active =>
|
741 |
|
|
v.sdcsn := (others => '1'); v.rasn := '1'; v.casn := '1';
|
742 |
|
|
v.sdwen := '1'; --v.cfg.command := "000";
|
743 |
|
|
v.cfg.command := r.sref_tmpcom; v.sref_tmpcom := "000";
|
744 |
|
|
v.cmstate := leadout; v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc; -- Extend trfc for mobile ddr
|
745 |
|
|
when others =>
|
746 |
|
|
if r.trfc = "0000" then v.cmstate := midle; end if;
|
747 |
|
|
|
748 |
|
|
end case;
|
749 |
|
|
|
750 |
|
|
-- sdram init
|
751 |
|
|
|
752 |
|
|
case r.istate is
|
753 |
|
|
when iidle =>
|
754 |
|
|
if r.cfg.renable = '1' then
|
755 |
|
|
v.cfg.cke := '1'; v.cfg.dllrst := '1';
|
756 |
|
|
if r.cfg.cke = '1' then v.istate := pre; v.cfg.command := CMD_PRE; end if; v.ba := "00";
|
757 |
|
|
end if;
|
758 |
|
|
when pre =>
|
759 |
|
|
if r.cfg.command = "000" then
|
760 |
|
|
if r.cfg.mobileen = "11" then
|
761 |
|
|
v.cfg.command := CMD_REF; v.istate := ref1;
|
762 |
|
|
else
|
763 |
|
|
v.cfg.command := "11" & r.cfg.dllrst; -- CMD_LMR/CMD_EMR
|
764 |
|
|
if r.cfg.dllrst = '1' then v.istate := emode; else v.istate := lmode; end if;
|
765 |
|
|
end if;
|
766 |
|
|
end if;
|
767 |
|
|
when emode =>
|
768 |
|
|
if r.cfg.command = "000" then
|
769 |
|
|
if r.cfg.mobileen = "11" then
|
770 |
|
|
v.istate := finish; --v.cfg.command := CMD_LMR;
|
771 |
|
|
v.cfg.refon := '1'; v.cfg.renable := '0';
|
772 |
|
|
else
|
773 |
|
|
v.istate := lmode; v.cfg.command := CMD_LMR;
|
774 |
|
|
end if;
|
775 |
|
|
end if;
|
776 |
|
|
when lmode =>
|
777 |
|
|
if r.cfg.command = "000" then
|
778 |
|
|
if r.cfg.mobileen = "11" then
|
779 |
|
|
v.cfg.command := CMD_EMR; v.istate := emode;
|
780 |
|
|
else
|
781 |
|
|
if r.cfg.dllrst = '1' then
|
782 |
|
|
if r.refresh(9 downto 8) = "00" then -- > 200 clocks delay
|
783 |
|
|
v.cfg.command := CMD_PRE; v.istate := ref1;
|
784 |
|
|
end if;
|
785 |
|
|
else
|
786 |
|
|
v.istate := finish; --v.cfg.command := CMD_LMR;
|
787 |
|
|
v.cfg.refon := '1'; v.cfg.renable := '0';
|
788 |
|
|
end if;
|
789 |
|
|
end if;
|
790 |
|
|
end if;
|
791 |
|
|
when ref1 =>
|
792 |
|
|
if r.cfg.command = "000" then
|
793 |
|
|
v.cfg.command := CMD_REF; v.cfg.dllrst := '0'; v.istate := ref2;
|
794 |
|
|
end if;
|
795 |
|
|
when ref2 =>
|
796 |
|
|
if r.cfg.command = "000" then
|
797 |
|
|
--v.cfg.command := CMD_REF; v.istate := pre;
|
798 |
|
|
if r.cfg.mobileen = "11" then v.istate := lmode; v.cfg.command := CMD_LMR;
|
799 |
|
|
else v.cfg.command := CMD_REF; v.istate := pre; end if;
|
800 |
|
|
end if;
|
801 |
|
|
when others =>
|
802 |
|
|
--if r.cfg.renable = '1' then
|
803 |
|
|
if r.cfg.renable = '1' and r.sdstate /= dpd then
|
804 |
|
|
v.istate := iidle; v.cfg.dllrst := '1';
|
805 |
|
|
end if;
|
806 |
|
|
end case;
|
807 |
|
|
|
808 |
|
|
-- second part of main fsm
|
809 |
|
|
|
810 |
|
|
case r.mstate is
|
811 |
|
|
when active =>
|
812 |
|
|
if v.hready = '1' then
|
813 |
|
|
v.mstate := midle;
|
814 |
|
|
end if;
|
815 |
|
|
when others => null;
|
816 |
|
|
end case;
|
817 |
|
|
|
818 |
|
|
-- sdram refresh counter
|
819 |
|
|
|
820 |
|
|
if (((r.cfg.refon = '1') and (r.istate = finish)) or
|
821 |
|
|
(r.cfg.dllrst = '1')) and (r.cfg.pmode /= PM_SR or r.cfg.mobileen(0) = '0')
|
822 |
|
|
then
|
823 |
|
|
v.refresh := r.refresh - 1;
|
824 |
|
|
if r.cfg.pmode = PM_SR and r.cfg.mobileen(0) = '0' and r.cfg.cke = '0' then
|
825 |
|
|
v.refresh := (8 => '1', 7 => '1', 6 => '1', 3 => '1', others => '0');
|
826 |
|
|
else
|
827 |
|
|
if (v.refresh(11) and not r.refresh(11)) = '1' then
|
828 |
|
|
v.refresh := r.cfg.refresh;
|
829 |
|
|
if r.cfg.dllrst = '0' then v.cfg.command := "100"; arefresh := '1'; end if;
|
830 |
|
|
end if;
|
831 |
|
|
end if;
|
832 |
|
|
end if;
|
833 |
|
|
|
834 |
|
|
-- AHB register access
|
835 |
|
|
|
836 |
|
|
if (ra.acc.hio and ra.acc.hwrite and writecfg) = '1' then
|
837 |
|
|
if r.waddr(2 downto 0) = "000" then
|
838 |
|
|
v.cfg.refresh := wdata(11+96 downto 0+96);
|
839 |
|
|
v.cfg.dllrst := wdata(17+96);
|
840 |
|
|
v.cfg.command := wdata(20+96 downto 18+96);
|
841 |
|
|
v.cfg.csize := wdata(22+96 downto 21+96);
|
842 |
|
|
v.cfg.bsize := wdata(25+96 downto 23+96);
|
843 |
|
|
v.cfg.trcd := wdata(26+96);
|
844 |
|
|
v.cfg.trfc := wdata(29+96 downto 27+96);
|
845 |
|
|
v.cfg.trp := wdata(30+96);
|
846 |
|
|
if r.cfg.pmode = "000" then
|
847 |
|
|
v.cfg.cke := wdata(15+96);
|
848 |
|
|
v.cfg.renable := wdata(16+96);
|
849 |
|
|
v.cfg.refon := wdata(31+96);
|
850 |
|
|
end if;
|
851 |
|
|
elsif r.waddr(2 downto 0) = "010" then
|
852 |
|
|
v.cfg.cl := wdata(30+32);
|
853 |
|
|
if r.cfg.mobileen(1) = '1' and mobile /= 3 then
|
854 |
|
|
v.cfg.mobileen(0) := wdata(31+32);
|
855 |
|
|
end if;
|
856 |
|
|
if r.cfg.mobileen(1) = '1' then
|
857 |
|
|
v.cfg.pasr(5 downto 3) := wdata( 2+32 downto 0+32);
|
858 |
|
|
v.cfg.tcsr(3 downto 2) := wdata( 4+32 downto 3+32);
|
859 |
|
|
v.cfg.ds(5 downto 3) := wdata( 7+32 downto 5+32);
|
860 |
|
|
v.cfg.pmode := wdata(18+32 downto 16+32);
|
861 |
|
|
v.cfg.txp := wdata(19+32);
|
862 |
|
|
v.cfg.txsr := wdata(23+32 downto 20+32);
|
863 |
|
|
v.cfg.tcke := wdata(24+32);
|
864 |
|
|
end if;
|
865 |
|
|
elsif r.waddr(2 downto 0) = "101" and confapi /= 0 then
|
866 |
|
|
v.cfg.conf(31 downto 0) := wdata(31+64 downto 0+64);
|
867 |
|
|
elsif r.waddr(2 downto 0) = "110" and confapi /= 0 then
|
868 |
|
|
v.cfg.conf(63 downto 32) := wdata(31+32 downto 0+32);
|
869 |
|
|
end if;
|
870 |
|
|
end if;
|
871 |
|
|
|
872 |
|
|
-- Disable CS and DPD when Mobile DDR is Disabled
|
873 |
|
|
if r.cfg.mobileen(0) = '0' then v.cfg.pmode(2) := '0'; end if;
|
874 |
|
|
|
875 |
|
|
-- Update EMR when ds, tcsr or pasr change
|
876 |
|
|
if r.cfg.command = "000" and arefresh = '0' and r.cfg.mobileen(0) = '1' then
|
877 |
|
|
if r.cfg.ds(2 downto 0) /= r.cfg.ds(5 downto 3) then
|
878 |
|
|
v.cfg.command := "111"; v.cfg.ds(2 downto 0) := r.cfg.ds(5 downto 3);
|
879 |
|
|
end if;
|
880 |
|
|
if r.cfg.tcsr(1 downto 0) /= r.cfg.tcsr(3 downto 2) then
|
881 |
|
|
v.cfg.command := "111"; v.cfg.tcsr(1 downto 0) := r.cfg.tcsr(3 downto 2);
|
882 |
|
|
end if;
|
883 |
|
|
if r.cfg.pasr(2 downto 0) /= r.cfg.pasr(5 downto 3) then
|
884 |
|
|
v.cfg.command := "111"; v.cfg.pasr(2 downto 0) := r.cfg.pasr(5 downto 3);
|
885 |
|
|
end if;
|
886 |
|
|
end if;
|
887 |
|
|
|
888 |
|
|
v.nbdrive := not v.bdrive;
|
889 |
|
|
|
890 |
|
|
if oepol = 1 then bdrive := r.nbdrive; vbdrive := (others => v.nbdrive);
|
891 |
|
|
else bdrive := r.bdrive; vbdrive := (others => v.bdrive);end if;
|
892 |
|
|
|
893 |
|
|
-- reset
|
894 |
|
|
|
895 |
|
|
if ddr_rst = '0' then
|
896 |
|
|
v.sdstate := sidle;
|
897 |
|
|
v.mstate := midle;
|
898 |
|
|
v.istate := finish;
|
899 |
|
|
v.cmstate := midle;
|
900 |
|
|
v.cfg.command := "000";
|
901 |
|
|
v.cfg.csize := conv_std_logic_vector(col-9, 2);
|
902 |
|
|
v.cfg.bsize := conv_std_logic_vector(log2(Mbyte/8), 3);
|
903 |
|
|
if MHz > 100 then v.cfg.trcd := '1'; else v.cfg.trcd := '0'; end if;
|
904 |
|
|
v.cfg.refon := '0';
|
905 |
|
|
if mobile >= 2 then -- Extend trfc for mobile ddr
|
906 |
|
|
if MHz > 100 then v.cfg.trfc := conv_std_logic_vector(98*MHz/1000-10, 3);
|
907 |
|
|
else v.cfg.trfc := conv_std_logic_vector(98*MHz/1000-2, 3); end if;
|
908 |
|
|
else v.cfg.trfc := conv_std_logic_vector(75*MHz/1000-2, 3); end if;
|
909 |
|
|
v.cfg.refresh := conv_std_logic_vector(7800*MHz/1000, 12);
|
910 |
|
|
v.refresh := (others => '0');
|
911 |
|
|
if pwron = 1 then v.cfg.renable := '1';
|
912 |
|
|
else v.cfg.renable := '0'; end if;
|
913 |
|
|
if MHz > 100 then v.cfg.trp := '1'; else v.cfg.trp := '0'; end if;
|
914 |
|
|
v.dqm := (others => '1');
|
915 |
|
|
v.sdwen := '1';
|
916 |
|
|
v.rasn := '1';
|
917 |
|
|
v.casn := '1';
|
918 |
|
|
v.hready := '0';
|
919 |
|
|
v.startsd := '0';
|
920 |
|
|
v.startsdold := '0';
|
921 |
|
|
v.cfg.dllrst := '0';
|
922 |
|
|
if mobile >= 2 then v.cfg.cke := '1';
|
923 |
|
|
else v.cfg.cke := '0'; end if;
|
924 |
|
|
v.cfg.pasr := (others => '0');
|
925 |
|
|
v.cfg.tcsr := (others => '0');
|
926 |
|
|
v.cfg.ds := (others => '0');
|
927 |
|
|
v.cfg.pmode := (others => '0');
|
928 |
|
|
v.cfg.txsr := conv_std_logic_vector(120*MHz/1000, 4);
|
929 |
|
|
v.cfg.txp := '1';
|
930 |
|
|
v.idlecnt := (others => '1');
|
931 |
|
|
v.ck := (others => '1');
|
932 |
|
|
if mobile >= 2 then v.cfg.mobileen := "11"; -- Default: Mobile DDR
|
933 |
|
|
elsif mobile = 1 then v.cfg.mobileen := "10"; -- Mobile DDR support enable
|
934 |
|
|
else v.cfg.mobileen := "00"; end if; -- Mobile DDR support disable
|
935 |
|
|
v.sref_tmpcom := "000";
|
936 |
|
|
v.cfg.cl := '0'; -- CL = 3/2 -- ****
|
937 |
|
|
v.cfg.tcke := '1';
|
938 |
|
|
if confapi /= 0 then
|
939 |
|
|
v.cfg.conf(31 downto 0) := conv_std_logic_vector(conf0, 32); --x"0000A0A0";
|
940 |
|
|
v.cfg.conf(63 downto 32) := conv_std_logic_vector(conf1, 32); --x"00060606";
|
941 |
|
|
end if;
|
942 |
|
|
end if;
|
943 |
|
|
|
944 |
|
|
if regoutput = 1 then
|
945 |
|
|
if oepol = 1 then v.sdo_bdrive := r.nbdrive; -- *** ??? delay ctrl
|
946 |
|
|
else v.sdo_bdrive := r.bdrive; end if;
|
947 |
|
|
v.sdo_qdrive := not (v.qdrive or r.nbdrive);
|
948 |
|
|
end if;
|
949 |
|
|
|
950 |
|
|
ri <= v;
|
951 |
|
|
ribdrive <= vbdrive;
|
952 |
|
|
|
953 |
|
|
|
954 |
|
|
end process;
|
955 |
|
|
|
956 |
|
|
--sdo.sdcke <= (others => r.cfg.cke);
|
957 |
|
|
ahbso.hconfig <= hconfig;
|
958 |
|
|
ahbso.hirq <= (others => '0');
|
959 |
|
|
ahbso.hindex <= hindex;
|
960 |
|
|
|
961 |
|
|
ahbregs : process(clk_ahb) begin
|
962 |
|
|
if rising_edge(clk_ahb) then
|
963 |
|
|
ra <= rai;
|
964 |
|
|
end if;
|
965 |
|
|
end process;
|
966 |
|
|
|
967 |
|
|
ddrregs : process(clk_ddr, rst, ddr_rst) begin
|
968 |
|
|
if rising_edge(clk_ddr) then
|
969 |
|
|
r <= ri; rbdrive <= ribdrive;
|
970 |
|
|
ddr_rst_gen <= ddr_rst_gen(2 downto 0) & '1';
|
971 |
|
|
end if;
|
972 |
|
|
if (rst = '0') then
|
973 |
|
|
ddr_rst_gen <= "0000";
|
974 |
|
|
end if;
|
975 |
|
|
if (ddr_rst = '0') then
|
976 |
|
|
r.sdcsn <= (others => '1'); r.bdrive <= '1'; r.nbdrive <= '0';
|
977 |
|
|
if oepol = 0 then rbdrive <= (others => '1');
|
978 |
|
|
else rbdrive <= (others => '0'); end if;
|
979 |
|
|
--r.cfg.cke <= '0';
|
980 |
|
|
if mobile = 2 then r.cfg.cke <= '1';
|
981 |
|
|
else r.cfg.cke <= '0'; end if;
|
982 |
|
|
end if;
|
983 |
|
|
end process;
|
984 |
|
|
|
985 |
|
|
--sdo.address <= '0' & ri.address;
|
986 |
|
|
--sdo.ba <= ri.ba;
|
987 |
|
|
--sdo.bdrive <= r.nbdrive when oepol = 1 else r.bdrive;
|
988 |
|
|
--sdo.qdrive <= not (ri.qdrive or r.nbdrive);
|
989 |
|
|
--sdo.vbdrive <= rbdrive;
|
990 |
|
|
--sdo.sdcsn <= ri.sdcsn;
|
991 |
|
|
--sdo.sdwen <= ri.sdwen;
|
992 |
|
|
--sdo.dqm <= r.dqm;
|
993 |
|
|
--sdo.rasn <= ri.rasn;
|
994 |
|
|
--sdo.casn <= ri.casn;
|
995 |
|
|
--sdo.data <= wdata;
|
996 |
|
|
--sdo.sdck <= r.ck;
|
997 |
|
|
|
998 |
|
|
sdo.address <= '0' & r.address when regoutput = 1 else '0' & ri.address; -- *** ??? delay ctrl
|
999 |
|
|
sdo.ba <= r.ba when regoutput = 1 else ri.ba; -- *** ??? delay ctrl
|
1000 |
|
|
sdo.bdrive <= r.sdo_bdrive when regoutput = 1 else r.nbdrive when oepol = 1 else r.bdrive; -- *** ??? delay ctrl
|
1001 |
|
|
sdo.qdrive <= r.sdo_qdrive when regoutput = 1 else not (ri.qdrive or r.nbdrive); -- *** ??? delay ctrl
|
1002 |
|
|
sdo.vbdrive <= rbdrive;
|
1003 |
|
|
sdo.sdcsn <= r.sdcsn when regoutput = 1 else ri.sdcsn; -- *** ??? delay ctrl
|
1004 |
|
|
sdo.sdwen <= r.sdwen when regoutput = 1 else ri.sdwen; -- *** ??? delay ctrl
|
1005 |
|
|
sdo.dqm <= r.dqm_dly when regoutput = 1 else r.dqm; -- *** ??? delay ctrl
|
1006 |
|
|
sdo.rasn <= r.rasn when regoutput = 1 else ri.rasn; -- *** ??? delay ctrl
|
1007 |
|
|
sdo.casn <= r.casn when regoutput = 1 else ri.casn; -- *** ??? delay ctrl
|
1008 |
|
|
sdo.data <= r.wdata when regoutput = 1 else wdata; -- *** ??? delay ctrl
|
1009 |
|
|
sdo.sdck <= r.ck_dly when regoutput = 1 else r.ck; -- *** ??? delay ctrl
|
1010 |
|
|
sdo.sdcke <= (others => r.cke_dly) when regoutput = 1 else (others => r.cfg.cke); -- *** ??? delay ctrl
|
1011 |
|
|
sdo.moben <= r.cfg.mobileen(0);
|
1012 |
|
|
sdo.conf <= r.cfg.conf;
|
1013 |
|
|
|
1014 |
|
|
read_buff : syncram_2p
|
1015 |
|
|
generic map (tech => memtech, abits => 4, dbits => 128, sepclk => 1, wrfst => 0)
|
1016 |
|
|
port map ( rclk => clk_ahb, renable => vcc, raddress => rai.raddr(5 downto 2),
|
1017 |
|
|
dataout => rdata, wclk => clk_ddr, write => ri.hready,
|
1018 |
|
|
waddress => r.waddr(5 downto 2), datain => ri.hrdata);
|
1019 |
|
|
|
1020 |
|
|
write_buff1 : syncram_2p
|
1021 |
|
|
generic map (tech => memtech, abits => 4, dbits => 32, sepclk => 1, wrfst => 0)
|
1022 |
|
|
port map ( rclk => clk_ddr, renable => vcc, raddress => r.waddr(5 downto 2),
|
1023 |
|
|
dataout => wdata(127 downto 96), wclk => clk_ahb, write => ra.write(0),
|
1024 |
|
|
waddress => ra.haddr(7 downto 4), datain => ahbsi.hwdata);
|
1025 |
|
|
|
1026 |
|
|
write_buff2 : syncram_2p
|
1027 |
|
|
generic map (tech => memtech, abits => 4, dbits => 32, sepclk => 1, wrfst => 0)
|
1028 |
|
|
port map ( rclk => clk_ddr, renable => vcc, raddress => r.waddr(5 downto 2),
|
1029 |
|
|
dataout => wdata(95 downto 64), wclk => clk_ahb, write => ra.write(1),
|
1030 |
|
|
waddress => ra.haddr(7 downto 4), datain => ahbsi.hwdata);
|
1031 |
|
|
|
1032 |
|
|
write_buff3 : syncram_2p
|
1033 |
|
|
generic map (tech => memtech, abits => 4, dbits => 32, sepclk => 1, wrfst => 0)
|
1034 |
|
|
port map ( rclk => clk_ddr, renable => vcc, raddress => r.waddr(5 downto 2),
|
1035 |
|
|
dataout => wdata(63 downto 32), wclk => clk_ahb, write => ra.write(2),
|
1036 |
|
|
waddress => ra.haddr(7 downto 4), datain => ahbsi.hwdata);
|
1037 |
|
|
|
1038 |
|
|
write_buff4 : syncram_2p
|
1039 |
|
|
generic map (tech => memtech, abits => 4, dbits => 32, sepclk => 1, wrfst => 0)
|
1040 |
|
|
port map ( rclk => clk_ddr, renable => vcc, raddress => r.waddr(5 downto 2),
|
1041 |
|
|
dataout => wdata(31 downto 0), wclk => clk_ahb, write => ra.write(3),
|
1042 |
|
|
waddress => ra.haddr(7 downto 4), datain => ahbsi.hwdata);
|
1043 |
|
|
|
1044 |
|
|
-- pragma translate_off
|
1045 |
|
|
bootmsg : report_version
|
1046 |
|
|
generic map (
|
1047 |
|
|
msg1 => "ddrsp" & tost(hindex) & ": 64-bit DDR266 controller rev " &
|
1048 |
|
|
tost(REVISION) & ", " & tost(Mbyte) & " Mbyte, " & tost(MHz) &
|
1049 |
|
|
" MHz DDR clock");
|
1050 |
|
|
-- pragma translate_on
|
1051 |
|
|
|
1052 |
|
|
end;
|
1053 |
|
|
|