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dimamali |
------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003, Gaisler Research
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-----------------------------------------------------------------------------
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-- Entity: sdctrl
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-- File: sdctrl.vhd
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-- Author: Jiri Gaisler - Gaisler Research
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-- Description: 32-bit SDRAM memory controller.
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library grlib;
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use grlib.amba.all;
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use grlib.stdlib.all;
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library gaisler;
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use grlib.devices.all;
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use gaisler.memctrl.all;
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entity sdctrl is
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generic (
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hindex : integer := 0;
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haddr : integer := 0;
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hmask : integer := 16#f00#;
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ioaddr : integer := 16#000#;
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iomask : integer := 16#fff#;
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wprot : integer := 0;
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invclk : integer := 0;
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fast : integer := 0;
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pwron : integer := 0;
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sdbits : integer := 32;
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oepol : integer := 0;
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pageburst : integer := 0;
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mobile : integer := 0
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);
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port (
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rst : in std_ulogic;
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clk : in std_ulogic;
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ahbsi : in ahb_slv_in_type;
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ahbso : out ahb_slv_out_type;
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sdi : in sdctrl_in_type;
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sdo : out sdctrl_out_type
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);
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end;
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architecture rtl of sdctrl is
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constant WPROTEN : boolean := wprot = 1;
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constant SDINVCLK : boolean := invclk = 1;
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constant BUS64 : boolean := (sdbits = 64);
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constant REVISION : integer := 1;
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constant PM_PD : std_logic_vector(2 downto 0) := "001";
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constant PM_SR : std_logic_vector(2 downto 0) := "010";
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constant PM_DPD : std_logic_vector(2 downto 0) := "101";
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constant std_rammask: Std_Logic_Vector(31 downto 20) :=
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Conv_Std_Logic_Vector(hmask, 12);
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constant hconfig : ahb_config_type := (
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4 => ahb_membar(haddr, '1', '1', hmask),
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5 => ahb_iobar(ioaddr, iomask),
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others => zero32);
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type mcycletype is (midle, active, leadout);
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type sdcycletype is (act1, act2, act3, rd1, rd2, rd3, rd4, rd5, rd6, rd7, rd8,
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wr1, wr2, wr3, wr4, wr5, sidle,
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sref, pd, dpd);
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type icycletype is (iidle, pre, ref, lmode, emode, finish);
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-- sdram configuration register
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type sdram_cfg_type is record
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command : std_logic_vector(2 downto 0);
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csize : std_logic_vector(1 downto 0);
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bsize : std_logic_vector(2 downto 0);
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casdel : std_ulogic; -- CAS to data delay: 2/3 clock cycles
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trfc : std_logic_vector(2 downto 0);
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trp : std_ulogic; -- precharge to activate: 2/3 clock cycles
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refresh : std_logic_vector(14 downto 0);
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renable : std_ulogic;
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pageburst : std_ulogic;
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mobileen : std_logic_vector(1 downto 0); -- Mobile SD support, Mobile SD enabled
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ds : std_logic_vector(3 downto 0); -- ds(1:0) (ds(3:2) used to detect update)
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tcsr : std_logic_vector(3 downto 0); -- tcrs(1:0) (tcrs(3:2) used to detect update)
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pasr : std_logic_vector(5 downto 0); -- pasr(2:0) (pasr(5:3) used to detect update)
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pmode : std_logic_vector(2 downto 0); -- Power-Saving mode
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txsr : std_logic_vector(3 downto 0); -- Exit Self Refresh timing
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cke : std_ulogic; -- Clock enable
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end record;
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-- local registers
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type reg_type is record
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hready : std_ulogic;
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hsel : std_ulogic;
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bdrive : std_ulogic;
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nbdrive : std_ulogic;
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burst : std_ulogic;
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wprothit : std_ulogic;
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hio : std_ulogic;
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startsd : std_ulogic;
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mstate : mcycletype;
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sdstate : sdcycletype;
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cmstate : mcycletype;
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istate : icycletype;
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icnt : std_logic_vector(2 downto 0);
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haddr : std_logic_vector(31 downto 0);
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hrdata : std_logic_vector(sdbits-1 downto 0);
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hwdata : std_logic_vector(31 downto 0);
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hwrite : std_ulogic;
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htrans : std_logic_vector(1 downto 0);
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hresp : std_logic_vector(1 downto 0);
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size : std_logic_vector(1 downto 0);
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cfg : sdram_cfg_type;
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trfc : std_logic_vector(3 downto 0);
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refresh : std_logic_vector(14 downto 0);
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sdcsn : std_logic_vector(1 downto 0);
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sdwen : std_ulogic;
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rasn : std_ulogic;
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casn : std_ulogic;
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dqm : std_logic_vector(7 downto 0);
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address : std_logic_vector(16 downto 2); -- memory address
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bsel : std_ulogic;
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idlecnt : std_logic_vector(3 downto 0); -- Counter, 16 idle clock sycles before entering Power-Saving mode
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sref_tmpcom : std_logic_vector(2 downto 0); -- Save SD command when exit sref
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end record;
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signal r, ri : reg_type;
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signal rbdrive, ribdrive : std_logic_vector(31 downto 0);
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attribute syn_preserve : boolean;
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attribute syn_preserve of rbdrive : signal is true;
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begin
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ctrl : process(rst, ahbsi, r, sdi, rbdrive)
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variable v : reg_type; -- local variables for registers
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variable startsd : std_ulogic;
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variable dataout : std_logic_vector(31 downto 0); -- data from memory
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variable regsd : std_logic_vector(31 downto 0); -- data from registers
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variable dqm : std_logic_vector(7 downto 0);
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variable raddr : std_logic_vector(12 downto 0);
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variable adec : std_ulogic;
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variable rams : std_logic_vector(1 downto 0);
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variable ba : std_logic_vector(1 downto 0);
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variable haddr : std_logic_vector(31 downto 0);
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variable dout : std_logic_vector(31 downto 0);
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variable hsize : std_logic_vector(1 downto 0);
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variable hwrite : std_ulogic;
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variable htrans : std_logic_vector(1 downto 0);
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variable hready : std_ulogic;
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variable vbdrive : std_logic_vector(31 downto 0);
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variable bdrive : std_ulogic;
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variable lline : std_logic_vector(2 downto 0);
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variable lineburst : boolean;
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variable haddr_tmp : std_logic_vector(31 downto 0);
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variable arefresh : std_logic;
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begin
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-- Variable default settings to avoid latches
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v := r; startsd := '0'; v.hresp := HRESP_OKAY; vbdrive := rbdrive; arefresh := '0';
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v.hrdata(sdbits-1 downto sdbits-32) := sdi.data(sdbits-1 downto sdbits-32);
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v.hrdata(31 downto 0) := sdi.data(31 downto 0);
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v.hwdata := ahbsi.hwdata;
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lline := not r.cfg.casdel & r.cfg.casdel & r.cfg.casdel;
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if (pageburst = 0) or ((pageburst = 2) and r.cfg.pageburst = '0') then
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lineburst := true;
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else lineburst := false; end if;
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if ((ahbsi.hready and ahbsi.hsel(hindex)) = '1') then
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v.size := ahbsi.hsize(1 downto 0); v.hwrite := ahbsi.hwrite;
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v.htrans := ahbsi.htrans;
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if ahbsi.htrans(1) = '1' then
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v.hio := ahbsi.hmbsel(1);
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v.hsel := '1'; v.hready := v.hio;
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end if;
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v.haddr := ahbsi.haddr;
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-- addr must be masked since address range can be smaller than
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-- total banksize. this can result in wrong chip select being
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-- asserted
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for i in 31 downto 20 loop
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v.haddr(i) := ahbsi.haddr(i) and not std_rammask(i);
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end loop;
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end if;
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if (r.hsel = '1') and (ahbsi.hready = '0') then
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haddr := r.haddr; hsize := r.size;
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htrans := r.htrans; hwrite := r.hwrite;
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else
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haddr := ahbsi.haddr; hsize := ahbsi.hsize(1 downto 0);
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htrans := ahbsi.htrans; hwrite := ahbsi.hwrite;
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-- addr must be masked since address range can be smaller than
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-- total banksize. this can result in wrong chip select being
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-- asserted
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for i in 31 downto 20 loop
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haddr(i) := ahbsi.haddr(i) and not std_rammask(i);
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end loop;
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end if;
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if fast = 1 then haddr := r.haddr; end if;
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if ahbsi.hready = '1' then v.hsel := ahbsi.hsel(hindex); end if;
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-- main state
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case r.size is
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when "00" =>
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case r.haddr(1 downto 0) is
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when "00" => dqm := "11110111";
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when "01" => dqm := "11111011";
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when "10" => dqm := "11111101";
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when others => dqm := "11111110";
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end case;
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when "01" =>
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if r.haddr(1) = '0' then dqm := "11110011"; else dqm := "11111100"; end if;
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when others => dqm := "11110000";
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end case;
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if BUS64 and (r.bsel = '1') then dqm := dqm(3 downto 0) & "1111"; end if;
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-- main FSM
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case r.mstate is
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when midle =>
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if ((v.hsel and htrans(1) and not v.hio) = '1') then
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if (r.sdstate = sidle) and (r.cfg.command = "000")
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and (r.cmstate = midle) and (v.hio = '0')
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then
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if fast = 0 then startsd := '1'; else v.startsd := '1'; end if;
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v.mstate := active;
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elsif ((r.sdstate = sref) or (r.sdstate = pd) or (r.sdstate = dpd))
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and (r.cfg.command = "000") and (r.cmstate = midle) and (v.hio = '0')
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then
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v.startsd := '1';
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if r.sdstate = dpd then -- Error response when on Deep Power-Down mode
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v.hresp := HRESP_ERROR;
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else
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v.mstate := active;
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end if;
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end if;
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end if;
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when others => null;
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end case;
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startsd := startsd or r.startsd;
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269 |
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-- generate row and column address size
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270 |
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271 |
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case r.cfg.csize is
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when "00" => raddr := haddr(22 downto 10);
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when "01" => raddr := haddr(23 downto 11);
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when "10" => raddr := haddr(24 downto 12);
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when others =>
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if r.cfg.bsize = "111" then raddr := haddr(26 downto 14);
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else raddr := haddr(25 downto 13); end if;
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end case;
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279 |
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280 |
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-- generate bank address
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281 |
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282 |
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ba := genmux(r.cfg.bsize, haddr(28 downto 21)) &
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genmux(r.cfg.bsize, haddr(27 downto 20));
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284 |
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285 |
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-- generate chip select
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286 |
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287 |
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if BUS64 then
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288 |
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adec := genmux(r.cfg.bsize, haddr(30 downto 23));
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289 |
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v.bsel := genmux(r.cfg.bsize, r.haddr(29 downto 22));
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else
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adec := genmux(r.cfg.bsize, haddr(29 downto 22)); v.bsel := '0';
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292 |
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end if;
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293 |
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|
294 |
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rams := adec & not adec;
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295 |
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|
296 |
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-- sdram access FSM
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297 |
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298 |
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if r.trfc /= "0000" then v.trfc := r.trfc - 1; end if;
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299 |
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300 |
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if r.idlecnt /= "0000" then v.idlecnt := r.idlecnt - 1; end if;
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301 |
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302 |
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case r.sdstate is
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when sidle =>
|
304 |
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if (startsd = '1') and (r.cfg.command = "000") and (r.cmstate = midle) then
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v.address(16 downto 2) := ba & raddr;
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306 |
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v.sdcsn := not rams(1 downto 0); v.rasn := '0'; v.sdstate := act1;
|
307 |
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v.startsd := '0';
|
308 |
|
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elsif (r.idlecnt = "0000") and (r.cfg.command = "000")
|
309 |
|
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and (r.cmstate = midle) and (r.cfg.mobileen(1) = '1') then
|
310 |
|
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case r.cfg.pmode is
|
311 |
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when PM_SR =>
|
312 |
|
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v.cfg.cke := '0'; v.sdstate := sref;
|
313 |
|
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v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
|
314 |
|
|
v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc; -- Control minimum duration of Self Refresh mode (= tRAS)
|
315 |
|
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when PM_PD => v.cfg.cke := '0'; v.sdstate := pd;
|
316 |
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when PM_DPD =>
|
317 |
|
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v.cfg.cke := '0'; v.sdstate := dpd;
|
318 |
|
|
v.sdcsn := (others => '0'); v.sdwen := '0'; v.rasn := '1'; v.casn := '1';
|
319 |
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when others =>
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320 |
|
|
end case;
|
321 |
|
|
end if;
|
322 |
|
|
when act1 =>
|
323 |
|
|
v.rasn := '1'; v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc;
|
324 |
|
|
if r.cfg.casdel = '1' then v.sdstate := act2; else
|
325 |
|
|
v.sdstate := act3;
|
326 |
|
|
v.hready := r.hwrite and ahbsi.htrans(0) and ahbsi.htrans(1);
|
327 |
|
|
end if;
|
328 |
|
|
if WPROTEN then
|
329 |
|
|
v.wprothit := sdi.wprot;
|
330 |
|
|
if sdi.wprot = '1' then v.hresp := HRESP_ERROR; end if;
|
331 |
|
|
end if;
|
332 |
|
|
when act2 =>
|
333 |
|
|
v.sdstate := act3;
|
334 |
|
|
v.hready := r.hwrite and ahbsi.htrans(0) and ahbsi.htrans(1);
|
335 |
|
|
if WPROTEN and (r.wprothit = '1') then
|
336 |
|
|
v.hresp := HRESP_ERROR; v.hready := '0';
|
337 |
|
|
end if;
|
338 |
|
|
when act3 =>
|
339 |
|
|
v.casn := '0';
|
340 |
|
|
v.address(14 downto 2) := r.haddr(13 downto 12) & '0' & r.haddr(11 downto 2);
|
341 |
|
|
v.dqm := dqm; v.burst := r.hready;
|
342 |
|
|
|
343 |
|
|
if r.hwrite = '1' then
|
344 |
|
|
|
345 |
|
|
v.sdstate := wr1; v.sdwen := '0'; v.bdrive := '0';
|
346 |
|
|
if ahbsi.htrans = "11" or (r.hready = '0') then v.hready := '1'; end if;
|
347 |
|
|
if WPROTEN and (r.wprothit = '1') then
|
348 |
|
|
v.hresp := HRESP_ERROR; v.hready := '1';
|
349 |
|
|
v.sdstate := wr1; v.sdwen := '1'; v.bdrive := '1'; v.casn := '1';
|
350 |
|
|
end if;
|
351 |
|
|
else v.sdstate := rd1; end if;
|
352 |
|
|
when wr1 =>
|
353 |
|
|
v.address(14 downto 2) := r.haddr(13 downto 12) & '0' & r.haddr(11 downto 2);
|
354 |
|
|
if (((r.burst and r.hready) = '1') and (r.htrans = "11"))
|
355 |
|
|
and not (WPROTEN and (r.wprothit = '1'))
|
356 |
|
|
then
|
357 |
|
|
v.hready := ahbsi.htrans(0) and ahbsi.htrans(1) and r.hready;
|
358 |
|
|
if ((r.haddr(5 downto 2) = "1111") and (r.cfg.command = "100")) then -- exit on refresh
|
359 |
|
|
v.hready := '0';
|
360 |
|
|
end if;
|
361 |
|
|
else
|
362 |
|
|
v.sdstate := wr2; v.bdrive := '1'; v.casn := '1'; v.sdwen := '1';
|
363 |
|
|
v.dqm := (others => '1');
|
364 |
|
|
end if;
|
365 |
|
|
when wr2 =>
|
366 |
|
|
if (r.cfg.trp = '0') then v.rasn := '0'; v.sdwen := '0'; end if;
|
367 |
|
|
v.sdstate := wr3;
|
368 |
|
|
when wr3 =>
|
369 |
|
|
if (r.cfg.trp = '1') then
|
370 |
|
|
v.rasn := '0'; v.sdwen := '0'; v.sdstate := wr4;
|
371 |
|
|
else
|
372 |
|
|
v.sdcsn := "11"; v.rasn := '1'; v.sdwen := '1'; v.sdstate := sidle;
|
373 |
|
|
v.idlecnt := (others => '1');
|
374 |
|
|
end if;
|
375 |
|
|
when wr4 =>
|
376 |
|
|
v.sdcsn := "11"; v.rasn := '1'; v.sdwen := '1';
|
377 |
|
|
if (r.cfg.trp = '1') then v.sdstate := wr5;
|
378 |
|
|
else v.sdstate := sidle; v.idlecnt := (others => '1'); end if;
|
379 |
|
|
when wr5 =>
|
380 |
|
|
v.sdstate := sidle; v.idlecnt := (others => '1');
|
381 |
|
|
when rd1 =>
|
382 |
|
|
v.casn := '1'; v.sdstate := rd7;
|
383 |
|
|
if lineburst and (ahbsi.htrans = "11") then
|
384 |
|
|
if r.haddr(4 downto 2) = "111" then
|
385 |
|
|
v.address(9 downto 5) := r.address(9 downto 5) + 1;
|
386 |
|
|
v.address(4 downto 2) := "000"; v.casn := '0';
|
387 |
|
|
end if;
|
388 |
|
|
end if;
|
389 |
|
|
when rd7 =>
|
390 |
|
|
v.casn := '1';
|
391 |
|
|
if r.cfg.casdel = '1' then
|
392 |
|
|
v.sdstate := rd2;
|
393 |
|
|
if lineburst and (ahbsi.htrans = "11") then
|
394 |
|
|
if r.haddr(4 downto 2) = "110" then
|
395 |
|
|
v.address(9 downto 5) := r.address(9 downto 5) + 1;
|
396 |
|
|
v.address(4 downto 2) := "000"; v.casn := '0';
|
397 |
|
|
end if;
|
398 |
|
|
end if;
|
399 |
|
|
else
|
400 |
|
|
v.sdstate := rd3;
|
401 |
|
|
if ahbsi.htrans /= "11" then
|
402 |
|
|
if (r.trfc(3 downto 1) = "000") then v.rasn := '0'; v.sdwen := '0'; end if;
|
403 |
|
|
elsif lineburst then
|
404 |
|
|
if r.haddr(4 downto 2) = "110" then
|
405 |
|
|
v.address(9 downto 5) := r.address(9 downto 5) + 1;
|
406 |
|
|
v.address(4 downto 2) := "000"; v.casn := '0';
|
407 |
|
|
end if;
|
408 |
|
|
end if;
|
409 |
|
|
end if;
|
410 |
|
|
when rd2 =>
|
411 |
|
|
v.casn := '1'; v.sdstate := rd3;
|
412 |
|
|
if ahbsi.htrans /= "11" then v.rasn := '0'; v.sdwen := '0';
|
413 |
|
|
elsif lineburst then
|
414 |
|
|
if r.haddr(4 downto 2) = "101" then
|
415 |
|
|
v.address(9 downto 5) := r.address(9 downto 5) + 1;
|
416 |
|
|
v.address(4 downto 2) := "000"; v.casn := '0';
|
417 |
|
|
end if;
|
418 |
|
|
end if;
|
419 |
|
|
if v.sdwen = '0' then v.dqm := (others => '1'); end if;
|
420 |
|
|
when rd3 =>
|
421 |
|
|
v.sdstate := rd4; v.hready := '1'; v.casn := '1';
|
422 |
|
|
if r.sdwen = '0' then
|
423 |
|
|
v.rasn := '1'; v.sdwen := '1'; v.sdcsn := "11"; v.dqm := (others => '1');
|
424 |
|
|
elsif lineburst and (ahbsi.htrans = "11") and (r.casn = '1') then
|
425 |
|
|
if r.haddr(4 downto 2) = ("10" & not r.cfg.casdel) then
|
426 |
|
|
v.address(9 downto 5) := r.address(9 downto 5) + 1;
|
427 |
|
|
v.address(4 downto 2) := "000"; v.casn := '0';
|
428 |
|
|
end if;
|
429 |
|
|
end if;
|
430 |
|
|
|
431 |
|
|
when rd4 =>
|
432 |
|
|
v.hready := '1'; v.casn := '1';
|
433 |
|
|
if (ahbsi.htrans /= "11") or (r.sdcsn = "11") or
|
434 |
|
|
((r.haddr(5 downto 2) = "1111") and (r.cfg.command = "100")) -- exit on refresh
|
435 |
|
|
then
|
436 |
|
|
v.hready := '0'; v.dqm := (others => '1');
|
437 |
|
|
if (r.sdcsn /= "11") then
|
438 |
|
|
v.rasn := '0'; v.sdwen := '0'; v.sdstate := rd5;
|
439 |
|
|
else
|
440 |
|
|
if r.cfg.trp = '1' then v.sdstate := rd6;
|
441 |
|
|
else v.sdstate := sidle; v.idlecnt := (others => '1'); end if;
|
442 |
|
|
end if;
|
443 |
|
|
elsif lineburst then
|
444 |
|
|
if (r.haddr(4 downto 2) = lline) and (r.casn = '1') then
|
445 |
|
|
v.address(9 downto 5) := r.address(9 downto 5) + 1;
|
446 |
|
|
v.address(4 downto 2) := "000"; v.casn := '0';
|
447 |
|
|
end if;
|
448 |
|
|
end if;
|
449 |
|
|
when rd5 =>
|
450 |
|
|
if r.cfg.trp = '1' then v.sdstate := rd6; else v.sdstate := sidle; v.idlecnt := (others => '1'); end if;
|
451 |
|
|
v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1'; v.dqm := (others => '1');
|
452 |
|
|
v.casn := '1';
|
453 |
|
|
when rd6 =>
|
454 |
|
|
v.sdstate := sidle; v.idlecnt := (others => '1'); v.dqm := (others => '1');
|
455 |
|
|
|
456 |
|
|
v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1';
|
457 |
|
|
|
458 |
|
|
when sref =>
|
459 |
|
|
if (startsd = '1' and (r.hio = '0'))
|
460 |
|
|
or (r.cfg.command /= "000") or r.cfg.pmode /= PM_SR then
|
461 |
|
|
if r.trfc = "0000" then -- Minimum duration (= tRAS)
|
462 |
|
|
v.cfg.cke := '1';
|
463 |
|
|
v.sdcsn := (others => '0'); v.rasn := '1'; v.casn := '1';
|
464 |
|
|
end if;
|
465 |
|
|
if r.cfg.cke = '1' then
|
466 |
|
|
if (r.idlecnt = "0000") then -- tXSR ns with NOP
|
467 |
|
|
v.sdstate := sidle;
|
468 |
|
|
v.idlecnt := (others => '1');
|
469 |
|
|
v.sref_tmpcom := r.cfg.command;
|
470 |
|
|
v.cfg.command := "100";
|
471 |
|
|
end if;
|
472 |
|
|
else
|
473 |
|
|
v.idlecnt := r.cfg.txsr;
|
474 |
|
|
end if;
|
475 |
|
|
end if;
|
476 |
|
|
when pd =>
|
477 |
|
|
if (startsd = '1' and (r.hio = '0'))
|
478 |
|
|
or (r.cfg.command /= "000") or r.cfg.pmode /= PM_PD then
|
479 |
|
|
v.cfg.cke := '1';
|
480 |
|
|
v.sdstate := sidle;
|
481 |
|
|
v.idlecnt := (others => '1');
|
482 |
|
|
end if;
|
483 |
|
|
when dpd =>
|
484 |
|
|
v.sdcsn := (others => '1'); v.sdwen := '1'; v.rasn := '1'; v.casn := '1';
|
485 |
|
|
v.cfg.renable := '0';
|
486 |
|
|
if (startsd = '1' and r.hio = '0') then
|
487 |
|
|
v.hready := '1'; -- ack all accesses with Error response
|
488 |
|
|
v.startsd := '0';
|
489 |
|
|
v.hresp := HRESP_ERROR;
|
490 |
|
|
elsif r.cfg.pmode /= PM_DPD then
|
491 |
|
|
v.cfg.cke := '1';
|
492 |
|
|
if r.cfg.cke = '1' then
|
493 |
|
|
v.sdstate := sidle;
|
494 |
|
|
v.idlecnt := (others => '1');
|
495 |
|
|
v.cfg.renable := '1';
|
496 |
|
|
end if;
|
497 |
|
|
end if;
|
498 |
|
|
when others =>
|
499 |
|
|
v.sdstate := sidle; v.idlecnt := (others => '1');
|
500 |
|
|
end case;
|
501 |
|
|
|
502 |
|
|
-- sdram commands
|
503 |
|
|
|
504 |
|
|
case r.cmstate is
|
505 |
|
|
when midle =>
|
506 |
|
|
if r.sdstate = sidle then
|
507 |
|
|
case r.cfg.command is
|
508 |
|
|
when "010" => -- precharge
|
509 |
|
|
v.sdcsn := (others => '0'); v.rasn := '0'; v.sdwen := '0';
|
510 |
|
|
v.address(12) := '1'; v.cmstate := active;
|
511 |
|
|
when "100" => -- auto-refresh
|
512 |
|
|
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
|
513 |
|
|
v.cmstate := active;
|
514 |
|
|
when "110" => -- Lodad Mode Reg
|
515 |
|
|
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
|
516 |
|
|
v.sdwen := '0'; v.cmstate := active;
|
517 |
|
|
if lineburst then
|
518 |
|
|
v.address(16 downto 2) := "0000010001" & r.cfg.casdel & "0011";
|
519 |
|
|
else
|
520 |
|
|
v.address(16 downto 2) := "0000010001" & r.cfg.casdel & "0111";
|
521 |
|
|
end if;
|
522 |
|
|
when "111" => -- Load Ext-Mode Reg
|
523 |
|
|
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
|
524 |
|
|
v.sdwen := '0'; v.cmstate := active;
|
525 |
|
|
v.address(16 downto 2) := "10000000" & r.cfg.ds(1 downto 0) & r.cfg.tcsr(1 downto 0)
|
526 |
|
|
& r.cfg.pasr(2 downto 0);
|
527 |
|
|
when others => null;
|
528 |
|
|
end case;
|
529 |
|
|
end if;
|
530 |
|
|
when active =>
|
531 |
|
|
v.sdcsn := (others => '1'); v.rasn := '1'; v.casn := '1';
|
532 |
|
|
v.sdwen := '1'; --v.cfg.command := "000";
|
533 |
|
|
v.cfg.command := r.sref_tmpcom; v.sref_tmpcom := "000";
|
534 |
|
|
v.cmstate := leadout; v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc;
|
535 |
|
|
when leadout =>
|
536 |
|
|
if r.trfc = "0000" then v.cmstate := midle; end if;
|
537 |
|
|
|
538 |
|
|
end case;
|
539 |
|
|
|
540 |
|
|
-- sdram init
|
541 |
|
|
|
542 |
|
|
case r.istate is
|
543 |
|
|
when iidle =>
|
544 |
|
|
v.cfg.cke := '1';
|
545 |
|
|
if r.cfg.renable = '1' and r.cfg.cke = '1' then
|
546 |
|
|
v.cfg.command := "010"; v.istate := pre;
|
547 |
|
|
end if;
|
548 |
|
|
when pre =>
|
549 |
|
|
if r.cfg.command = "000" then
|
550 |
|
|
v.cfg.command := "100"; v.istate := ref; v.icnt := "111";
|
551 |
|
|
end if;
|
552 |
|
|
when ref =>
|
553 |
|
|
if r.cfg.command = "000" then
|
554 |
|
|
v.cfg.command := "100"; v.icnt := r.icnt - 1;
|
555 |
|
|
if r.icnt = "000" then v.istate := lmode; v.cfg.command := "110"; end if;
|
556 |
|
|
end if;
|
557 |
|
|
when lmode =>
|
558 |
|
|
if r.cfg.command = "000" then
|
559 |
|
|
if r.cfg.mobileen = "11" then
|
560 |
|
|
v.cfg.command := "111"; v.istate := emode;
|
561 |
|
|
else
|
562 |
|
|
v.istate := finish;
|
563 |
|
|
end if;
|
564 |
|
|
end if;
|
565 |
|
|
when emode =>
|
566 |
|
|
if r.cfg.command = "000" then
|
567 |
|
|
v.istate := finish;
|
568 |
|
|
end if;
|
569 |
|
|
when others =>
|
570 |
|
|
if r.cfg.renable = '0' and r.sdstate /= dpd then
|
571 |
|
|
v.istate := iidle;
|
572 |
|
|
end if;
|
573 |
|
|
end case;
|
574 |
|
|
|
575 |
|
|
if (ahbsi.hready and ahbsi.hsel(hindex) ) = '1' then
|
576 |
|
|
if ahbsi.htrans(1) = '0' then v.hready := '1'; end if;
|
577 |
|
|
end if;
|
578 |
|
|
|
579 |
|
|
if (r.hsel and r.hio and not r.hready) = '1' then v.hready := '1'; end if;
|
580 |
|
|
|
581 |
|
|
-- second part of main fsm
|
582 |
|
|
|
583 |
|
|
case r.mstate is
|
584 |
|
|
when active =>
|
585 |
|
|
if v.hready = '1' then
|
586 |
|
|
v.mstate := midle;
|
587 |
|
|
end if;
|
588 |
|
|
when others => null;
|
589 |
|
|
end case;
|
590 |
|
|
|
591 |
|
|
-- sdram refresh counter
|
592 |
|
|
|
593 |
|
|
-- pragma translate_off
|
594 |
|
|
if not is_x(r.cfg.refresh) then
|
595 |
|
|
-- pragma translate_on
|
596 |
|
|
if (r.cfg.renable = '1') and (r.istate = finish) and r.sdstate /= sref then
|
597 |
|
|
v.refresh := r.refresh - 1;
|
598 |
|
|
if (v.refresh(14) and not r.refresh(14)) = '1' then
|
599 |
|
|
v.refresh := r.cfg.refresh;
|
600 |
|
|
v.cfg.command := "100";
|
601 |
|
|
arefresh := '1';
|
602 |
|
|
end if;
|
603 |
|
|
end if;
|
604 |
|
|
-- pragma translate_off
|
605 |
|
|
end if;
|
606 |
|
|
-- pragma translate_on
|
607 |
|
|
|
608 |
|
|
-- AHB register access
|
609 |
|
|
|
610 |
|
|
if (r.hsel and r.hio and r.hwrite and r.htrans(1)) = '1' then
|
611 |
|
|
if r.haddr(3 downto 2) = "00" then
|
612 |
|
|
if pageburst = 2 then v.cfg.pageburst := ahbsi.hwdata(17); end if;
|
613 |
|
|
v.cfg.command := ahbsi.hwdata(20 downto 18);
|
614 |
|
|
v.cfg.csize := ahbsi.hwdata(22 downto 21);
|
615 |
|
|
v.cfg.bsize := ahbsi.hwdata(25 downto 23);
|
616 |
|
|
v.cfg.casdel := ahbsi.hwdata(26);
|
617 |
|
|
v.cfg.trfc := ahbsi.hwdata(29 downto 27);
|
618 |
|
|
v.cfg.trp := ahbsi.hwdata(30);
|
619 |
|
|
v.cfg.renable := ahbsi.hwdata(31);
|
620 |
|
|
v.cfg.refresh := ahbsi.hwdata(14 downto 0);
|
621 |
|
|
v.refresh := (others => '0');
|
622 |
|
|
elsif r.haddr(3 downto 2) = "01" then
|
623 |
|
|
if r.cfg.mobileen(1) = '1' and mobile /= 3 then v.cfg.mobileen(0) := ahbsi.hwdata(31); end if;
|
624 |
|
|
if r.cfg.pmode = "000" then
|
625 |
|
|
v.cfg.cke := ahbsi.hwdata(30);
|
626 |
|
|
end if;
|
627 |
|
|
if r.cfg.mobileen(1) = '1' then
|
628 |
|
|
v.cfg.txsr := ahbsi.hwdata(23 downto 20);
|
629 |
|
|
v.cfg.pmode := ahbsi.hwdata(18 downto 16);
|
630 |
|
|
v.cfg.ds(3 downto 2) := ahbsi.hwdata( 6 downto 5);
|
631 |
|
|
v.cfg.tcsr(3 downto 2) := ahbsi.hwdata( 4 downto 3);
|
632 |
|
|
v.cfg.pasr(5 downto 3) := ahbsi.hwdata( 2 downto 0);
|
633 |
|
|
end if;
|
634 |
|
|
end if;
|
635 |
|
|
end if;
|
636 |
|
|
|
637 |
|
|
-- Disable CS and DPD when Mobile SDR is Disabled
|
638 |
|
|
if r.cfg.mobileen(0) = '0' then v.cfg.pmode(2) := '0'; end if;
|
639 |
|
|
|
640 |
|
|
-- Update EMR when ds, tcsr or pasr change
|
641 |
|
|
if r.cfg.command = "000" and arefresh = '0' and r.cfg.mobileen(0) = '1' then
|
642 |
|
|
if r.cfg.ds(1 downto 0) /= r.cfg.ds(3 downto 2) then
|
643 |
|
|
v.cfg.command := "111"; v.cfg.ds(1 downto 0) := r.cfg.ds(3 downto 2);
|
644 |
|
|
end if;
|
645 |
|
|
if r.cfg.tcsr(1 downto 0) /= r.cfg.tcsr(3 downto 2) then
|
646 |
|
|
v.cfg.command := "111"; v.cfg.tcsr(1 downto 0) := r.cfg.tcsr(3 downto 2);
|
647 |
|
|
end if;
|
648 |
|
|
if r.cfg.pasr(2 downto 0) /= r.cfg.pasr(5 downto 3) then
|
649 |
|
|
v.cfg.command := "111"; v.cfg.pasr(2 downto 0) := r.cfg.pasr(5 downto 3);
|
650 |
|
|
end if;
|
651 |
|
|
end if;
|
652 |
|
|
|
653 |
|
|
regsd := (others => '0');
|
654 |
|
|
|
655 |
|
|
if r.haddr(3 downto 2) = "00" then
|
656 |
|
|
regsd(31 downto 18) := r.cfg.renable & r.cfg.trp & r.cfg.trfc &
|
657 |
|
|
r.cfg.casdel & r.cfg.bsize & r.cfg.csize & r.cfg.command;
|
658 |
|
|
if not lineburst then regsd(17) := '1'; end if;
|
659 |
|
|
regsd(16) := r.cfg.mobileen(1);
|
660 |
|
|
if BUS64 then regsd(15) := '1'; end if;
|
661 |
|
|
regsd(14 downto 0) := r.cfg.refresh;
|
662 |
|
|
elsif r.haddr(3 downto 2) = "01" then
|
663 |
|
|
regsd(31) := r.cfg.mobileen(0);
|
664 |
|
|
regsd(30) := r.cfg.cke;
|
665 |
|
|
regsd(23 downto 0) := r.cfg.txsr & '0' & r.cfg.pmode & "000000000" &
|
666 |
|
|
r.cfg.ds(1 downto 0) & r.cfg.tcsr(1 downto 0) & r.cfg.pasr(2 downto 0);
|
667 |
|
|
end if;
|
668 |
|
|
|
669 |
|
|
if (r.hsel and r.hio) = '1' then dout := regsd;
|
670 |
|
|
else
|
671 |
|
|
if BUS64 and r.bsel = '1' then dout := r.hrdata(63 downto 32);
|
672 |
|
|
else dout := r.hrdata(31 downto 0); end if;
|
673 |
|
|
end if;
|
674 |
|
|
|
675 |
|
|
v.nbdrive := not v.bdrive;
|
676 |
|
|
|
677 |
|
|
if oepol = 1 then bdrive := r.nbdrive; vbdrive := (others => v.nbdrive);
|
678 |
|
|
else bdrive := r.bdrive; vbdrive := (others => v.bdrive);end if;
|
679 |
|
|
|
680 |
|
|
-- reset
|
681 |
|
|
|
682 |
|
|
if rst = '0' then
|
683 |
|
|
v.sdstate := sidle;
|
684 |
|
|
v.mstate := midle;
|
685 |
|
|
v.istate := iidle;
|
686 |
|
|
v.cmstate := midle;
|
687 |
|
|
v.hsel := '0';
|
688 |
|
|
v.cfg.command := "000";
|
689 |
|
|
v.cfg.csize := "10";
|
690 |
|
|
v.cfg.bsize := "000";
|
691 |
|
|
v.cfg.casdel := '1';
|
692 |
|
|
v.cfg.trfc := "111";
|
693 |
|
|
if pwron = 1 then v.cfg.renable := '1';
|
694 |
|
|
else v.cfg.renable := '0'; end if;
|
695 |
|
|
v.cfg.trp := '1';
|
696 |
|
|
v.dqm := (others => '1');
|
697 |
|
|
v.sdwen := '1';
|
698 |
|
|
v.rasn := '1';
|
699 |
|
|
v.casn := '1';
|
700 |
|
|
v.hready := '1';
|
701 |
|
|
v.bsel := '0';
|
702 |
|
|
v.startsd := '0';
|
703 |
|
|
if (pageburst = 2) then
|
704 |
|
|
v.cfg.pageburst := '0';
|
705 |
|
|
end if;
|
706 |
|
|
if mobile >= 2 then v.cfg.mobileen := "11";
|
707 |
|
|
elsif mobile = 1 then v.cfg.mobileen := "10";
|
708 |
|
|
else v.cfg.mobileen := "00"; end if;
|
709 |
|
|
v.cfg.txsr := (others => '1');
|
710 |
|
|
v.cfg.pmode := (others => '0');
|
711 |
|
|
v.cfg.ds := (others => '0');
|
712 |
|
|
v.cfg.tcsr := (others => '0');
|
713 |
|
|
v.cfg.pasr := (others => '0');
|
714 |
|
|
if mobile >= 2 then v.cfg.cke := '0';
|
715 |
|
|
else v.cfg.cke := '1'; end if;
|
716 |
|
|
v.sref_tmpcom := "000";
|
717 |
|
|
v.idlecnt := (others => '1');
|
718 |
|
|
end if;
|
719 |
|
|
|
720 |
|
|
ri <= v;
|
721 |
|
|
ribdrive <= vbdrive;
|
722 |
|
|
|
723 |
|
|
ahbso.hready <= r.hready;
|
724 |
|
|
ahbso.hresp <= r.hresp;
|
725 |
|
|
ahbso.hrdata <= dout;
|
726 |
|
|
ahbso.hcache <= not r.hio;
|
727 |
|
|
|
728 |
|
|
end process;
|
729 |
|
|
|
730 |
|
|
--sdo.sdcke <= (others => '1');
|
731 |
|
|
sdo.sdcke <= (others => r.cfg.cke);
|
732 |
|
|
ahbso.hconfig <= hconfig;
|
733 |
|
|
ahbso.hirq <= (others => '0');
|
734 |
|
|
ahbso.hindex <= hindex;
|
735 |
|
|
ahbso.hsplit <= (others => '0');
|
736 |
|
|
|
737 |
|
|
regs : process(clk, rst) begin
|
738 |
|
|
if rising_edge(clk) then
|
739 |
|
|
r <= ri; rbdrive <= ribdrive;
|
740 |
|
|
if rst = '0' then r.icnt <= (others => '0'); end if;
|
741 |
|
|
end if;
|
742 |
|
|
if (rst = '0') then
|
743 |
|
|
r.sdcsn <= (others => '1'); r.bdrive <= '1'; r.nbdrive <= '0';
|
744 |
|
|
if oepol = 0 then rbdrive <= (others => '1');
|
745 |
|
|
else rbdrive <= (others => '0'); end if;
|
746 |
|
|
end if;
|
747 |
|
|
end process;
|
748 |
|
|
|
749 |
|
|
rgen : if not SDINVCLK generate
|
750 |
|
|
sdo.address <= r.address;
|
751 |
|
|
sdo.bdrive <= r.nbdrive when oepol = 1 else r.bdrive;
|
752 |
|
|
sdo.vbdrive <= rbdrive;
|
753 |
|
|
sdo.sdcsn <= r.sdcsn;
|
754 |
|
|
sdo.sdwen <= r.sdwen;
|
755 |
|
|
sdo.dqm <= "11111111" & r.dqm;
|
756 |
|
|
sdo.rasn <= r.rasn;
|
757 |
|
|
sdo.casn <= r.casn;
|
758 |
|
|
sdo.data(31 downto 0) <= r.hwdata;
|
759 |
|
|
end generate;
|
760 |
|
|
|
761 |
|
|
ngen : if SDINVCLK generate
|
762 |
|
|
nregs : process(clk, rst) begin
|
763 |
|
|
if falling_edge(clk) then
|
764 |
|
|
sdo.address <= r.address;
|
765 |
|
|
if oepol = 1 then sdo.bdrive <= r.nbdrive;
|
766 |
|
|
else sdo.bdrive <= r.bdrive; end if;
|
767 |
|
|
sdo.vbdrive <= rbdrive;
|
768 |
|
|
sdo.sdcsn <= r.sdcsn;
|
769 |
|
|
sdo.sdwen <= r.sdwen;
|
770 |
|
|
sdo.dqm <= "11111111" & r.dqm;
|
771 |
|
|
sdo.rasn <= r.rasn;
|
772 |
|
|
sdo.casn <= r.casn;
|
773 |
|
|
sdo.data(31 downto 0) <= r.hwdata;
|
774 |
|
|
end if;
|
775 |
|
|
if rst = '0' then sdo.sdcsn <= (others => '1'); end if;
|
776 |
|
|
end process;
|
777 |
|
|
end generate;
|
778 |
|
|
|
779 |
|
|
-- pragma translate_off
|
780 |
|
|
bootmsg : report_version
|
781 |
|
|
generic map ("sdctrl" & tost(hindex) &
|
782 |
|
|
": PC133 SDRAM controller rev " & tost(REVISION));
|
783 |
|
|
-- pragma translate_on
|
784 |
|
|
|
785 |
|
|
end;
|
786 |
|
|
|