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dimamali |
--------------------------------------------------------------------
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-- Entity: SPI_OC
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-- File: spi_oc.vhd
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-- Author: Thomas Ameseder, Gleichmann Electronics
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--
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-- Description: VHDL wrapper for the Opencores SPI core with APB
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-- interface
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--------------------------------------------------------------------
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-- CVS Entries:
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-- $Date: 2006/12/04 14:44:05 $
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-- $Author: tame $
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-- $Log: spi_oc.vhd,v $
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-- Revision 1.3 2006/12/04 14:44:05 tame
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-- Changed interrupt output to LEON from a level (that is active until it is reset) to
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-- a short pulse.
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--
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-- Revision 1.1 2006/11/17 12:28:56 tame
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-- Added SPI files: Simple SPI package and a wrapper for the (modified)
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-- OpenCores Simple SPI Core with APB interface.
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--
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--------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library grlib;
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use grlib.amba.all;
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use grlib.stdlib.all;
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use grlib.devices.all;
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library opencores;
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use opencores.occomp.all;
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library gleichmann;
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use gleichmann.sspi.all;
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-- pragma translate_off
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use std.textio.all;
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-- pragma translate_on
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entity spi_oc is
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generic (
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pindex : integer := 0; -- Leon-Index
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paddr : integer := 0; -- Leon-Address
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pmask : integer := 16#FFF#; -- Leon-Mask
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pirq : integer := 0 -- Leon-IRQ
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);
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port (
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rstn : in std_ulogic; -- global Reset, active low
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clk : in std_ulogic; -- global Clock
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apbi : in apb_slv_in_type; -- APB-Input
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apbo : out apb_slv_out_type; -- APB-Output
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spi_in : in sspi_in_type; -- MultIO-Inputs
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spi_out : out sspi_out_type -- Spi-Outputs
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);
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end entity spi_oc;
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architecture implementation of spi_oc is
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constant data_width : integer := 8;
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constant address_width : integer := 3;
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constant REVISION : integer := 0;
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constant pconfig : apb_config_type := (
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1 => apb_iobar(paddr, pmask)
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);
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signal irq : std_ulogic;
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signal irq_1t : std_ulogic;
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signal irq_adapt : std_ulogic; -- registered and converted to rising edge activity
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begin
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simple_spi_top_1 : simple_spi_top
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port map (
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prdata_o => apbo.prdata(data_width-1 downto 0),
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pirq_o => irq,
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sck_o => spi_out.sck,
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mosi_o => spi_out.mosi,
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ssn_o => spi_out.ssn,
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pclk_i => clk,
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prst_i => rstn,
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psel_i => apbi.psel(pindex),
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penable_i => apbi.penable,
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paddr_i => apbi.paddr(address_width+1 downto 2), -- 32-bit addresses
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pwrite_i => apbi.pwrite,
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pwdata_i => apbi.pwdata(data_width-1 downto 0),
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miso_i => spi_in.miso);
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-- drive selected interrupt, remaining bits with zeroes
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apbo.pirq(NAHBIRQ-1 downto pirq+1) <= (others => '0');
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-- apbo.pirq(pirq) <= irq; -- corrected by MH, 28.11.2006
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apbo.pirq(pirq) <= irq_adapt;
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apbo.pirq(pirq-1 downto 0) <= (others => '0');
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-- drive unused data bits with don't cares
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apbo.prdata(31 downto data_width) <= (others => '0');
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-- drive index for diagnostic use
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apbo.pindex <= pindex;
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-- drive slave configuration
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apbo.pconfig <= pconfig;
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---------------------------------------------------------------------------------------
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-- Synchronous process to convert the high level interrupt from the core to
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-- to an rising edge triggered interrupt to be suitable for the Leon IRQCTL
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-- asynchronous low active reset like the open core simple SPI module !!!
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---------------------------------------------------------------------------------------
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irq_adaption: process (clk, rstn) -- added by MH, 28.11.2006
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begin -- process irq_adaption)
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if rstn = '0' then
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irq_adapt <= '0';
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irq_1t <= '0';
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elsif clk'event and clk = '1' then
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irq_1t <= irq;
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irq_adapt <= irq and not irq_1t;
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end if;
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end process irq_adaption;
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---------------------------------------------------------------------------------------
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-- DEBUG SECTION
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---------------------------------------------------------------------------------------
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-- pragma translate_off
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assert (pirq < 15 and pirq > 0 ) report
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"Simple SPI Controller interrupt warning: " &
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"0 does not exist, 15 is unmaskable, 16 to 31 are unused"
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severity warning;
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bootmsg : report_version
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generic map ("SPI_OC: Simple SPI Controller rev " & tost(REVISION) &
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", IRQ " & tost(pirq) &
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", APB slave " & tost(pindex));
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-- pragma translate_on
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end architecture implementation;
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