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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [lib/] [opencores/] [ata/] [ocidec2_controller.vhd] - Blame information for rev 2

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---------------------------------------------------------------------
----                                                             ----
----  OpenCores IDE Controller                                   ----
----  ATA/ATAPI-5 Controller (OCIDEC-2)                          ----
----                                                             ----
----  Author: Richard Herveille                                  ----
----          richard@asics.ws                                   ----
----          www.asics.ws                                       ----
----                                                             ----
---------------------------------------------------------------------
----                                                             ----
---- Copyright (C) 2001, 2002 Richard Herveille                  ----
----                          richard@asics.ws                   ----
----                                                             ----
---- This source file may be used and distributed without        ----
---- restriction provided that this copyright statement is not   ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
----                                                             ----
----     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ----
---- LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ----
---- POSSIBILITY OF SUCH DAMAGE.                                 ----
----                                                             ----
---------------------------------------------------------------------
 
-- rev.: 1.0  march 18th, 2001. Initial release
-- rev.: 1.0a april 12th, 2001. Removed references to records.vhd
-- rev.: 1.1  june  18th, 2001. Changed PIOack generation. Avoid asserting PIOack continuously when IDEen = '0'
-- rev.: 1.2  june  26th, 2001. Changed dPIOreq generation. Core did not support wishbone burst accesses to ATA-device.
-- rev.: 1.3  july  11th, 2001. Changed PIOreq & PIOack generation (made them synchronous). 
--
--  CVS Log
--
--  $Id: atahost_controller.vhd,v 1.2 2002/05/19 06:07:09 rherveille Exp $
--
--  $Date: 2002/05/19 06:07:09 $
--  $Revision: 1.2 $
--  $Author: rherveille $
--  $Locker:  $
--  $State: Exp $
--
-- Change History:
--               $Log: atahost_controller.vhd,v $
--               Revision 1.2  2002/05/19 06:07:09  rherveille
--               Fixed a potential bug where the core was forced into an unknown state
--               when an asynchronous reset was given without a running clock.
--
--
 
--
-- OCIDEC2 supports:    
-- -Common Compatible timing access to all connected devices
--      -Separate timing accesses to data port
-- -No DMA support
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
entity ocidec2_controller is
        generic(
                TWIDTH : natural := 8;                   -- counter width
 
                -- PIO mode 0 settings (@100MHz clock)
                PIO_mode0_T1 : natural := 6;             -- 70ns
                PIO_mode0_T2 : natural := 28;            -- 290ns
                PIO_mode0_T4 : natural := 2;             -- 30ns
                PIO_mode0_Teoc : natural := 23           -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240
        );
        port(
                clk    : in std_logic;                                            -- master clock in
                nReset  : in std_logic := '1';                 -- asynchronous active low reset
                rst    : in std_logic := '0';                    -- synchronous active high reset
 
                irq : out std_logic;                          -- interrupt request signal
 
                -- control / registers
                IDEctrl_rst,
                IDEctrl_IDEen,
                IDEctrl_FATR0,
                IDEctrl_FATR1 : in std_logic;
 
                -- PIO registers
                cmdport_T1,
                cmdport_T2,
                cmdport_T4,
                cmdport_Teoc : in std_logic_vector(7 downto 0);
                cmdport_IORDYen : in std_logic;             -- PIO command port / non-fast timing
 
                dport0_T1,
                dport0_T2,
                dport0_T4,
                dport0_Teoc : in std_logic_vector(7 downto 0);
                dport0_IORDYen : in std_logic;              -- PIO mode data-port / fast timing device 0
 
                dport1_T1,
                dport1_T2,
                dport1_T4,
                dport1_Teoc : in std_logic_vector(7 downto 0);
                dport1_IORDYen : in std_logic;              -- PIO mode data-port / fast timing device 1
 
                PIOreq : in std_logic;                      -- PIO transfer request
                PIOack : out std_logic;                  -- PIO transfer ended
                PIOa   : in std_logic_vector(3 downto 0);           -- PIO address
                PIOd   : in std_logic_vector(15 downto 0);  -- PIO data in
                PIOq   : out std_logic_vector(15 downto 0); -- PIO data out
                PIOwe  : in std_logic;                      -- PIO direction bit '1'=write, '0'=read
 
                -- ATA signals
                RESETn  : out std_logic;
                DDi      : in std_logic_vector(15 downto 0);
                DDo  : out std_logic_vector(15 downto 0);
                DDoe : out std_logic;
                DA        : out std_logic_vector(2 downto 0);
                CS0n    : out std_logic;
                CS1n    : out std_logic;
 
                DIORn   : out std_logic;
                DIOWn   : out std_logic;
                IORDY   : in std_logic;
                INTRQ   : in std_logic
        );
end entity ocidec2_controller;
 
architecture structural of ocidec2_controller is
        --
        -- component declarations
        --
        component atahost_pio_actrl is
        generic(
                TWIDTH : natural := 8;                     -- counter width
 
                -- PIO mode 0 settings (@100MHz clock)
                PIO_mode0_T1 : natural := 6;               -- 70ns
                PIO_mode0_T2 : natural := 28;              -- 290ns
                PIO_mode0_T4 : natural := 2;               -- 30ns
                PIO_mode0_Teoc : natural := 23             -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240
        );
        port(
                clk    : in std_logic;                     -- master clock
                nReset : in std_logic;                     -- asynchronous active low reset
                rst    : in std_logic;                     -- synchronous active high reset
 
                IDEctrl_FATR0,
                IDEctrl_FATR1 : in std_logic;
 
                cmdport_T1,
                cmdport_T2,
                cmdport_T4,
                cmdport_Teoc : in std_logic_vector(7 downto 0);
                cmdport_IORDYen : in std_logic;            -- PIO command port / non-fast timing
 
                dport0_T1,
                dport0_T2,
                dport0_T4,
                dport0_Teoc : in std_logic_vector(7 downto 0);
                dport0_IORDYen : in std_logic;             -- PIO mode data-port / fast timing device 0
 
                dport1_T1,
                dport1_T2,
                dport1_T4,
                dport1_Teoc : in std_logic_vector(7 downto 0);
                dport1_IORDYen : in std_logic;             -- PIO mode data-port / fast timing device 1
 
                SelDev : in std_logic;                     -- Selected device   
 
                go   : in  std_logic;                      -- Start transfer sequence
                done : out std_logic;                      -- Transfer sequence done
                dir  : in  std_logic;                      -- Transfer direction '1'=write, '0'=read
                a    : in  std_logic_vector(3 downto 0);           -- PIO transfer address
                q    : out std_logic_vector(15 downto 0);  -- Data read from ATA devices
 
                DDi : in std_logic_vector(15 downto 0);    -- Data from ATA DD bus
                oe  : out std_logic;                    -- DDbus output-enable signal
 
                DIOR,
                DIOW  : out std_logic;
                IORDY : in std_logic
        );
        end component;
 
        --
        -- signals
        --
        signal SelDev : std_logic;                      -- selected device
 
        signal dPIOreq, PIOgo : std_logic;              -- start PIO timing controller
        signal PIOdone : std_logic;                     -- PIO timing controller done
 
        -- PIO signals
        signal PIOdior, PIOdiow : std_logic;
        signal PIOoe   : std_logic;
        signal rPIOack : std_logic;
        -- synchronized ATA inputs
        signal sIORDY : std_logic;
 
begin
 
        --
        -- synchronize incoming signals
        --
        synch_incoming: block
                signal cIORDY : std_logic;                   -- capture IORDY
                signal cINTRQ : std_logic;                   -- capture INTRQ
        begin
                process(clk)
                begin
                        if (clk'event and clk = '1') then
                                cIORDY <= IORDY;
                                cINTRQ <= INTRQ;
 
                                sIORDY <= cIORDY;
                                irq    <= cINTRQ;
                        end if;
                end process;
        end block synch_incoming;
 
        --
        -- generate ATA signals
        --
        gen_ata_sigs: block
        begin
                -- generate registers for ATA signals
                gen_regs: process(clk, nReset)
                begin
                        if (nReset = '0') then
                                RESETn <= '0';
                                DIORn  <= '1';
                                DIOWn  <= '1';
                                DA     <= (others => '0');
                                CS0n      <= '1';
                                CS1n      <= '1';
                                DDo    <= (others => '0');
                                DDoe   <= '0';
                        elsif (clk'event and clk = '1') then
                                if (rst = '1') then
                                        RESETn <= '0';
                                        DIORn  <= '1';
                                        DIOWn  <= '1';
                                        DA     <= (others => '0');
                                        CS0n   <= '1';
                                        CS1n    <= '1';
                                        DDo    <= (others => '0');
                                        DDoe   <= '0';
                                else
                                        RESETn <= not IDEctrl_rst;
                                        DA   <= PIOa(2 downto 0);
                                        CS0n    <= not (not PIOa(3) and PIOreq); -- CS0 asserted when A(3) = '0'
                                        CS1n    <= not (    PIOa(3) and PIOreq); -- CS1 asserted when A(3) = '1'
 
                                        DDo   <= PIOd;
                                        DDoe  <= PIOoe;
                                        DIORn <= not PIOdior;
                                        DIOWn <= not PIOdiow;
                                end if;
                        end if;
                end process gen_regs;
        end block gen_ata_sigs;
 
        --
        -- generate selected device
        --
        gen_seldev: process(clk)
                variable Asel : std_logic; -- address selected
        begin
                if (clk'event and clk = '1') then
                        Asel := not PIOa(3) and PIOa(2) and PIOa(1) and not PIOa(0); -- header/device register
                        if ( (PIOdone = '1') and (Asel = '1') and (PIOwe = '1') ) then
                                SelDev <= PIOd(4);
                        end if;
                end if;
        end process gen_seldev;
 
        -- generate PIOgo signal
        gen_PIOgo: process(clk, nReset)
        begin
                if (nReset = '0') then
                        dPIOreq <= '0';
                        PIOgo   <= '0';
                elsif (clk'event and clk = '1') then
                        if (rst = '1') then
                                dPIOreq <= '0';
                                PIOgo   <= '0';
                        else
                                dPIOreq <= PIOreq and not rPIOack;
                                PIOgo   <= (PIOreq and not dPIOreq) and IDEctrl_IDEen;
                        end if;
        end if;
        end process gen_PIOgo;
        --
        -- Hookup PIO access controller
        --
        pio_access_control: atahost_pio_actrl
                generic map(
                        TWIDTH => TWIDTH,
                        PIO_mode0_T1 => PIO_mode0_T1,
                        PIO_mode0_T2 => PIO_mode0_T2,
                        PIO_mode0_T4 => PIO_mode0_T4,
                        PIO_mode0_Teoc => PIO_mode0_Teoc
                )
                port map(
                        clk    => clk,
                        nReset => nReset,
                        rst    => rst,
                        IDEctrl_FATR0 => IDEctrl_FATR0,
                        IDEctrl_FATR1 => IDEctrl_FATR1,
                        cmdport_T1    => cmdport_T1,
                        cmdport_T2    => cmdport_T2,
                        cmdport_T4    => cmdport_T4,
                        cmdport_Teoc  => cmdport_Teoc,
                        cmdport_IORDYen => cmdport_IORDYen,
                        dport0_T1     => dport0_T1,
                        dport0_T2     => dport0_T2,
                        dport0_T4     => dport0_T4,
                        dport0_Teoc   => dport0_Teoc,
                        dport0_IORDYen => dport0_IORDYen,
                        dport1_T1     => dport1_T1,
                        dport1_T2     => dport1_T2,
                        dport1_T4     => dport1_T4,
                        dport1_Teoc   => dport1_Teoc,
                        dport1_IORDYen => dport1_IORDYen,
                        SelDev => SelDev,
                        go     => PIOgo,
                        done   => PIOdone,
                        dir    => PIOwe,
                        a      => PIOa,
                        q      => PIOq,
                        DDi    => DDi,
                        oe     => PIOoe,
                        DIOR   => PIOdior,
                        DIOW   => PIOdiow,
                        IORDY  => sIORDY
                );
 
        -- generate acknowledge
        gen_ack: process(clk)
        begin
                if (clk'event and clk = '1') then
                        rPIOack <= PIOdone or (PIOreq and not IDEctrl_IDEen); -- acknowledge when done or when IDE not enabled (discard request)
                end if;
           PIOack <= rPIOack;
   end process gen_ack;
end architecture structural;
 

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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [lib/] [opencores/] [ata/] [ocidec2_controller.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	dimamali	`---------------------------------------------------------------------`
2			`---- ----`
3			`---- OpenCores IDE Controller ----`
4			`---- ATA/ATAPI-5 Controller (OCIDEC-2) ----`
5			`---- ----`
6			`---- Author: Richard Herveille ----`
7			`---- richard@asics.ws ----`
8			`---- www.asics.ws ----`
9			`---- ----`
10			`---------------------------------------------------------------------`
11			`---- ----`
12			`---- Copyright (C) 2001, 2002 Richard Herveille ----`
13			`---- richard@asics.ws ----`
14			`---- ----`
15			`---- This source file may be used and distributed without ----`
16			`---- restriction provided that this copyright statement is not ----`
17			`---- removed from the file and that any derivative work contains ----`
18			`---- the original copyright notice and the associated disclaimer.----`
19			`---- ----`
20			---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
21			`---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----`
22			`---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----`
23			`---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----`
24			`---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----`
25			`---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----`
26			`---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----`
27			`---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----`
28			`---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----`
29			`---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----`
30			`---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----`
31			`---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----`
32			`---- POSSIBILITY OF SUCH DAMAGE. ----`
33			`---- ----`
34			`---------------------------------------------------------------------`
35
36			`-- rev.: 1.0 march 18th, 2001. Initial release`
37			`-- rev.: 1.0a april 12th, 2001. Removed references to records.vhd`
38			`-- rev.: 1.1 june 18th, 2001. Changed PIOack generation. Avoid asserting PIOack continuously when IDEen = '0'`
39			`-- rev.: 1.2 june 26th, 2001. Changed dPIOreq generation. Core did not support wishbone burst accesses to ATA-device.`
40			`-- rev.: 1.3 july 11th, 2001. Changed PIOreq & PIOack generation (made them synchronous).`
41			`--`
42			`-- CVS Log`
43			`--`
44			`-- $Id: atahost_controller.vhd,v 1.2 2002/05/19 06:07:09 rherveille Exp $`
45			`--`
46			`-- $Date: 2002/05/19 06:07:09 $`
47			`-- $Revision: 1.2 $`
48			`-- $Author: rherveille $`
49			`-- $Locker: $`
50			`-- $State: Exp $`
51			`--`
52			`-- Change History:`
53			`-- $Log: atahost_controller.vhd,v $`
54			`-- Revision 1.2 2002/05/19 06:07:09 rherveille`
55			`-- Fixed a potential bug where the core was forced into an unknown state`
56			`-- when an asynchronous reset was given without a running clock.`
57			`--`
58			`--`
59
60			`--`
61			`-- OCIDEC2 supports:`
62			`-- -Common Compatible timing access to all connected devices`
63			`-- -Separate timing accesses to data port`
64			`-- -No DMA support`
65
66			`library ieee;`
67			`use ieee.std_logic_1164.all;`
68			`use ieee.numeric_std.all;`
69
70			`entity ocidec2_controller is`
71			`generic(`
72			`TWIDTH : natural := 8; -- counter width`
73
74			`-- PIO mode 0 settings (@100MHz clock)`
75			`PIO_mode0_T1 : natural := 6; -- 70ns`
76			`PIO_mode0_T2 : natural := 28; -- 290ns`
77			`PIO_mode0_T4 : natural := 2; -- 30ns`
78			`PIO_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240`
79			`);`
80			`port(`
81			`clk : in std_logic; -- master clock in`
82			`nReset : in std_logic := '1'; -- asynchronous active low reset`
83			`rst : in std_logic := '0'; -- synchronous active high reset`
84
85			`irq : out std_logic; -- interrupt request signal`
86
87			`-- control / registers`
88			`IDEctrl_rst,`
89			`IDEctrl_IDEen,`
90			`IDEctrl_FATR0,`
91			`IDEctrl_FATR1 : in std_logic;`
92
93			`-- PIO registers`
94			`cmdport_T1,`
95			`cmdport_T2,`
96			`cmdport_T4,`
97			`cmdport_Teoc : in std_logic_vector(7 downto 0);`
98			`cmdport_IORDYen : in std_logic; -- PIO command port / non-fast timing`
99
100			`dport0_T1,`
101			`dport0_T2,`
102			`dport0_T4,`
103			`dport0_Teoc : in std_logic_vector(7 downto 0);`
104			`dport0_IORDYen : in std_logic; -- PIO mode data-port / fast timing device 0`
105
106			`dport1_T1,`
107			`dport1_T2,`
108			`dport1_T4,`
109			`dport1_Teoc : in std_logic_vector(7 downto 0);`
110			`dport1_IORDYen : in std_logic; -- PIO mode data-port / fast timing device 1`
111
112			`PIOreq : in std_logic; -- PIO transfer request`
113			`PIOack : out std_logic; -- PIO transfer ended`
114			`PIOa : in std_logic_vector(3 downto 0); -- PIO address`
115			`PIOd : in std_logic_vector(15 downto 0); -- PIO data in`
116			`PIOq : out std_logic_vector(15 downto 0); -- PIO data out`
117			`PIOwe : in std_logic; -- PIO direction bit '1'=write, '0'=read`
118
119			`-- ATA signals`
120			`RESETn : out std_logic;`
121			`DDi : in std_logic_vector(15 downto 0);`
122			`DDo : out std_logic_vector(15 downto 0);`
123			`DDoe : out std_logic;`
124			`DA : out std_logic_vector(2 downto 0);`
125			`CS0n : out std_logic;`
126			`CS1n : out std_logic;`
127
128			`DIORn : out std_logic;`
129			`DIOWn : out std_logic;`
130			`IORDY : in std_logic;`
131			`INTRQ : in std_logic`
132			`);`
133			`end entity ocidec2_controller;`
134
135			`architecture structural of ocidec2_controller is`
136			`--`
137			`-- component declarations`
138			`--`
139			`component atahost_pio_actrl is`
140			`generic(`
141			`TWIDTH : natural := 8; -- counter width`
142
143			`-- PIO mode 0 settings (@100MHz clock)`
144			`PIO_mode0_T1 : natural := 6; -- 70ns`
145			`PIO_mode0_T2 : natural := 28; -- 290ns`
146			`PIO_mode0_T4 : natural := 2; -- 30ns`
147			`PIO_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240`
148			`);`
149			`port(`
150			`clk : in std_logic; -- master clock`
151			`nReset : in std_logic; -- asynchronous active low reset`
152			`rst : in std_logic; -- synchronous active high reset`
153
154			`IDEctrl_FATR0,`
155			`IDEctrl_FATR1 : in std_logic;`
156
157			`cmdport_T1,`
158			`cmdport_T2,`
159			`cmdport_T4,`
160			`cmdport_Teoc : in std_logic_vector(7 downto 0);`
161			`cmdport_IORDYen : in std_logic; -- PIO command port / non-fast timing`
162
163			`dport0_T1,`
164			`dport0_T2,`
165			`dport0_T4,`
166			`dport0_Teoc : in std_logic_vector(7 downto 0);`
167			`dport0_IORDYen : in std_logic; -- PIO mode data-port / fast timing device 0`
168
169			`dport1_T1,`
170			`dport1_T2,`
171			`dport1_T4,`
172			`dport1_Teoc : in std_logic_vector(7 downto 0);`
173			`dport1_IORDYen : in std_logic; -- PIO mode data-port / fast timing device 1`
174
175			`SelDev : in std_logic; -- Selected device`
176
177			`go : in std_logic; -- Start transfer sequence`
178			`done : out std_logic; -- Transfer sequence done`
179			`dir : in std_logic; -- Transfer direction '1'=write, '0'=read`
180			`a : in std_logic_vector(3 downto 0); -- PIO transfer address`
181			`q : out std_logic_vector(15 downto 0); -- Data read from ATA devices`
182
183			`DDi : in std_logic_vector(15 downto 0); -- Data from ATA DD bus`
184			`oe : out std_logic; -- DDbus output-enable signal`
185
186			`DIOR,`
187			`DIOW : out std_logic;`
188			`IORDY : in std_logic`
189			`);`
190			`end component;`
191
192			`--`
193			`-- signals`
194			`--`
195			`signal SelDev : std_logic; -- selected device`
196
197			`signal dPIOreq, PIOgo : std_logic; -- start PIO timing controller`
198			`signal PIOdone : std_logic; -- PIO timing controller done`
199
200			`-- PIO signals`
201			`signal PIOdior, PIOdiow : std_logic;`
202			`signal PIOoe : std_logic;`
203			`signal rPIOack : std_logic;`
204			`-- synchronized ATA inputs`
205			`signal sIORDY : std_logic;`
206
207			`begin`
208
209			`--`
210			`-- synchronize incoming signals`
211			`--`
212			`synch_incoming: block`
213			`signal cIORDY : std_logic; -- capture IORDY`
214			`signal cINTRQ : std_logic; -- capture INTRQ`
215			`begin`
216			`process(clk)`
217			`begin`
218			`if (clk'event and clk = '1') then`
219			`cIORDY <= IORDY;`
220			`cINTRQ <= INTRQ;`
221
222			`sIORDY <= cIORDY;`
223			`irq <= cINTRQ;`
224			`end if;`
225			`end process;`
226			`end block synch_incoming;`
227
228			`--`
229			`-- generate ATA signals`
230			`--`
231			`gen_ata_sigs: block`
232			`begin`
233			`-- generate registers for ATA signals`
234			`gen_regs: process(clk, nReset)`
235			`begin`
236			`if (nReset = '0') then`
237			`RESETn <= '0';`
238			`DIORn <= '1';`
239			`DIOWn <= '1';`
240			`DA <= (others => '0');`
241			`CS0n <= '1';`
242			`CS1n <= '1';`
243			`DDo <= (others => '0');`
244			`DDoe <= '0';`
245			`elsif (clk'event and clk = '1') then`
246			`if (rst = '1') then`
247			`RESETn <= '0';`
248			`DIORn <= '1';`
249			`DIOWn <= '1';`
250			`DA <= (others => '0');`
251			`CS0n <= '1';`
252			`CS1n <= '1';`
253			`DDo <= (others => '0');`
254			`DDoe <= '0';`
255			`else`
256			`RESETn <= not IDEctrl_rst;`
257			`DA <= PIOa(2 downto 0);`
258			`CS0n <= not (not PIOa(3) and PIOreq); -- CS0 asserted when A(3) = '0'`
259			`CS1n <= not ( PIOa(3) and PIOreq); -- CS1 asserted when A(3) = '1'`
260
261			`DDo <= PIOd;`
262			`DDoe <= PIOoe;`
263			`DIORn <= not PIOdior;`
264			`DIOWn <= not PIOdiow;`
265			`end if;`
266			`end if;`
267			`end process gen_regs;`
268			`end block gen_ata_sigs;`
269
270			`--`
271			`-- generate selected device`
272			`--`
273			`gen_seldev: process(clk)`
274			`variable Asel : std_logic; -- address selected`
275			`begin`
276			`if (clk'event and clk = '1') then`
277			`Asel := not PIOa(3) and PIOa(2) and PIOa(1) and not PIOa(0); -- header/device register`
278			`if ( (PIOdone = '1') and (Asel = '1') and (PIOwe = '1') ) then`
279			`SelDev <= PIOd(4);`
280			`end if;`
281			`end if;`
282			`end process gen_seldev;`
283
284			`-- generate PIOgo signal`
285			`gen_PIOgo: process(clk, nReset)`
286			`begin`
287			`if (nReset = '0') then`
288			`dPIOreq <= '0';`
289			`PIOgo <= '0';`
290			`elsif (clk'event and clk = '1') then`
291			`if (rst = '1') then`
292			`dPIOreq <= '0';`
293			`PIOgo <= '0';`
294			`else`
295			`dPIOreq <= PIOreq and not rPIOack;`
296			`PIOgo <= (PIOreq and not dPIOreq) and IDEctrl_IDEen;`
297			`end if;`
298			`end if;`
299			`end process gen_PIOgo;`
300			`--`
301			`-- Hookup PIO access controller`
302			`--`
303			`pio_access_control: atahost_pio_actrl`
304			`generic map(`
305			`TWIDTH => TWIDTH,`
306			`PIO_mode0_T1 => PIO_mode0_T1,`
307			`PIO_mode0_T2 => PIO_mode0_T2,`
308			`PIO_mode0_T4 => PIO_mode0_T4,`
309			`PIO_mode0_Teoc => PIO_mode0_Teoc`
310			`)`
311			`port map(`
312			`clk => clk,`
313			`nReset => nReset,`
314			`rst => rst,`
315			`IDEctrl_FATR0 => IDEctrl_FATR0,`
316			`IDEctrl_FATR1 => IDEctrl_FATR1,`
317			`cmdport_T1 => cmdport_T1,`
318			`cmdport_T2 => cmdport_T2,`
319			`cmdport_T4 => cmdport_T4,`
320			`cmdport_Teoc => cmdport_Teoc,`
321			`cmdport_IORDYen => cmdport_IORDYen,`
322			`dport0_T1 => dport0_T1,`
323			`dport0_T2 => dport0_T2,`
324			`dport0_T4 => dport0_T4,`
325			`dport0_Teoc => dport0_Teoc,`
326			`dport0_IORDYen => dport0_IORDYen,`
327			`dport1_T1 => dport1_T1,`
328			`dport1_T2 => dport1_T2,`
329			`dport1_T4 => dport1_T4,`
330			`dport1_Teoc => dport1_Teoc,`
331			`dport1_IORDYen => dport1_IORDYen,`
332			`SelDev => SelDev,`
333			`go => PIOgo,`
334			`done => PIOdone,`
335			`dir => PIOwe,`
336			`a => PIOa,`
337			`q => PIOq,`
338			`DDi => DDi,`
339			`oe => PIOoe,`
340			`DIOR => PIOdior,`
341			`DIOW => PIOdiow,`
342			`IORDY => sIORDY`
343			`);`
344
345			`-- generate acknowledge`
346			`gen_ack: process(clk)`
347			`begin`
348			`if (clk'event and clk = '1') then`
349			`rPIOack <= PIOdone or (PIOreq and not IDEctrl_IDEen); -- acknowledge when done or when IDE not enabled (discard request)`
350			`end if;`
351			`PIOack <= rPIOack;`
352			`end process gen_ack;`
353			`end architecture structural;`
354