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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [lib/] [opencores/] [ata/] [ro_cnt.vhd] - Blame information for rev 2

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---------------------------------------------------------------------
----                                                             ----
----  Run-Once Counter                                           ----
----                                                             ----
----  Author: Richard Herveille                                  ----
----          richard@asics.ws                                   ----
----          www.asics.ws                                       ----
----                                                             ----
---------------------------------------------------------------------
----                                                             ----
---- Copyright (C) 2001, 2002 Richard Herveille                  ----
----                          richard@asics.ws                   ----
----                                                             ----
---- This source file may be used and distributed without        ----
---- restriction provided that this copyright statement is not   ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
----                                                             ----
----     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ----
---- LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ----
---- POSSIBILITY OF SUCH DAMAGE.                                 ----
----                                                             ----
---------------------------------------------------------------------
 
--
--  CVS Log
--
--  $Id: ro_cnt.vhd,v 1.1 2002/03/01 03:49:03 rherveille Exp $
--
--  $Date: 2002/03/01 03:49:03 $
--  $Revision: 1.1 $
--  $Author: rherveille $
--  $Locker:  $
--  $State: Exp $
--
-- Change History:
--               $Log: ro_cnt.vhd,v $
--               Revision 1.1  2002/03/01 03:49:03  rherveille
--               Changed internal counter libraries.
--               Split counter.vhd into separate files.
--               Core is in same state as Verilog version now.
--
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
entity ro_cnt is
        generic(
                SIZE : natural := 8;
                UD   : integer := 0; -- default count down
                ID   : natural := 0      -- initial data after reset
        );
        port(
                clk    : in  std_logic;                  -- master clock
                nReset : in  std_logic := '1';           -- asynchronous active low reset
                rst    : in  std_logic := '0';           -- synchronous active high reset
 
                cnt_en : in  std_logic := '1';           -- count enable
                go     : in  std_logic;                  -- load counter and start sequence
                done   : out std_logic;                  -- done counting
                d      : in  std_logic_vector(SIZE -1 downto 0); -- load counter value
                q      : out std_logic_vector(SIZE -1 downto 0)  -- current counter value
        );
end entity ro_cnt;
 
architecture structural of ro_cnt is
        component ud_cnt is
        generic(
                SIZE : natural := 8;
                RESD : natural := 0      -- initial data after reset
        );
        port(
                clk    : in  std_logic;                  -- master clock
                nReset : in  std_logic := '1';           -- asynchronous active low reset
                rst    : in  std_logic := '0';           -- synchronous active high reset
 
                cnt_en : in  std_logic := '1';           -- count enable
                ud     : in  std_logic := '0';           -- up / not down
                nld    : in  std_logic := '1';           -- synchronous active low load
                d      : in  std_logic_vector(SIZE -1 downto 0); -- load counter value
                q      : out std_logic_vector(SIZE -1 downto 0); -- current counter value
 
                rci    : in  std_logic := '1';           -- carry input
                rco    : out std_logic                   -- carry output
        );
        end component ud_cnt;
 
        signal rci, rco, nld, UDP : std_logic;
begin
        gen_ctrl: process(clk, nReset)
        begin
                if (nReset = '0') then
                        rci <= '0';
                elsif (clk'event and clk = '1') then
                        if (rst = '1') then
                                rci <= '0';
                        else
                                rci <= go or (rci and not rco);
                        end if;
                end if;
        end process;
 
        nld <= not go;
 
        UDP <= '0' when UD = 0 else '1';
        -- hookup counter
        cnt : ud_cnt
                generic map (
                        SIZE => SIZE,
                        RESD => ID
                )
                port map (
                        clk => clk,
                        nReset => nReset,
                        rst => rst,
                        cnt_en => cnt_en,
                        ud => UDP,
                        nld => nld,
                        D => D,
                        Q => Q,
                        rci => rci,
                        rco => rco
                );
 
        done <= rco;
end architecture structural;

Line No.	Rev	Author	Line
1	2	dimamali	`---------------------------------------------------------------------`
2			`---- ----`
3			`---- Run-Once Counter ----`
4			`---- ----`
5			`---- Author: Richard Herveille ----`
6			`---- richard@asics.ws ----`
7			`---- www.asics.ws ----`
8			`---- ----`
9			`---------------------------------------------------------------------`
10			`---- ----`
11			`---- Copyright (C) 2001, 2002 Richard Herveille ----`
12			`---- richard@asics.ws ----`
13			`---- ----`
14			`---- This source file may be used and distributed without ----`
15			`---- restriction provided that this copyright statement is not ----`
16			`---- removed from the file and that any derivative work contains ----`
17			`---- the original copyright notice and the associated disclaimer.----`
18			`---- ----`
19			---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
20			`---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----`
21			`---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----`
22			`---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----`
23			`---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----`
24			`---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----`
25			`---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----`
26			`---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----`
27			`---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----`
28			`---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----`
29			`---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----`
30			`---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----`
31			`---- POSSIBILITY OF SUCH DAMAGE. ----`
32			`---- ----`
33			`---------------------------------------------------------------------`
34
35			`--`
36			`-- CVS Log`
37			`--`
38			`-- $Id: ro_cnt.vhd,v 1.1 2002/03/01 03:49:03 rherveille Exp $`
39			`--`
40			`-- $Date: 2002/03/01 03:49:03 $`
41			`-- $Revision: 1.1 $`
42			`-- $Author: rherveille $`
43			`-- $Locker: $`
44			`-- $State: Exp $`
45			`--`
46			`-- Change History:`
47			`-- $Log: ro_cnt.vhd,v $`
48			`-- Revision 1.1 2002/03/01 03:49:03 rherveille`
49			`-- Changed internal counter libraries.`
50			`-- Split counter.vhd into separate files.`
51			`-- Core is in same state as Verilog version now.`
52			`--`
53
54			`library ieee;`
55			`use ieee.std_logic_1164.all;`
56			`use ieee.numeric_std.all;`
57
58			`entity ro_cnt is`
59			`generic(`
60			`SIZE : natural := 8;`
61			`UD : integer := 0; -- default count down`
62			`ID : natural := 0 -- initial data after reset`
63			`);`
64			`port(`
65			`clk : in std_logic; -- master clock`
66			`nReset : in std_logic := '1'; -- asynchronous active low reset`
67			`rst : in std_logic := '0'; -- synchronous active high reset`
68
69			`cnt_en : in std_logic := '1'; -- count enable`
70			`go : in std_logic; -- load counter and start sequence`
71			`done : out std_logic; -- done counting`
72			`d : in std_logic_vector(SIZE -1 downto 0); -- load counter value`
73			`q : out std_logic_vector(SIZE -1 downto 0) -- current counter value`
74			`);`
75			`end entity ro_cnt;`
76
77			`architecture structural of ro_cnt is`
78			`component ud_cnt is`
79			`generic(`
80			`SIZE : natural := 8;`
81			`RESD : natural := 0 -- initial data after reset`
82			`);`
83			`port(`
84			`clk : in std_logic; -- master clock`
85			`nReset : in std_logic := '1'; -- asynchronous active low reset`
86			`rst : in std_logic := '0'; -- synchronous active high reset`
87
88			`cnt_en : in std_logic := '1'; -- count enable`
89			`ud : in std_logic := '0'; -- up / not down`
90			`nld : in std_logic := '1'; -- synchronous active low load`
91			`d : in std_logic_vector(SIZE -1 downto 0); -- load counter value`
92			`q : out std_logic_vector(SIZE -1 downto 0); -- current counter value`
93
94			`rci : in std_logic := '1'; -- carry input`
95			`rco : out std_logic -- carry output`
96			`);`
97			`end component ud_cnt;`
98
99			`signal rci, rco, nld, UDP : std_logic;`
100			`begin`
101			`gen_ctrl: process(clk, nReset)`
102			`begin`
103			`if (nReset = '0') then`
104			`rci <= '0';`
105			`elsif (clk'event and clk = '1') then`
106			`if (rst = '1') then`
107			`rci <= '0';`
108			`else`
109			`rci <= go or (rci and not rco);`
110			`end if;`
111			`end if;`
112			`end process;`
113
114			`nld <= not go;`
115
116			`UDP <= '0' when UD = 0 else '1';`
117			`-- hookup counter`
118			`cnt : ud_cnt`
119			`generic map (`
120			`SIZE => SIZE,`
121			`RESD => ID`
122			`)`
123			`port map (`
124			`clk => clk,`
125			`nReset => nReset,`
126			`rst => rst,`
127			`cnt_en => cnt_en,`
128			`ud => UDP,`
129			`nld => nld,`
130			`D => D,`
131			`Q => Q,`
132			`rci => rci,`
133			`rco => rco`
134			`);`
135
136			`done <= rco;`
137			`end architecture structural;`

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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [lib/] [opencores/] [ata/] [ro_cnt.vhd] - Blame information for rev 2