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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [lib/] [techmap/] [axcelerator/] [grspwc_axcelerator.vhd] - Blame information for rev 2

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------------------------------------------------------------------------------
--  This file is a part of the GRLIB VHDL IP LIBRARY
--  Copyright (C) 2003, Gaisler Research
--
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License as published by
--  the Free Software Foundation; either version 2 of the License, or
--  (at your option) any later version.
--
--  This program is distributed in the hope that it will be useful,
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--  GNU General Public License for more details.
--
--  You should have received a copy of the GNU General Public License
--  along with this program; if not, write to the Free Software
--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
-----------------------------------------------------------------------------
-- Entity:      grspwc_axcelerator
-- File:        grspwc_axcelerator.vhd
-- Author:      Jiri Gaisler - Gaisler Research 
-- Description: tech wrapper for axcelerator grspwc netlist
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library axcelerator;
use axcelerator.all;
 
entity grspwc_axcelerator is
  generic(
    sysfreq      : integer := 40000;
    usegen       : integer range 0 to 1  := 1;
    nsync        : integer range 1 to 2  := 1;
    rmap         : integer range 0 to 1  := 0;
    rmapcrc      : integer range 0 to 1  := 0;
    fifosize1    : integer range 4 to 32 := 16;
    fifosize2    : integer range 16 to 64 := 16;
    rxunaligned  : integer range 0 to 1 := 0;
    rmapbufs     : integer range 2 to 8 := 4;
    scantest     : integer range 0 to 1 := 0
  );
  port(
    rst          : in  std_ulogic;
    clk          : in  std_ulogic;
    txclk        : in  std_ulogic;
    --ahb mst in
    hgrant       : in  std_ulogic;
    hready       : in  std_ulogic;
    hresp        : in  std_logic_vector(1 downto 0);
    hrdata       : in  std_logic_vector(31 downto 0);
    --ahb mst out
    hbusreq      : out  std_ulogic;
    hlock        : out  std_ulogic;
    htrans       : out  std_logic_vector(1 downto 0);
    haddr        : out  std_logic_vector(31 downto 0);
    hwrite       : out  std_ulogic;
    hsize        : out  std_logic_vector(2 downto 0);
    hburst       : out  std_logic_vector(2 downto 0);
    hprot        : out  std_logic_vector(3 downto 0);
    hwdata       : out  std_logic_vector(31 downto 0);
    --apb slv in 
    psel         : in   std_ulogic;
    penable      : in   std_ulogic;
    paddr        : in   std_logic_vector(31 downto 0);
    pwrite       : in   std_ulogic;
    pwdata       : in   std_logic_vector(31 downto 0);
    --apb slv out
    prdata       : out  std_logic_vector(31 downto 0);
    --spw in
    di : in std_logic_vector(1 downto 0);
    si : in std_logic_vector(1 downto 0);
    --spw out
    do : out std_logic_vector(1 downto 0);
    so : out std_logic_vector(1 downto 0);
    --time iface
    tickin       : in   std_ulogic;
    tickout      : out  std_ulogic;
    --irq
    irq          : out  std_logic;
    --misc     
    clkdiv10     : in   std_logic_vector(7 downto 0);
    dcrstval     : in   std_logic_vector(9 downto 0);
    timerrstval  : in   std_logic_vector(11 downto 0);
    --rmapen
    rmapen       : in   std_ulogic;
    --clk bufs
    rxclki : in std_logic_vector(1 downto 0);
    nrxclki : in std_logic_vector(1 downto 0);
    rxclko : out std_logic_vector(1 downto 0);
 
    --rx ahb fifo
    rxrenable    : out  std_ulogic;
    rxraddress   : out  std_logic_vector(4 downto 0);
    rxwrite      : out  std_ulogic;
    rxwdata      : out  std_logic_vector(31 downto 0);
    rxwaddress   : out  std_logic_vector(4 downto 0);
    rxrdata      : in   std_logic_vector(31 downto 0);
    --tx ahb fifo
    txrenable    : out  std_ulogic;
    txraddress   : out  std_logic_vector(4 downto 0);
    txwrite      : out  std_ulogic;
    txwdata      : out  std_logic_vector(31 downto 0);
    txwaddress   : out  std_logic_vector(4 downto 0);
    txrdata      : in   std_logic_vector(31 downto 0);
    --nchar fifo
    ncrenable    : out  std_ulogic;
    ncraddress   : out  std_logic_vector(5 downto 0);
    ncwrite      : out  std_ulogic;
    ncwdata      : out  std_logic_vector(8 downto 0);
    ncwaddress   : out  std_logic_vector(5 downto 0);
    ncrdata      : in   std_logic_vector(8 downto 0);
    --rmap buf
    rmrenable    : out  std_ulogic;
    rmraddress   : out  std_logic_vector(7 downto 0);
    rmwrite      : out  std_ulogic;
    rmwdata      : out  std_logic_vector(7 downto 0);
    rmwaddress   : out  std_logic_vector(7 downto 0);
    rmrdata      : in   std_logic_vector(7 downto 0);
    linkdis      : out  std_ulogic;
    testclk      : in   std_ulogic := '0';
    testrst      : in   std_ulogic := '0';
    testen       : in   std_ulogic := '0'
  );
end entity;
 
architecture rtl of grspwc_axcelerator is
 
component grspwc_axcelerator_16_16_rmap0_crc1 is
port(
 rst :  in std_logic;
  clk :  in std_logic;
  txclk :  in std_logic;
  hgrant :  in std_logic;
  hready :  in std_logic;
  hresp : in std_logic_vector(1 downto 0);
  hrdata : in std_logic_vector(31 downto 0);
  hbusreq :  out std_logic;
  hlock :  out std_logic;
  htrans : out std_logic_vector(1 downto 0);
  haddr : out std_logic_vector(31 downto 0);
  hwrite :  out std_logic;
  hsize : out std_logic_vector(2 downto 0);
  hburst : out std_logic_vector(2 downto 0);
  hprot : out std_logic_vector(3 downto 0);
  hwdata : out std_logic_vector(31 downto 0);
  psel :  in std_logic;
  penable :  in std_logic;
  paddr : in std_logic_vector(31 downto 0);
  pwrite :  in std_logic;
  pwdata : in std_logic_vector(31 downto 0);
  prdata : out std_logic_vector(31 downto 0);
  di : in std_logic_vector(1 downto 0);
  si : in std_logic_vector(1 downto 0);
  do : out std_logic_vector(1 downto 0);
  so : out std_logic_vector(1 downto 0);
  tickin :  in std_logic;
  tickout :  out std_logic;
  irq :  out std_logic;
  clkdiv10 : in std_logic_vector(7 downto 0);
  dcrstval : in std_logic_vector(9 downto 0);
  timerrstval : in std_logic_vector(11 downto 0);
  rmapen :  in std_logic;
  rxclki : in std_logic_vector(1 downto 0);
  nrxclki : in std_logic_vector(1 downto 0);
  rxclko : out std_logic_vector(1 downto 0);
  rxrenable :  out std_logic;
  rxraddress : out std_logic_vector(4 downto 0);
  rxwrite :  out std_logic;
  rxwdata : out std_logic_vector(31 downto 0);
  rxwaddress : out std_logic_vector(4 downto 0);
  rxrdata : in std_logic_vector(31 downto 0);
  txrenable :  out std_logic;
  txraddress : out std_logic_vector(4 downto 0);
  txwrite :  out std_logic;
  txwdata : out std_logic_vector(31 downto 0);
  txwaddress : out std_logic_vector(4 downto 0);
  txrdata : in std_logic_vector(31 downto 0);
  ncrenable :  out std_logic;
  ncraddress : out std_logic_vector(5 downto 0);
  ncwrite :  out std_logic;
  ncwdata : out std_logic_vector(8 downto 0);
  ncwaddress : out std_logic_vector(5 downto 0);
  ncrdata : in std_logic_vector(8 downto 0);
  rmrenable :  out std_logic;
  rmraddress : out std_logic_vector(7 downto 0);
  rmwrite :  out std_logic;
  rmwdata : out std_logic_vector(7 downto 0);
  rmwaddress : out std_logic_vector(7 downto 0);
  rmrdata : in std_logic_vector(7 downto 0);
  linkdis :  out std_logic;
  testclk :  in std_logic;
  testrst :  in std_logic;
  testen :  in std_logic);
end component;
 
component grspwc_axcelerator_16_16_rmap8_crc1 is
port(
 rst :  in std_logic;
  clk :  in std_logic;
  txclk :  in std_logic;
  hgrant :  in std_logic;
  hready :  in std_logic;
  hresp : in std_logic_vector(1 downto 0);
  hrdata : in std_logic_vector(31 downto 0);
  hbusreq :  out std_logic;
  hlock :  out std_logic;
  htrans : out std_logic_vector(1 downto 0);
  haddr : out std_logic_vector(31 downto 0);
  hwrite :  out std_logic;
  hsize : out std_logic_vector(2 downto 0);
  hburst : out std_logic_vector(2 downto 0);
  hprot : out std_logic_vector(3 downto 0);
  hwdata : out std_logic_vector(31 downto 0);
  psel :  in std_logic;
  penable :  in std_logic;
  paddr : in std_logic_vector(31 downto 0);
  pwrite :  in std_logic;
  pwdata : in std_logic_vector(31 downto 0);
  prdata : out std_logic_vector(31 downto 0);
  di : in std_logic_vector(1 downto 0);
  si : in std_logic_vector(1 downto 0);
  do : out std_logic_vector(1 downto 0);
  so : out std_logic_vector(1 downto 0);
  tickin :  in std_logic;
  tickout :  out std_logic;
  irq :  out std_logic;
  clkdiv10 : in std_logic_vector(7 downto 0);
  dcrstval : in std_logic_vector(9 downto 0);
  timerrstval : in std_logic_vector(11 downto 0);
  rmapen :  in std_logic;
  rxclki : in std_logic_vector(1 downto 0);
  nrxclki : in std_logic_vector(1 downto 0);
  rxclko : out std_logic_vector(1 downto 0);
  rxrenable :  out std_logic;
  rxraddress : out std_logic_vector(4 downto 0);
  rxwrite :  out std_logic;
  rxwdata : out std_logic_vector(31 downto 0);
  rxwaddress : out std_logic_vector(4 downto 0);
  rxrdata : in std_logic_vector(31 downto 0);
  txrenable :  out std_logic;
  txraddress : out std_logic_vector(4 downto 0);
  txwrite :  out std_logic;
  txwdata : out std_logic_vector(31 downto 0);
  txwaddress : out std_logic_vector(4 downto 0);
  txrdata : in std_logic_vector(31 downto 0);
  ncrenable :  out std_logic;
  ncraddress : out std_logic_vector(5 downto 0);
  ncwrite :  out std_logic;
  ncwdata : out std_logic_vector(8 downto 0);
  ncwaddress : out std_logic_vector(5 downto 0);
  ncrdata : in std_logic_vector(8 downto 0);
  rmrenable :  out std_logic;
  rmraddress : out std_logic_vector(7 downto 0);
  rmwrite :  out std_logic;
  rmwdata : out std_logic_vector(7 downto 0);
  rmwaddress : out std_logic_vector(7 downto 0);
  rmrdata : in std_logic_vector(7 downto 0);
  linkdis :  out std_logic;
  testclk :  in std_logic;
  testrst :  in std_logic;
  testen :  in std_logic);
end component;
 
component grspwc_axcelerator_16_16_rmap0_crc0 is
port(
  rst :  in std_logic;
  clk :  in std_logic;
  txclk :  in std_logic;
  hgrant :  in std_logic;
  hready :  in std_logic;
  hresp : in std_logic_vector (1 downto 0);
  hrdata : in std_logic_vector (31 downto 0);
  hbusreq :  out std_logic;
  hlock :  out std_logic;
  htrans : out std_logic_vector (1 downto 0);
  haddr : out std_logic_vector (31 downto 0);
  hwrite :  out std_logic;
  hsize : out std_logic_vector (2 downto 0);
  hburst : out std_logic_vector (2 downto 0);
  hprot : out std_logic_vector (3 downto 0);
  hwdata : out std_logic_vector (31 downto 0);
  psel :  in std_logic;
  penable :  in std_logic;
  paddr : in std_logic_vector (31 downto 0);
  pwrite :  in std_logic;
  pwdata : in std_logic_vector (31 downto 0);
  prdata : out std_logic_vector (31 downto 0);
  di : in std_logic_vector(1 downto 0);
  si : in std_logic_vector(1 downto 0);
  do : out std_logic_vector(1 downto 0);
  so : out std_logic_vector(1 downto 0);
  tickin :  in std_logic;
  tickout :  out std_logic;
  irq :  out std_logic;
  clkdiv10 : in std_logic_vector (7 downto 0);
  dcrstval : in std_logic_vector (9 downto 0);
  timerrstval : in std_logic_vector (11 downto 0);
  rmapen :  in std_logic;
  rxclki : in std_logic_vector(1 downto 0);
  nrxclki : in std_logic_vector(1 downto 0);
  rxclko : out std_logic_vector(1 downto 0);
  rxrenable :  out std_logic;
  rxraddress : out std_logic_vector (4 downto 0);
  rxwrite :  out std_logic;
  rxwdata : out std_logic_vector (31 downto 0);
  rxwaddress : out std_logic_vector (4 downto 0);
  rxrdata : in std_logic_vector (31 downto 0);
  txrenable :  out std_logic;
  txraddress : out std_logic_vector (4 downto 0);
  txwrite :  out std_logic;
  txwdata : out std_logic_vector (31 downto 0);
  txwaddress : out std_logic_vector (4 downto 0);
  txrdata : in std_logic_vector (31 downto 0);
  ncrenable :  out std_logic;
  ncraddress : out std_logic_vector (5 downto 0);
  ncwrite :  out std_logic;
  ncwdata : out std_logic_vector (8 downto 0);
  ncwaddress : out std_logic_vector (5 downto 0);
  ncrdata : in std_logic_vector (8 downto 0);
  rmrenable :  out std_logic;
  rmraddress : out std_logic_vector (7 downto 0);
  rmwrite :  out std_logic;
  rmwdata : out std_logic_vector (7 downto 0);
  rmwaddress : out std_logic_vector (7 downto 0);
  rmrdata : in std_logic_vector (7 downto 0);
  linkdis :  out std_logic;
  testclk :  in std_logic;
  testrst :  in std_logic;
  testen :  in std_logic);
end component;
 
begin
 
  hlock <= '0';
f16_16_crc1 : if (rmapcrc = 1) and (rmap = 0) and (fifosize1 = 16) and (fifosize2 = 16) generate
    grspwc0 : grspwc_axcelerator_16_16_rmap0_crc1
    port map(
      rst          => rst,
      clk          => clk,
      txclk        => txclk,
      --ahb mst in
      hgrant       => hgrant,
      hready       => hready,
      hresp        => hresp,
      hrdata       => hrdata,
      --ahb mst out
      hbusreq      => hbusreq,
      hlock        => open, --hlock,
      htrans       => htrans,
      haddr        => haddr,
      hwrite       => hwrite,
      hsize        => hsize,
      hburst       => hburst,
      hprot        => hprot,
      hwdata       => hwdata,
      --apb slv in 
      psel         => psel,
      penable      => penable,
      paddr        => paddr,
      pwrite       => pwrite,
      pwdata       => pwdata,
      --apb slv out
      prdata       => prdata,
      --spw in
      di           => di,
      si           => si,
      --spw out
      do           => do,
      so           => so,
      --time iface
      tickin       => tickin,
      tickout      => tickout,
      --clk bufs
      rxclki       => rxclki,
      nrxclki      => nrxclki,
      rxclko       => rxclko,
      --irq
      irq          => irq,
      --misc     
      clkdiv10     => clkdiv10,
      dcrstval     => dcrstval,
      timerrstval  => timerrstval,
      --rmapen    
      rmapen       => rmapen,
      --rx ahb fifo
      rxrenable    => rxrenable,
      rxraddress   => rxraddress,
      rxwrite      => rxwrite,
      rxwdata      => rxwdata,
      rxwaddress   => rxwaddress,
      rxrdata      => rxrdata,
      --tx ahb fifo
      txrenable    => txrenable,
      txraddress   => txraddress,
      txwrite      => txwrite,
      txwdata      => txwdata,
      txwaddress   => txwaddress,
      txrdata      => txrdata,
      --nchar fifo
      ncrenable    => ncrenable,
      ncraddress   => ncraddress,
      ncwrite      => ncwrite,
      ncwdata      => ncwdata,
      ncwaddress   => ncwaddress,
      ncrdata      => ncrdata,
      --rmap buf
      rmrenable    => rmrenable,
      rmraddress   => rmraddress,
      rmwrite      => rmwrite,
      rmwdata      => rmwdata,
      rmwaddress   => rmwaddress,
      rmrdata      => rmrdata,
      linkdis      => linkdis,
      testclk      => testclk,
      testrst      => testrst,
      testen       => testen
      );
end generate;
 
f16_16_rmap8_crc1 : if (rmapcrc = 1) and (rmap = 1) and (rmapbufs = 8) and (fifosize1 = 16) and (fifosize2 = 16)  generate
    grspwc0 : grspwc_axcelerator_16_16_rmap8_crc1
    port map(
      rst          => rst,
      clk          => clk,
      txclk        => txclk,
      --ahb mst in
      hgrant       => hgrant,
      hready       => hready,
      hresp        => hresp,
      hrdata       => hrdata,
      --ahb mst out
      hbusreq      => hbusreq,
      hlock        => open, --hlock,
      htrans       => htrans,
      haddr        => haddr,
      hwrite       => hwrite,
      hsize        => hsize,
      hburst       => hburst,
      hprot        => hprot,
      hwdata       => hwdata,
      --apb slv in 
      psel         => psel,
      penable      => penable,
      paddr        => paddr,
      pwrite       => pwrite,
      pwdata       => pwdata,
      --apb slv out
      prdata       => prdata,
      --spw in
      di           => di,
      si           => si,
      --spw out
      do           => do,
      so           => so,
      --time iface
      tickin       => tickin,
      tickout      => tickout,
      --clk bufs
      rxclki       => rxclki,
      nrxclki      => nrxclki,
      rxclko       => rxclko,
      --irq
      irq          => irq,
      --misc     
      clkdiv10     => clkdiv10,
      dcrstval     => dcrstval,
      timerrstval  => timerrstval,
      --rmapen    
      rmapen       => rmapen,
      --rx ahb fifo
      rxrenable    => rxrenable,
      rxraddress   => rxraddress,
      rxwrite      => rxwrite,
      rxwdata      => rxwdata,
      rxwaddress   => rxwaddress,
      rxrdata      => rxrdata,
      --tx ahb fifo
      txrenable    => txrenable,
      txraddress   => txraddress,
      txwrite      => txwrite,
      txwdata      => txwdata,
      txwaddress   => txwaddress,
      txrdata      => txrdata,
      --nchar fifo
      ncrenable    => ncrenable,
      ncraddress   => ncraddress,
      ncwrite      => ncwrite,
      ncwdata      => ncwdata,
      ncwaddress   => ncwaddress,
      ncrdata      => ncrdata,
      --rmap buf
      rmrenable    => rmrenable,
      rmraddress   => rmraddress,
      rmwrite      => rmwrite,
      rmwdata      => rmwdata,
      rmwaddress   => rmwaddress,
      rmrdata      => rmrdata,
      linkdis      => linkdis,
      testclk      => testclk,
      testrst      => testrst,
      testen       => testen
      );
end generate;
 
f16_16_crc0 : if (rmapcrc = 0) and (rmap = 0) and (fifosize1 = 16) and (fifosize2 = 16) generate
    grspwc0 : grspwc_axcelerator_16_16_rmap0_crc0
    port map(
      rst          => rst,
      clk          => clk,
      txclk        => txclk,
      --ahb mst in
      hgrant       => hgrant,
      hready       => hready,
      hresp        => hresp,
      hrdata       => hrdata,
      --ahb mst out
      hbusreq      => hbusreq,
      hlock        => open, --hlock,
      htrans       => htrans,
      haddr        => haddr,
      hwrite       => hwrite,
      hsize        => hsize,
      hburst       => hburst,
      hprot        => hprot,
      hwdata       => hwdata,
      --apb slv in 
      psel         => psel,
      penable      => penable,
      paddr        => paddr,
      pwrite       => pwrite,
      pwdata       => pwdata,
      --apb slv out
      prdata       => prdata,
      --spw in
      di           => di,
      si           => si,
      --spw out
      do           => do,
      so           => so,
      --time iface
      tickin       => tickin,
      tickout      => tickout,
      --clk bufs
      rxclki       => rxclki,
      nrxclki      => nrxclki,
      rxclko       => rxclko,
      --irq
      irq          => irq,
      --misc     
      clkdiv10     => clkdiv10,
      dcrstval     => dcrstval,
      timerrstval  => timerrstval,
      --rmapen    
      rmapen       => rmapen,
      --rx ahb fifo
      rxrenable    => rxrenable,
      rxraddress   => rxraddress,
      rxwrite      => rxwrite,
      rxwdata      => rxwdata,
      rxwaddress   => rxwaddress,
      rxrdata      => rxrdata,
      --tx ahb fifo
      txrenable    => txrenable,
      txraddress   => txraddress,
      txwrite      => txwrite,
      txwdata      => txwdata,
      txwaddress   => txwaddress,
      txrdata      => txrdata,
      --nchar fifo
      ncrenable    => ncrenable,
      ncraddress   => ncraddress,
      ncwrite      => ncwrite,
      ncwdata      => ncwdata,
      ncwaddress   => ncwaddress,
      ncrdata      => ncrdata,
      --rmap buf
      rmrenable    => rmrenable,
      rmraddress   => rmraddress,
      rmwrite      => rmwrite,
      rmwdata      => rmwdata,
      rmwaddress   => rmwaddress,
      rmrdata      => rmrdata,
      linkdis      => linkdis,
      testclk      => testclk,
      testrst      => testrst,
      testen       => testen
      );
end generate;
 
end architecture;

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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [lib/] [techmap/] [axcelerator/] [grspwc_axcelerator.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	dimamali	`------------------------------------------------------------------------------`
2			`-- This file is a part of the GRLIB VHDL IP LIBRARY`
3			`-- Copyright (C) 2003, Gaisler Research`
4			`--`
5			`-- This program is free software; you can redistribute it and/or modify`
6			`-- it under the terms of the GNU General Public License as published by`
7			`-- the Free Software Foundation; either version 2 of the License, or`
8			`-- (at your option) any later version.`
9			`--`
10			`-- This program is distributed in the hope that it will be useful,`
11			`-- but WITHOUT ANY WARRANTY; without even the implied warranty of`
12			`-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
13			`-- GNU General Public License for more details.`
14			`--`
15			`-- You should have received a copy of the GNU General Public License`
16			`-- along with this program; if not, write to the Free Software`
17			`-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA`
18			`-----------------------------------------------------------------------------`
19			`-- Entity: grspwc_axcelerator`
20			`-- File: grspwc_axcelerator.vhd`
21			`-- Author: Jiri Gaisler - Gaisler Research`
22			`-- Description: tech wrapper for axcelerator grspwc netlist`
23			`------------------------------------------------------------------------------`
24			`library ieee;`
25			`use ieee.std_logic_1164.all;`
26			`library axcelerator;`
27			`use axcelerator.all;`
28
29			`entity grspwc_axcelerator is`
30			`generic(`
31			`sysfreq : integer := 40000;`
32			`usegen : integer range 0 to 1 := 1;`
33			`nsync : integer range 1 to 2 := 1;`
34			`rmap : integer range 0 to 1 := 0;`
35			`rmapcrc : integer range 0 to 1 := 0;`
36			`fifosize1 : integer range 4 to 32 := 16;`
37			`fifosize2 : integer range 16 to 64 := 16;`
38			`rxunaligned : integer range 0 to 1 := 0;`
39			`rmapbufs : integer range 2 to 8 := 4;`
40			`scantest : integer range 0 to 1 := 0`
41			`);`
42			`port(`
43			`rst : in std_ulogic;`
44			`clk : in std_ulogic;`
45			`txclk : in std_ulogic;`
46			`--ahb mst in`
47			`hgrant : in std_ulogic;`
48			`hready : in std_ulogic;`
49			`hresp : in std_logic_vector(1 downto 0);`
50			`hrdata : in std_logic_vector(31 downto 0);`
51			`--ahb mst out`
52			`hbusreq : out std_ulogic;`
53			`hlock : out std_ulogic;`
54			`htrans : out std_logic_vector(1 downto 0);`
55			`haddr : out std_logic_vector(31 downto 0);`
56			`hwrite : out std_ulogic;`
57			`hsize : out std_logic_vector(2 downto 0);`
58			`hburst : out std_logic_vector(2 downto 0);`
59			`hprot : out std_logic_vector(3 downto 0);`
60			`hwdata : out std_logic_vector(31 downto 0);`
61			`--apb slv in`
62			`psel : in std_ulogic;`
63			`penable : in std_ulogic;`
64			`paddr : in std_logic_vector(31 downto 0);`
65			`pwrite : in std_ulogic;`
66			`pwdata : in std_logic_vector(31 downto 0);`
67			`--apb slv out`
68			`prdata : out std_logic_vector(31 downto 0);`
69			`--spw in`
70			`di : in std_logic_vector(1 downto 0);`
71			`si : in std_logic_vector(1 downto 0);`
72			`--spw out`
73			`do : out std_logic_vector(1 downto 0);`
74			`so : out std_logic_vector(1 downto 0);`
75			`--time iface`
76			`tickin : in std_ulogic;`
77			`tickout : out std_ulogic;`
78			`--irq`
79			`irq : out std_logic;`
80			`--misc`
81			`clkdiv10 : in std_logic_vector(7 downto 0);`
82			`dcrstval : in std_logic_vector(9 downto 0);`
83			`timerrstval : in std_logic_vector(11 downto 0);`
84			`--rmapen`
85			`rmapen : in std_ulogic;`
86			`--clk bufs`
87			`rxclki : in std_logic_vector(1 downto 0);`
88			`nrxclki : in std_logic_vector(1 downto 0);`
89			`rxclko : out std_logic_vector(1 downto 0);`
90
91			`--rx ahb fifo`
92			`rxrenable : out std_ulogic;`
93			`rxraddress : out std_logic_vector(4 downto 0);`
94			`rxwrite : out std_ulogic;`
95			`rxwdata : out std_logic_vector(31 downto 0);`
96			`rxwaddress : out std_logic_vector(4 downto 0);`
97			`rxrdata : in std_logic_vector(31 downto 0);`
98			`--tx ahb fifo`
99			`txrenable : out std_ulogic;`
100			`txraddress : out std_logic_vector(4 downto 0);`
101			`txwrite : out std_ulogic;`
102			`txwdata : out std_logic_vector(31 downto 0);`
103			`txwaddress : out std_logic_vector(4 downto 0);`
104			`txrdata : in std_logic_vector(31 downto 0);`
105			`--nchar fifo`
106			`ncrenable : out std_ulogic;`
107			`ncraddress : out std_logic_vector(5 downto 0);`
108			`ncwrite : out std_ulogic;`
109			`ncwdata : out std_logic_vector(8 downto 0);`
110			`ncwaddress : out std_logic_vector(5 downto 0);`
111			`ncrdata : in std_logic_vector(8 downto 0);`
112			`--rmap buf`
113			`rmrenable : out std_ulogic;`
114			`rmraddress : out std_logic_vector(7 downto 0);`
115			`rmwrite : out std_ulogic;`
116			`rmwdata : out std_logic_vector(7 downto 0);`
117			`rmwaddress : out std_logic_vector(7 downto 0);`
118			`rmrdata : in std_logic_vector(7 downto 0);`
119			`linkdis : out std_ulogic;`
120			`testclk : in std_ulogic := '0';`
121			`testrst : in std_ulogic := '0';`
122			`testen : in std_ulogic := '0'`
123			`);`
124			`end entity;`
125
126			`architecture rtl of grspwc_axcelerator is`
127
128			`component grspwc_axcelerator_16_16_rmap0_crc1 is`
129			`port(`
130			`rst : in std_logic;`
131			`clk : in std_logic;`
132			`txclk : in std_logic;`
133			`hgrant : in std_logic;`
134			`hready : in std_logic;`
135			`hresp : in std_logic_vector(1 downto 0);`
136			`hrdata : in std_logic_vector(31 downto 0);`
137			`hbusreq : out std_logic;`
138			`hlock : out std_logic;`
139			`htrans : out std_logic_vector(1 downto 0);`
140			`haddr : out std_logic_vector(31 downto 0);`
141			`hwrite : out std_logic;`
142			`hsize : out std_logic_vector(2 downto 0);`
143			`hburst : out std_logic_vector(2 downto 0);`
144			`hprot : out std_logic_vector(3 downto 0);`
145			`hwdata : out std_logic_vector(31 downto 0);`
146			`psel : in std_logic;`
147			`penable : in std_logic;`
148			`paddr : in std_logic_vector(31 downto 0);`
149			`pwrite : in std_logic;`
150			`pwdata : in std_logic_vector(31 downto 0);`
151			`prdata : out std_logic_vector(31 downto 0);`
152			`di : in std_logic_vector(1 downto 0);`
153			`si : in std_logic_vector(1 downto 0);`
154			`do : out std_logic_vector(1 downto 0);`
155			`so : out std_logic_vector(1 downto 0);`
156			`tickin : in std_logic;`
157			`tickout : out std_logic;`
158			`irq : out std_logic;`
159			`clkdiv10 : in std_logic_vector(7 downto 0);`
160			`dcrstval : in std_logic_vector(9 downto 0);`
161			`timerrstval : in std_logic_vector(11 downto 0);`
162			`rmapen : in std_logic;`
163			`rxclki : in std_logic_vector(1 downto 0);`
164			`nrxclki : in std_logic_vector(1 downto 0);`
165			`rxclko : out std_logic_vector(1 downto 0);`
166			`rxrenable : out std_logic;`
167			`rxraddress : out std_logic_vector(4 downto 0);`
168			`rxwrite : out std_logic;`
169			`rxwdata : out std_logic_vector(31 downto 0);`
170			`rxwaddress : out std_logic_vector(4 downto 0);`
171			`rxrdata : in std_logic_vector(31 downto 0);`
172			`txrenable : out std_logic;`
173			`txraddress : out std_logic_vector(4 downto 0);`
174			`txwrite : out std_logic;`
175			`txwdata : out std_logic_vector(31 downto 0);`
176			`txwaddress : out std_logic_vector(4 downto 0);`
177			`txrdata : in std_logic_vector(31 downto 0);`
178			`ncrenable : out std_logic;`
179			`ncraddress : out std_logic_vector(5 downto 0);`
180			`ncwrite : out std_logic;`
181			`ncwdata : out std_logic_vector(8 downto 0);`
182			`ncwaddress : out std_logic_vector(5 downto 0);`
183			`ncrdata : in std_logic_vector(8 downto 0);`
184			`rmrenable : out std_logic;`
185			`rmraddress : out std_logic_vector(7 downto 0);`
186			`rmwrite : out std_logic;`
187			`rmwdata : out std_logic_vector(7 downto 0);`
188			`rmwaddress : out std_logic_vector(7 downto 0);`
189			`rmrdata : in std_logic_vector(7 downto 0);`
190			`linkdis : out std_logic;`
191			`testclk : in std_logic;`
192			`testrst : in std_logic;`
193			`testen : in std_logic);`
194			`end component;`
195
196			`component grspwc_axcelerator_16_16_rmap8_crc1 is`
197			`port(`
198			`rst : in std_logic;`
199			`clk : in std_logic;`
200			`txclk : in std_logic;`
201			`hgrant : in std_logic;`
202			`hready : in std_logic;`
203			`hresp : in std_logic_vector(1 downto 0);`
204			`hrdata : in std_logic_vector(31 downto 0);`
205			`hbusreq : out std_logic;`
206			`hlock : out std_logic;`
207			`htrans : out std_logic_vector(1 downto 0);`
208			`haddr : out std_logic_vector(31 downto 0);`
209			`hwrite : out std_logic;`
210			`hsize : out std_logic_vector(2 downto 0);`
211			`hburst : out std_logic_vector(2 downto 0);`
212			`hprot : out std_logic_vector(3 downto 0);`
213			`hwdata : out std_logic_vector(31 downto 0);`
214			`psel : in std_logic;`
215			`penable : in std_logic;`
216			`paddr : in std_logic_vector(31 downto 0);`
217			`pwrite : in std_logic;`
218			`pwdata : in std_logic_vector(31 downto 0);`
219			`prdata : out std_logic_vector(31 downto 0);`
220			`di : in std_logic_vector(1 downto 0);`
221			`si : in std_logic_vector(1 downto 0);`
222			`do : out std_logic_vector(1 downto 0);`
223			`so : out std_logic_vector(1 downto 0);`
224			`tickin : in std_logic;`
225			`tickout : out std_logic;`
226			`irq : out std_logic;`
227			`clkdiv10 : in std_logic_vector(7 downto 0);`
228			`dcrstval : in std_logic_vector(9 downto 0);`
229			`timerrstval : in std_logic_vector(11 downto 0);`
230			`rmapen : in std_logic;`
231			`rxclki : in std_logic_vector(1 downto 0);`
232			`nrxclki : in std_logic_vector(1 downto 0);`
233			`rxclko : out std_logic_vector(1 downto 0);`
234			`rxrenable : out std_logic;`
235			`rxraddress : out std_logic_vector(4 downto 0);`
236			`rxwrite : out std_logic;`
237			`rxwdata : out std_logic_vector(31 downto 0);`
238			`rxwaddress : out std_logic_vector(4 downto 0);`
239			`rxrdata : in std_logic_vector(31 downto 0);`
240			`txrenable : out std_logic;`
241			`txraddress : out std_logic_vector(4 downto 0);`
242			`txwrite : out std_logic;`
243			`txwdata : out std_logic_vector(31 downto 0);`
244			`txwaddress : out std_logic_vector(4 downto 0);`
245			`txrdata : in std_logic_vector(31 downto 0);`
246			`ncrenable : out std_logic;`
247			`ncraddress : out std_logic_vector(5 downto 0);`
248			`ncwrite : out std_logic;`
249			`ncwdata : out std_logic_vector(8 downto 0);`
250			`ncwaddress : out std_logic_vector(5 downto 0);`
251			`ncrdata : in std_logic_vector(8 downto 0);`
252			`rmrenable : out std_logic;`
253			`rmraddress : out std_logic_vector(7 downto 0);`
254			`rmwrite : out std_logic;`
255			`rmwdata : out std_logic_vector(7 downto 0);`
256			`rmwaddress : out std_logic_vector(7 downto 0);`
257			`rmrdata : in std_logic_vector(7 downto 0);`
258			`linkdis : out std_logic;`
259			`testclk : in std_logic;`
260			`testrst : in std_logic;`
261			`testen : in std_logic);`
262			`end component;`
263
264			`component grspwc_axcelerator_16_16_rmap0_crc0 is`
265			`port(`
266			`rst : in std_logic;`
267			`clk : in std_logic;`
268			`txclk : in std_logic;`
269			`hgrant : in std_logic;`
270			`hready : in std_logic;`
271			`hresp : in std_logic_vector (1 downto 0);`
272			`hrdata : in std_logic_vector (31 downto 0);`
273			`hbusreq : out std_logic;`
274			`hlock : out std_logic;`
275			`htrans : out std_logic_vector (1 downto 0);`
276			`haddr : out std_logic_vector (31 downto 0);`
277			`hwrite : out std_logic;`
278			`hsize : out std_logic_vector (2 downto 0);`
279			`hburst : out std_logic_vector (2 downto 0);`
280			`hprot : out std_logic_vector (3 downto 0);`
281			`hwdata : out std_logic_vector (31 downto 0);`
282			`psel : in std_logic;`
283			`penable : in std_logic;`
284			`paddr : in std_logic_vector (31 downto 0);`
285			`pwrite : in std_logic;`
286			`pwdata : in std_logic_vector (31 downto 0);`
287			`prdata : out std_logic_vector (31 downto 0);`
288			`di : in std_logic_vector(1 downto 0);`
289			`si : in std_logic_vector(1 downto 0);`
290			`do : out std_logic_vector(1 downto 0);`
291			`so : out std_logic_vector(1 downto 0);`
292			`tickin : in std_logic;`
293			`tickout : out std_logic;`
294			`irq : out std_logic;`
295			`clkdiv10 : in std_logic_vector (7 downto 0);`
296			`dcrstval : in std_logic_vector (9 downto 0);`
297			`timerrstval : in std_logic_vector (11 downto 0);`
298			`rmapen : in std_logic;`
299			`rxclki : in std_logic_vector(1 downto 0);`
300			`nrxclki : in std_logic_vector(1 downto 0);`
301			`rxclko : out std_logic_vector(1 downto 0);`
302			`rxrenable : out std_logic;`
303			`rxraddress : out std_logic_vector (4 downto 0);`
304			`rxwrite : out std_logic;`
305			`rxwdata : out std_logic_vector (31 downto 0);`
306			`rxwaddress : out std_logic_vector (4 downto 0);`
307			`rxrdata : in std_logic_vector (31 downto 0);`
308			`txrenable : out std_logic;`
309			`txraddress : out std_logic_vector (4 downto 0);`
310			`txwrite : out std_logic;`
311			`txwdata : out std_logic_vector (31 downto 0);`
312			`txwaddress : out std_logic_vector (4 downto 0);`
313			`txrdata : in std_logic_vector (31 downto 0);`
314			`ncrenable : out std_logic;`
315			`ncraddress : out std_logic_vector (5 downto 0);`
316			`ncwrite : out std_logic;`
317			`ncwdata : out std_logic_vector (8 downto 0);`
318			`ncwaddress : out std_logic_vector (5 downto 0);`
319			`ncrdata : in std_logic_vector (8 downto 0);`
320			`rmrenable : out std_logic;`
321			`rmraddress : out std_logic_vector (7 downto 0);`
322			`rmwrite : out std_logic;`
323			`rmwdata : out std_logic_vector (7 downto 0);`
324			`rmwaddress : out std_logic_vector (7 downto 0);`
325			`rmrdata : in std_logic_vector (7 downto 0);`
326			`linkdis : out std_logic;`
327			`testclk : in std_logic;`
328			`testrst : in std_logic;`
329			`testen : in std_logic);`
330			`end component;`
331
332			`begin`
333
334			`hlock <= '0';`
335			`f16_16_crc1 : if (rmapcrc = 1) and (rmap = 0) and (fifosize1 = 16) and (fifosize2 = 16) generate`
336			`grspwc0 : grspwc_axcelerator_16_16_rmap0_crc1`
337			`port map(`
338			`rst => rst,`
339			`clk => clk,`
340			`txclk => txclk,`
341			`--ahb mst in`
342			`hgrant => hgrant,`
343			`hready => hready,`
344			`hresp => hresp,`
345			`hrdata => hrdata,`
346			`--ahb mst out`
347			`hbusreq => hbusreq,`
348			`hlock => open, --hlock,`
349			`htrans => htrans,`
350			`haddr => haddr,`
351			`hwrite => hwrite,`
352			`hsize => hsize,`
353			`hburst => hburst,`
354			`hprot => hprot,`
355			`hwdata => hwdata,`
356			`--apb slv in`
357			`psel => psel,`
358			`penable => penable,`
359			`paddr => paddr,`
360			`pwrite => pwrite,`
361			`pwdata => pwdata,`
362			`--apb slv out`
363			`prdata => prdata,`
364			`--spw in`
365			`di => di,`
366			`si => si,`
367			`--spw out`
368			`do => do,`
369			`so => so,`
370			`--time iface`
371			`tickin => tickin,`
372			`tickout => tickout,`
373			`--clk bufs`
374			`rxclki => rxclki,`
375			`nrxclki => nrxclki,`
376			`rxclko => rxclko,`
377			`--irq`
378			`irq => irq,`
379			`--misc`
380			`clkdiv10 => clkdiv10,`
381			`dcrstval => dcrstval,`
382			`timerrstval => timerrstval,`
383			`--rmapen`
384			`rmapen => rmapen,`
385			`--rx ahb fifo`
386			`rxrenable => rxrenable,`
387			`rxraddress => rxraddress,`
388			`rxwrite => rxwrite,`
389			`rxwdata => rxwdata,`
390			`rxwaddress => rxwaddress,`
391			`rxrdata => rxrdata,`
392			`--tx ahb fifo`
393			`txrenable => txrenable,`
394			`txraddress => txraddress,`
395			`txwrite => txwrite,`
396			`txwdata => txwdata,`
397			`txwaddress => txwaddress,`
398			`txrdata => txrdata,`
399			`--nchar fifo`
400			`ncrenable => ncrenable,`
401			`ncraddress => ncraddress,`
402			`ncwrite => ncwrite,`
403			`ncwdata => ncwdata,`
404			`ncwaddress => ncwaddress,`
405			`ncrdata => ncrdata,`
406			`--rmap buf`
407			`rmrenable => rmrenable,`
408			`rmraddress => rmraddress,`
409			`rmwrite => rmwrite,`
410			`rmwdata => rmwdata,`
411			`rmwaddress => rmwaddress,`
412			`rmrdata => rmrdata,`
413			`linkdis => linkdis,`
414			`testclk => testclk,`
415			`testrst => testrst,`
416			`testen => testen`
417			`);`
418			`end generate;`
419
420			`f16_16_rmap8_crc1 : if (rmapcrc = 1) and (rmap = 1) and (rmapbufs = 8) and (fifosize1 = 16) and (fifosize2 = 16) generate`
421			`grspwc0 : grspwc_axcelerator_16_16_rmap8_crc1`
422			`port map(`
423			`rst => rst,`
424			`clk => clk,`
425			`txclk => txclk,`
426			`--ahb mst in`
427			`hgrant => hgrant,`
428			`hready => hready,`
429			`hresp => hresp,`
430			`hrdata => hrdata,`
431			`--ahb mst out`
432			`hbusreq => hbusreq,`
433			`hlock => open, --hlock,`
434			`htrans => htrans,`
435			`haddr => haddr,`
436			`hwrite => hwrite,`
437			`hsize => hsize,`
438			`hburst => hburst,`
439			`hprot => hprot,`
440			`hwdata => hwdata,`
441			`--apb slv in`
442			`psel => psel,`
443			`penable => penable,`
444			`paddr => paddr,`
445			`pwrite => pwrite,`
446			`pwdata => pwdata,`
447			`--apb slv out`
448			`prdata => prdata,`
449			`--spw in`
450			`di => di,`
451			`si => si,`
452			`--spw out`
453			`do => do,`
454			`so => so,`
455			`--time iface`
456			`tickin => tickin,`
457			`tickout => tickout,`
458			`--clk bufs`
459			`rxclki => rxclki,`
460			`nrxclki => nrxclki,`
461			`rxclko => rxclko,`
462			`--irq`
463			`irq => irq,`
464			`--misc`
465			`clkdiv10 => clkdiv10,`
466			`dcrstval => dcrstval,`
467			`timerrstval => timerrstval,`
468			`--rmapen`
469			`rmapen => rmapen,`
470			`--rx ahb fifo`
471			`rxrenable => rxrenable,`
472			`rxraddress => rxraddress,`
473			`rxwrite => rxwrite,`
474			`rxwdata => rxwdata,`
475			`rxwaddress => rxwaddress,`
476			`rxrdata => rxrdata,`
477			`--tx ahb fifo`
478			`txrenable => txrenable,`
479			`txraddress => txraddress,`
480			`txwrite => txwrite,`
481			`txwdata => txwdata,`
482			`txwaddress => txwaddress,`
483			`txrdata => txrdata,`
484			`--nchar fifo`
485			`ncrenable => ncrenable,`
486			`ncraddress => ncraddress,`
487			`ncwrite => ncwrite,`
488			`ncwdata => ncwdata,`
489			`ncwaddress => ncwaddress,`
490			`ncrdata => ncrdata,`
491			`--rmap buf`
492			`rmrenable => rmrenable,`
493			`rmraddress => rmraddress,`
494			`rmwrite => rmwrite,`
495			`rmwdata => rmwdata,`
496			`rmwaddress => rmwaddress,`
497			`rmrdata => rmrdata,`
498			`linkdis => linkdis,`
499			`testclk => testclk,`
500			`testrst => testrst,`
501			`testen => testen`
502			`);`
503			`end generate;`
504
505			`f16_16_crc0 : if (rmapcrc = 0) and (rmap = 0) and (fifosize1 = 16) and (fifosize2 = 16) generate`
506			`grspwc0 : grspwc_axcelerator_16_16_rmap0_crc0`
507			`port map(`
508			`rst => rst,`
509			`clk => clk,`
510			`txclk => txclk,`
511			`--ahb mst in`
512			`hgrant => hgrant,`
513			`hready => hready,`
514			`hresp => hresp,`
515			`hrdata => hrdata,`
516			`--ahb mst out`
517			`hbusreq => hbusreq,`
518			`hlock => open, --hlock,`
519			`htrans => htrans,`
520			`haddr => haddr,`
521			`hwrite => hwrite,`
522			`hsize => hsize,`
523			`hburst => hburst,`
524			`hprot => hprot,`
525			`hwdata => hwdata,`
526			`--apb slv in`
527			`psel => psel,`
528			`penable => penable,`
529			`paddr => paddr,`
530			`pwrite => pwrite,`
531			`pwdata => pwdata,`
532			`--apb slv out`
533			`prdata => prdata,`
534			`--spw in`
535			`di => di,`
536			`si => si,`
537			`--spw out`
538			`do => do,`
539			`so => so,`
540			`--time iface`
541			`tickin => tickin,`
542			`tickout => tickout,`
543			`--clk bufs`
544			`rxclki => rxclki,`
545			`nrxclki => nrxclki,`
546			`rxclko => rxclko,`
547			`--irq`
548			`irq => irq,`
549			`--misc`
550			`clkdiv10 => clkdiv10,`
551			`dcrstval => dcrstval,`
552			`timerrstval => timerrstval,`
553			`--rmapen`
554			`rmapen => rmapen,`
555			`--rx ahb fifo`
556			`rxrenable => rxrenable,`
557			`rxraddress => rxraddress,`
558			`rxwrite => rxwrite,`
559			`rxwdata => rxwdata,`
560			`rxwaddress => rxwaddress,`
561			`rxrdata => rxrdata,`
562			`--tx ahb fifo`
563			`txrenable => txrenable,`
564			`txraddress => txraddress,`
565			`txwrite => txwrite,`
566			`txwdata => txwdata,`
567			`txwaddress => txwaddress,`
568			`txrdata => txrdata,`
569			`--nchar fifo`
570			`ncrenable => ncrenable,`
571			`ncraddress => ncraddress,`
572			`ncwrite => ncwrite,`
573			`ncwdata => ncwdata,`
574			`ncwaddress => ncwaddress,`
575			`ncrdata => ncrdata,`
576			`--rmap buf`
577			`rmrenable => rmrenable,`
578			`rmraddress => rmraddress,`
579			`rmwrite => rmwrite,`
580			`rmwdata => rmwdata,`
581			`rmwaddress => rmwaddress,`
582			`rmrdata => rmrdata,`
583			`linkdis => linkdis,`
584			`testclk => testclk,`
585			`testrst => testrst,`
586			`testen => testen`
587			`);`
588			`end generate;`
589
590			`end architecture;`