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dimamali |
------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003, Gaisler Research
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-----------------------------------------------------------------------------
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-- Entity: grfpw
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-- File: grfpw.vhd
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-- Author: Jiri Gaisler - Gaisler Research
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-- Description: GRFPU / GRLFPC netlist wrapper
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------------------------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use work.gencomp.all;
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entity grfpw_net is
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generic (tech : integer := 0;
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pclow : integer range 0 to 2 := 2;
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dsu : integer range 0 to 2 := 1;
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disas : integer range 0 to 2 := 0;
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pipe : integer range 0 to 2 := 0
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);
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port (
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rst : in std_ulogic; -- Reset
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clk : in std_ulogic;
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holdn : in std_ulogic; -- pipeline hold
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cpi_flush : in std_ulogic; -- pipeline flush
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cpi_exack : in std_ulogic; -- FP exception acknowledge
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cpi_a_rs1 : in std_logic_vector(4 downto 0);
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cpi_d_pc : in std_logic_vector(31 downto 0);
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cpi_d_inst : in std_logic_vector(31 downto 0);
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cpi_d_cnt : in std_logic_vector(1 downto 0);
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cpi_d_trap : in std_ulogic;
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cpi_d_annul : in std_ulogic;
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cpi_d_pv : in std_ulogic;
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cpi_a_pc : in std_logic_vector(31 downto 0);
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cpi_a_inst : in std_logic_vector(31 downto 0);
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cpi_a_cnt : in std_logic_vector(1 downto 0);
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cpi_a_trap : in std_ulogic;
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cpi_a_annul : in std_ulogic;
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cpi_a_pv : in std_ulogic;
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cpi_e_pc : in std_logic_vector(31 downto 0);
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cpi_e_inst : in std_logic_vector(31 downto 0);
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cpi_e_cnt : in std_logic_vector(1 downto 0);
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cpi_e_trap : in std_ulogic;
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cpi_e_annul : in std_ulogic;
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cpi_e_pv : in std_ulogic;
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cpi_m_pc : in std_logic_vector(31 downto 0);
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cpi_m_inst : in std_logic_vector(31 downto 0);
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cpi_m_cnt : in std_logic_vector(1 downto 0);
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cpi_m_trap : in std_ulogic;
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cpi_m_annul : in std_ulogic;
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cpi_m_pv : in std_ulogic;
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cpi_x_pc : in std_logic_vector(31 downto 0);
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cpi_x_inst : in std_logic_vector(31 downto 0);
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cpi_x_cnt : in std_logic_vector(1 downto 0);
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cpi_x_trap : in std_ulogic;
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cpi_x_annul : in std_ulogic;
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cpi_x_pv : in std_ulogic;
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cpi_lddata : in std_logic_vector(31 downto 0); -- load data
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cpi_dbg_enable : in std_ulogic;
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cpi_dbg_write : in std_ulogic;
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cpi_dbg_fsr : in std_ulogic; -- FSR access
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cpi_dbg_addr : in std_logic_vector(4 downto 0);
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cpi_dbg_data : in std_logic_vector(31 downto 0);
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cpo_data : out std_logic_vector(31 downto 0); -- store data
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cpo_exc : out std_logic; -- FP exception
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cpo_cc : out std_logic_vector(1 downto 0); -- FP condition codes
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cpo_ccv : out std_ulogic; -- FP condition codes valid
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cpo_ldlock : out std_logic; -- FP pipeline hold
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cpo_holdn : out std_ulogic;
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cpo_dbg_data : out std_logic_vector(31 downto 0);
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rfi1_rd1addr : out std_logic_vector(3 downto 0);
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rfi1_rd2addr : out std_logic_vector(3 downto 0);
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rfi1_wraddr : out std_logic_vector(3 downto 0);
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rfi1_wrdata : out std_logic_vector(31 downto 0);
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rfi1_ren1 : out std_ulogic;
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rfi1_ren2 : out std_ulogic;
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rfi1_wren : out std_ulogic;
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rfi2_rd1addr : out std_logic_vector(3 downto 0);
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rfi2_rd2addr : out std_logic_vector(3 downto 0);
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rfi2_wraddr : out std_logic_vector(3 downto 0);
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rfi2_wrdata : out std_logic_vector(31 downto 0);
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rfi2_ren1 : out std_ulogic;
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rfi2_ren2 : out std_ulogic;
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rfi2_wren : out std_ulogic;
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rfo1_data1 : in std_logic_vector(31 downto 0);
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rfo1_data2 : in std_logic_vector(31 downto 0);
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rfo2_data1 : in std_logic_vector(31 downto 0);
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rfo2_data2 : in std_logic_vector(31 downto 0)
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);
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end;
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architecture rtl of grfpw_net is
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component grfpw_unisim
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generic (tech : integer := 0);
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port(
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rst : in std_logic;
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clk : in std_logic;
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holdn : in std_logic;
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cpi_flush : in std_logic;
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cpi_exack : in std_logic;
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cpi_a_rs1 : in std_logic_vector (4 downto 0);
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cpi_d_pc : in std_logic_vector (31 downto 0);
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cpi_d_inst : in std_logic_vector (31 downto 0);
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cpi_d_cnt : in std_logic_vector (1 downto 0);
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cpi_d_trap : in std_logic;
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cpi_d_annul : in std_logic;
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cpi_d_pv : in std_logic;
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cpi_a_pc : in std_logic_vector (31 downto 0);
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cpi_a_inst : in std_logic_vector (31 downto 0);
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cpi_a_cnt : in std_logic_vector (1 downto 0);
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cpi_a_trap : in std_logic;
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cpi_a_annul : in std_logic;
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cpi_a_pv : in std_logic;
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cpi_e_pc : in std_logic_vector (31 downto 0);
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cpi_e_inst : in std_logic_vector (31 downto 0);
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cpi_e_cnt : in std_logic_vector (1 downto 0);
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cpi_e_trap : in std_logic;
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cpi_e_annul : in std_logic;
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cpi_e_pv : in std_logic;
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cpi_m_pc : in std_logic_vector (31 downto 0);
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cpi_m_inst : in std_logic_vector (31 downto 0);
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cpi_m_cnt : in std_logic_vector (1 downto 0);
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cpi_m_trap : in std_logic;
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cpi_m_annul : in std_logic;
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cpi_m_pv : in std_logic;
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cpi_x_pc : in std_logic_vector (31 downto 0);
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cpi_x_inst : in std_logic_vector (31 downto 0);
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cpi_x_cnt : in std_logic_vector (1 downto 0);
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cpi_x_trap : in std_logic;
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cpi_x_annul : in std_logic;
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cpi_x_pv : in std_logic;
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cpi_lddata : in std_logic_vector (31 downto 0);
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cpi_dbg_enable : in std_logic;
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cpi_dbg_write : in std_logic;
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cpi_dbg_fsr : in std_logic;
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cpi_dbg_addr : in std_logic_vector (4 downto 0);
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cpi_dbg_data : in std_logic_vector (31 downto 0);
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cpo_data : out std_logic_vector (31 downto 0);
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cpo_exc : out std_logic;
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cpo_cc : out std_logic_vector (1 downto 0);
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cpo_ccv : out std_logic;
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cpo_ldlock : out std_logic;
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cpo_holdn : out std_logic;
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cpo_dbg_data : out std_logic_vector (31 downto 0);
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rfi1_rd1addr : out std_logic_vector (3 downto 0);
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rfi1_rd2addr : out std_logic_vector (3 downto 0);
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rfi1_wraddr : out std_logic_vector (3 downto 0);
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rfi1_wrdata : out std_logic_vector (31 downto 0);
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rfi1_ren1 : out std_logic;
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rfi1_ren2 : out std_logic;
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rfi1_wren : out std_logic;
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rfi2_rd1addr : out std_logic_vector (3 downto 0);
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rfi2_rd2addr : out std_logic_vector (3 downto 0);
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rfi2_wraddr : out std_logic_vector (3 downto 0);
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rfi2_wrdata : out std_logic_vector (31 downto 0);
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rfi2_ren1 : out std_logic;
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rfi2_ren2 : out std_logic;
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rfi2_wren : out std_logic;
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rfo1_data1 : in std_logic_vector (31 downto 0);
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rfo1_data2 : in std_logic_vector (31 downto 0);
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rfo2_data1 : in std_logic_vector (31 downto 0);
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rfo2_data2 : in std_logic_vector (31 downto 0);
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disasen : in std_logic);
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end component;
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component grfpw_0_stratixii
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port(
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rst : in std_logic;
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clk : in std_logic;
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holdn : in std_logic;
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cpi_flush : in std_logic;
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cpi_exack : in std_logic;
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cpi_a_rs1 : in std_logic_vector (4 downto 0);
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cpi_d_pc : in std_logic_vector (31 downto 0);
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cpi_d_inst : in std_logic_vector (31 downto 0);
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cpi_d_cnt : in std_logic_vector (1 downto 0);
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cpi_d_trap : in std_logic;
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cpi_d_annul : in std_logic;
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cpi_d_pv : in std_logic;
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cpi_a_pc : in std_logic_vector (31 downto 0);
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cpi_a_inst : in std_logic_vector (31 downto 0);
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cpi_a_cnt : in std_logic_vector (1 downto 0);
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cpi_a_trap : in std_logic;
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cpi_a_annul : in std_logic;
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cpi_a_pv : in std_logic;
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cpi_e_pc : in std_logic_vector (31 downto 0);
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cpi_e_inst : in std_logic_vector (31 downto 0);
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cpi_e_cnt : in std_logic_vector (1 downto 0);
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cpi_e_trap : in std_logic;
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cpi_e_annul : in std_logic;
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cpi_e_pv : in std_logic;
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cpi_m_pc : in std_logic_vector (31 downto 0);
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cpi_m_inst : in std_logic_vector (31 downto 0);
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cpi_m_cnt : in std_logic_vector (1 downto 0);
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cpi_m_trap : in std_logic;
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cpi_m_annul : in std_logic;
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cpi_m_pv : in std_logic;
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cpi_x_pc : in std_logic_vector (31 downto 0);
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cpi_x_inst : in std_logic_vector (31 downto 0);
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cpi_x_cnt : in std_logic_vector (1 downto 0);
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cpi_x_trap : in std_logic;
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cpi_x_annul : in std_logic;
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cpi_x_pv : in std_logic;
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cpi_lddata : in std_logic_vector (31 downto 0);
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cpi_dbg_enable : in std_logic;
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cpi_dbg_write : in std_logic;
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cpi_dbg_fsr : in std_logic;
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cpi_dbg_addr : in std_logic_vector (4 downto 0);
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cpi_dbg_data : in std_logic_vector (31 downto 0);
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cpo_data : out std_logic_vector (31 downto 0);
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cpo_exc : out std_logic;
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cpo_cc : out std_logic_vector (1 downto 0);
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cpo_ccv : out std_logic;
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cpo_ldlock : out std_logic;
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cpo_holdn : out std_logic;
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cpo_dbg_data : out std_logic_vector (31 downto 0);
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rfi1_rd1addr : out std_logic_vector (3 downto 0);
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rfi1_rd2addr : out std_logic_vector (3 downto 0);
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rfi1_wraddr : out std_logic_vector (3 downto 0);
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rfi1_wrdata : out std_logic_vector (31 downto 0);
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rfi1_ren1 : out std_logic;
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rfi1_ren2 : out std_logic;
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rfi1_wren : out std_logic;
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rfi2_rd1addr : out std_logic_vector (3 downto 0);
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rfi2_rd2addr : out std_logic_vector (3 downto 0);
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rfi2_wraddr : out std_logic_vector (3 downto 0);
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rfi2_wrdata : out std_logic_vector (31 downto 0);
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rfi2_ren1 : out std_logic;
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rfi2_ren2 : out std_logic;
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rfi2_wren : out std_logic;
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rfo1_data1 : in std_logic_vector (31 downto 0);
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rfo1_data2 : in std_logic_vector (31 downto 0);
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rfo2_data1 : in std_logic_vector (31 downto 0);
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rfo2_data2 : in std_logic_vector (31 downto 0));
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end component;
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component grfpw_tsmc90
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port (
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rst : in std_ulogic; -- Reset
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clk : in std_ulogic;
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263 |
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holdn : in std_ulogic; -- pipeline hold
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264 |
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cpi_flush : in std_ulogic; -- pipeline flush
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265 |
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cpi_exack : in std_ulogic; -- FP exception acknowledge
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266 |
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cpi_a_rs1 : in std_logic_vector(4 downto 0);
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267 |
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cpi_d_pc : in std_logic_vector(31 downto 0);
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268 |
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cpi_d_inst : in std_logic_vector(31 downto 0);
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cpi_d_cnt : in std_logic_vector(1 downto 0);
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270 |
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cpi_d_trap : in std_ulogic;
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271 |
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cpi_d_annul : in std_ulogic;
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272 |
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cpi_d_pv : in std_ulogic;
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273 |
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cpi_a_pc : in std_logic_vector(31 downto 0);
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274 |
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cpi_a_inst : in std_logic_vector(31 downto 0);
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275 |
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cpi_a_cnt : in std_logic_vector(1 downto 0);
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276 |
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cpi_a_trap : in std_ulogic;
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277 |
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cpi_a_annul : in std_ulogic;
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278 |
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cpi_a_pv : in std_ulogic;
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279 |
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cpi_e_pc : in std_logic_vector(31 downto 0);
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280 |
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cpi_e_inst : in std_logic_vector(31 downto 0);
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281 |
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cpi_e_cnt : in std_logic_vector(1 downto 0);
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282 |
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cpi_e_trap : in std_ulogic;
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283 |
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cpi_e_annul : in std_ulogic;
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284 |
|
|
cpi_e_pv : in std_ulogic;
|
285 |
|
|
cpi_m_pc : in std_logic_vector(31 downto 0);
|
286 |
|
|
cpi_m_inst : in std_logic_vector(31 downto 0);
|
287 |
|
|
cpi_m_cnt : in std_logic_vector(1 downto 0);
|
288 |
|
|
cpi_m_trap : in std_ulogic;
|
289 |
|
|
cpi_m_annul : in std_ulogic;
|
290 |
|
|
cpi_m_pv : in std_ulogic;
|
291 |
|
|
cpi_x_pc : in std_logic_vector(31 downto 0);
|
292 |
|
|
cpi_x_inst : in std_logic_vector(31 downto 0);
|
293 |
|
|
cpi_x_cnt : in std_logic_vector(1 downto 0);
|
294 |
|
|
cpi_x_trap : in std_ulogic;
|
295 |
|
|
cpi_x_annul : in std_ulogic;
|
296 |
|
|
cpi_x_pv : in std_ulogic;
|
297 |
|
|
cpi_lddata : in std_logic_vector(31 downto 0); -- load data
|
298 |
|
|
cpi_dbg_enable : in std_ulogic;
|
299 |
|
|
cpi_dbg_write : in std_ulogic;
|
300 |
|
|
cpi_dbg_fsr : in std_ulogic; -- FSR access
|
301 |
|
|
cpi_dbg_addr : in std_logic_vector(4 downto 0);
|
302 |
|
|
cpi_dbg_data : in std_logic_vector(31 downto 0);
|
303 |
|
|
|
304 |
|
|
cpo_data : out std_logic_vector(31 downto 0); -- store data
|
305 |
|
|
cpo_exc : out std_logic; -- FP exception
|
306 |
|
|
cpo_cc : out std_logic_vector(1 downto 0); -- FP condition codes
|
307 |
|
|
cpo_ccv : out std_ulogic; -- FP condition codes valid
|
308 |
|
|
cpo_ldlock : out std_logic; -- FP pipeline hold
|
309 |
|
|
cpo_holdn : out std_ulogic;
|
310 |
|
|
--cpo_restart : out std_ulogic;
|
311 |
|
|
cpo_dbg_data : out std_logic_vector(31 downto 0);
|
312 |
|
|
|
313 |
|
|
rfi1_rd1addr : out std_logic_vector(3 downto 0);
|
314 |
|
|
rfi1_rd2addr : out std_logic_vector(3 downto 0);
|
315 |
|
|
rfi1_wraddr : out std_logic_vector(3 downto 0);
|
316 |
|
|
rfi1_wrdata : out std_logic_vector(31 downto 0);
|
317 |
|
|
rfi1_ren1 : out std_ulogic;
|
318 |
|
|
rfi1_ren2 : out std_ulogic;
|
319 |
|
|
rfi1_wren : out std_ulogic;
|
320 |
|
|
|
321 |
|
|
rfi2_rd1addr : out std_logic_vector(3 downto 0);
|
322 |
|
|
rfi2_rd2addr : out std_logic_vector(3 downto 0);
|
323 |
|
|
rfi2_wraddr : out std_logic_vector(3 downto 0);
|
324 |
|
|
rfi2_wrdata : out std_logic_vector(31 downto 0);
|
325 |
|
|
rfi2_ren1 : out std_ulogic;
|
326 |
|
|
rfi2_ren2 : out std_ulogic;
|
327 |
|
|
rfi2_wren : out std_ulogic;
|
328 |
|
|
|
329 |
|
|
rfo1_data1 : in std_logic_vector(31 downto 0);
|
330 |
|
|
rfo1_data2 : in std_logic_vector(31 downto 0);
|
331 |
|
|
rfo2_data1 : in std_logic_vector(31 downto 0);
|
332 |
|
|
rfo2_data2 : in std_logic_vector(31 downto 0)
|
333 |
|
|
);
|
334 |
|
|
end component;
|
335 |
|
|
|
336 |
|
|
attribute DONT_TOUCH : boolean;
|
337 |
|
|
attribute DONT_TOUCH of u0_tsmc90 : label is TRUE;
|
338 |
|
|
|
339 |
|
|
signal disasen : std_logic;
|
340 |
|
|
|
341 |
|
|
begin
|
342 |
|
|
|
343 |
|
|
disasen <= '1' when disas /= 0 else '0';
|
344 |
|
|
|
345 |
|
|
uni : if (tech = virtex2) or (tech = virtex4) or (tech = virtex5) or
|
346 |
|
|
(tech = spartan3) or (tech = spartan3e)
|
347 |
|
|
generate
|
348 |
|
|
grfpw0 : grfpw_unisim
|
349 |
|
|
generic map (tech => tech)
|
350 |
|
|
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
|
351 |
|
|
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
|
352 |
|
|
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
|
353 |
|
|
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
|
354 |
|
|
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
|
355 |
|
|
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
|
356 |
|
|
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
|
357 |
|
|
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
|
358 |
|
|
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
|
359 |
|
|
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
|
360 |
|
|
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
|
361 |
|
|
rfo1_data2, rfo2_data1, rfo2_data2, disasen);
|
362 |
|
|
end generate;
|
363 |
|
|
|
364 |
|
|
alt : if (tech = stratix1) or (tech = cyclone3) or
|
365 |
|
|
(tech = stratix2) or (tech = stratix3) or (tech = altera) generate
|
366 |
|
|
grfpw0 : grfpw_0_stratixii
|
367 |
|
|
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
|
368 |
|
|
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
|
369 |
|
|
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
|
370 |
|
|
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
|
371 |
|
|
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
|
372 |
|
|
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
|
373 |
|
|
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
|
374 |
|
|
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
|
375 |
|
|
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
|
376 |
|
|
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
|
377 |
|
|
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
|
378 |
|
|
rfo1_data2, rfo2_data1, rfo2_data2 );
|
379 |
|
|
end generate;
|
380 |
|
|
|
381 |
|
|
u0_tsmc90 : if tech = tsmc90 generate
|
382 |
|
|
grfpw0 : grfpw_tsmc90
|
383 |
|
|
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
|
384 |
|
|
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
|
385 |
|
|
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
|
386 |
|
|
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
|
387 |
|
|
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
|
388 |
|
|
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
|
389 |
|
|
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
|
390 |
|
|
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
|
391 |
|
|
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
|
392 |
|
|
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
|
393 |
|
|
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
|
394 |
|
|
rfo1_data2, rfo2_data1, rfo2_data2 );
|
395 |
|
|
end generate;
|
396 |
|
|
|
397 |
|
|
|
398 |
|
|
end;
|
399 |
|
|
|