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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [lib/] [techmap/] [stratixiii/] [alt/] [aclkout.vhd] - Blame information for rev 2

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1 2 dimamali 
library ieee;
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use ieee.std_logic_1164.all;
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library grlib;
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use grlib.stdlib.all;
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library techmap;
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use techmap.gencomp.all;
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library stratixiii;
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use stratixiii.all;
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entity aclkout is
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  port(
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    clk     : in  std_logic;
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    ddr_clk : out std_logic;
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    ddr_clkn: out std_logic
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  );
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end;
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architecture rtl of aclkout is
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component stratixiii_ddio_out
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  generic(
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    power_up                           :  string := "low";
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    async_mode                         :  string := "none";
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    sync_mode                          :  string := "none";
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    half_rate_mode                     :  string := "false";
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    use_new_clocking_model             :  string := "false";
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    lpm_type                           :  string := "stratixiii_ddio_out"
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  );
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  port (
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    datainlo                : in std_logic := '0';
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    datainhi                : in std_logic := '0';
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    clk                     : in std_logic := '0';
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    clkhi                   : in std_logic := '0';
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    clklo                   : in std_logic := '0';
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    muxsel                  : in std_logic := '0';
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    ena                     : in std_logic := '1';
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    areset                  : in std_logic := '0';
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    sreset                  : in std_logic := '0';
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    dataout                 : out std_logic;
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    dfflo                   : out std_logic;
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    dffhi                   : out std_logic-- ;
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    --devclrn                 : in std_logic := '1';
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    --devpor                  : in std_logic := '1'
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  );
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end component;
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component stratixiii_pseudo_diff_out is
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  generic (
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    lpm_type        :  string := "stratixiii_pseudo_diff_out"
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  );
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  port (
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    i                       : in std_logic := '0';
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    o                       : out std_logic;
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    obar                    : out std_logic
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  );
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end component;
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component  stratixiii_io_obuf
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  generic(
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    bus_hold    :       string := "false";
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    open_drain_output   :       string := "false";
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    shift_series_termination_control    :       string := "false";
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    lpm_type    :       string := "stratixiii_io_obuf"
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  );
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  port(
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    dynamicterminationcontrol   :       in std_logic := '0';
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    i   :       in std_logic := '0';
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    o   :       out std_logic;
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    obar        :       out std_logic;
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    oe  :       in std_logic := '1'--;
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    --parallelterminationcontrol        :       in std_logic_vector(13 downto 0) := (others => '0');
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    --seriesterminationcontrol  :       in std_logic_vector(13 downto 0) := (others => '0')
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  );
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end component;
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signal vcc      : std_logic;
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signal gnd      : std_logic_vector(13 downto 0);
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signal clk_reg  : std_logic;
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signal clk_buf, clk_bufn  : std_logic;
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begin
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  vcc <= '1'; gnd <= (others => '0');
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  out_reg0 : stratixiii_ddio_out
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    generic map(
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      power_up               => "low",
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      async_mode             => "none",
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      sync_mode              => "none",
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      half_rate_mode         => "false",
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      use_new_clocking_model => "true",
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      lpm_type               => "stratixiii_ddio_out"
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    )
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    port map(
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      datainlo => gnd(0),
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      datainhi => vcc,
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      clk      => clk,
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      clkhi    => clk,
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      clklo    => clk,
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      muxsel   => clk,
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      ena      => vcc,
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      areset   => gnd(0),
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      sreset   => gnd(0),
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      dataout  => clk_reg,
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      dfflo    => open,
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      dffhi    => open--,
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      --devclrn  => vcc,
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      --devpor   => vcc
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    );
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  pseudo_diff0 : stratixiii_pseudo_diff_out
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    port map(
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      i     => clk_reg,
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      o     => clk_buf,
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      obar  => clk_bufn
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    );
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  out_buf0 : stratixiii_io_obuf
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    generic map(
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      open_drain_output                => "false",
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      shift_series_termination_control => "false",
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      bus_hold                         => "false",
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      lpm_type                         => "stratixiii_io_obuf"
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    )
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    port map(
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      i                          => clk_buf,
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      oe                         => vcc,
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      dynamicterminationcontrol  => gnd(0),
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      --seriesterminationcontrol   => gnd,
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      --parallelterminationcontrol => gnd,
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      o                          => ddr_clk,
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      obar                       => open
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    );
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  out_bufn0 : stratixiii_io_obuf
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    generic map(
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      open_drain_output                => "false",
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      shift_series_termination_control => "false",
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      bus_hold                         => "false",
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      lpm_type                         => "stratixiii_io_obuf"
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    )
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    port map(
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      i                          => clk_bufn,
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      oe                         => vcc,
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      dynamicterminationcontrol  => gnd(0),
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      --seriesterminationcontrol   => gnd,
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      --parallelterminationcontrol => gnd,
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      o                          => ddr_clkn,
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      obar                       => open
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    );
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end;

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