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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [lib/] [techmap/] [stratixiii/] [alt/] [adqsout.vhd] - Blame information for rev 2

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1 2 dimamali 
library ieee;
2 
use ieee.std_logic_1164.all;
3 
library grlib;
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use grlib.stdlib.all;
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library techmap;
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use techmap.gencomp.all;
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library stratixiii;
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use stratixiii.all;
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entity adqsout is
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  port(
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    clk       : in  std_logic; -- clk90
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    dqs       : in  std_logic;
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    dqs_oe    : in  std_logic;
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    dqs_oct   : in  std_logic; -- gnd = disable
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    dqs_pad   : out std_logic; -- DQS pad
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    dqsn_pad  : out std_logic  -- DQSN pad
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  );
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end;
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architecture rtl of adqsout is
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component stratixiii_ddio_out
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  generic(
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    power_up                           :  string := "low";
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    async_mode                         :  string := "none";
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    sync_mode                          :  string := "none";
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    half_rate_mode                     :  string := "false";
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    use_new_clocking_model             :  string := "false";
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    lpm_type                           :  string := "stratixiii_ddio_out"
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  );
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  port (
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    datainlo                : in std_logic := '0';
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    datainhi                : in std_logic := '0';
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    clk                     : in std_logic := '0';
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    clkhi                   : in std_logic := '0';
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    clklo                   : in std_logic := '0';
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    muxsel                  : in std_logic := '0';
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    ena                     : in std_logic := '1';
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    areset                  : in std_logic := '0';
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    sreset                  : in std_logic := '0';
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    dataout                 : out std_logic--;
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    --dfflo                   : out std_logic;
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    --dffhi                   : out std_logic;
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    --devclrn                 : in std_logic := '1';
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    --devpor                  : in std_logic := '1'
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  );
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end component;
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component stratixiii_ddio_oe is
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  generic(
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    power_up              :  string := "low";
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    async_mode            :  string := "none";
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    sync_mode             :  string := "none";
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    lpm_type              :  string := "stratixiii_ddio_oe"
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  );
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  port (
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    oe                      : IN std_logic := '1';
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    clk                     : IN std_logic := '0';
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    ena                     : IN std_logic := '1';
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    areset                  : IN std_logic := '0';
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    sreset                  : IN std_logic := '0';
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    dataout                 : OUT std_logic--;
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    --dfflo                   : OUT std_logic;
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    --dffhi                   : OUT std_logic;
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    --devclrn                 : IN std_logic := '1';
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    --devpor                  : IN std_logic := '1'
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  );
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end component;
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component stratixiii_pseudo_diff_out is
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  generic (
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    lpm_type        :  string := "stratixiii_pseudo_diff_out"
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  );
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  port (
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    i                       : in std_logic := '0';
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    o                       : out std_logic;
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    obar                    : out std_logic
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  );
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end component;
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component  stratixiii_io_obuf
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  generic(
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    bus_hold    :       string := "false";
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    open_drain_output   :       string := "false";
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    shift_series_termination_control    :       string := "false";
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    lpm_type    :       string := "stratixiii_io_obuf"
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  );
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  port(
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    dynamicterminationcontrol   :       in std_logic := '0';
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    i   :       in std_logic := '0';
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    o   :       out std_logic;
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    obar        :       out std_logic;
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    oe  :       in std_logic := '1'--;
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    --parallelterminationcontrol        :       in std_logic_vector(13 downto 0) := (others => '0');
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    --seriesterminationcontrol  :       in std_logic_vector(13 downto 0) := (others => '0')
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  );
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end component;
98 
 
99 
signal vcc      : std_logic;
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signal gnd      : std_logic_vector(13 downto 0);
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signal dqs_reg, dqs_buf, dqsn_buf : std_logic;
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signal dqs_oe_reg, dqs_oe_reg_n, dqs_oct_reg : std_logic;
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signal dqsn_oe_reg, dqsn_oe_reg_n, dqsn_oct_reg : std_logic;
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begin
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  vcc <= '1'; gnd <= (others => '0');
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-- DQS output register --------------------------------------------------------------
108 
 
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  dqs_reg0 : stratixiii_ddio_out
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    generic map(
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      power_up               => "high",
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      async_mode             => "none",
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      sync_mode              => "none",
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      half_rate_mode         => "false",
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      use_new_clocking_model => "false",
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      lpm_type               => "stratixiii_ddio_out"
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    )
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    port map(
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      datainlo => gnd(0),
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      datainhi => dqs,
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      clk      => clk,
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      clkhi    => clk,
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      clklo    => clk,
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      muxsel   => clk,
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      ena      => vcc,
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      areset   => gnd(0),
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      sreset   => gnd(0),
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      dataout  => dqs_reg--,
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      --dfflo    => open,
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      --dffhi    => open,
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      --devclrn  => vcc,
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      --devpor   => vcc
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    );
134 
 
135 
  pseudo_diff0 : stratixiii_pseudo_diff_out
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    port map(
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      i     => dqs_reg,
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      o     => dqs_buf,
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      obar  => dqsn_buf
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    );
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-- Outout enable and oct for DQS, DQSN ----------------------------------------------
143 
 
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  dqs_oe_reg0 : stratixiii_ddio_oe
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    generic map(
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      power_up    => "low",
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      async_mode  => "none",
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      sync_mode   => "none",
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      lpm_type    => "stratixiii_ddio_oe"
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    )
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    port map(
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      oe        => dqs_oe,
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      clk       => clk,
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      ena       => vcc,
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      areset    => gnd(0),
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      sreset    => gnd(0),
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      dataout   => dqs_oe_reg--,
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      --dfflo   => open,
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      --dffhi   => open,
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      --devclrn => vcc,
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      --devpor  => vcc
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    );
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  dqs_oe_reg_n <= not dqs_oe_reg;
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  dqs_oct_reg0 : stratixiii_ddio_oe
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    generic map(
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      power_up    => "low",
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      async_mode  => "none",
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      sync_mode   => "none",
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      lpm_type    => "stratixiii_ddio_oe"
171 
    )
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    port map(
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      oe        => dqs_oct,
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      clk       => clk,
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      ena       => vcc,
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      areset    => gnd(0),
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      sreset    => gnd(0),
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      dataout   => dqs_oct_reg--,
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      --dfflo   => open,
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      --dffhi   => open,
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      --devclrn => vcc,
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      --devpor  => vcc
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    );
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  dqsn_oe_reg0 : stratixiii_ddio_oe
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    generic map(
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      power_up    => "low",
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      async_mode  => "none",
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      sync_mode   => "none",
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      lpm_type    => "stratixiii_ddio_oe"
191 
    )
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    port map(
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      oe        => dqs_oe,
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      clk       => clk,
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      ena       => vcc,
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      areset    => gnd(0),
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      sreset    => gnd(0),
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      dataout   => dqsn_oe_reg--,
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      --dfflo   => open,
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      --dffhi   => open,
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      --devclrn => vcc,
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      --devpor  => vcc
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    );
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  dqsn_oe_reg_n <= not dqsn_oe_reg;
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  dqsn_oct_reg0 : stratixiii_ddio_oe
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    generic map(
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      power_up    => "low",
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      async_mode  => "none",
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      sync_mode   => "none",
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      lpm_type    => "stratixiii_ddio_oe"
212 
    )
213 
    port map(
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      oe        => dqs_oct,
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      clk       => clk,
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      ena       => vcc,
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      areset    => gnd(0),
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      sreset    => gnd(0),
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      dataout   => dqsn_oct_reg--,
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      --dfflo   => open,
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      --dffhi   => open,
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      --devclrn => vcc,
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      --devpor  => vcc
224 
    );
225 
 
226 
-- Out buffer (DQS, DQSN) -----------------------------------------------------------
227 
 
228 
  dqs_buf0 : stratixiii_io_obuf
229 
    generic map(
230 
      open_drain_output                => "false",
231 
      shift_series_termination_control => "false",
232 
      bus_hold                         => "false",
233 
      lpm_type                         => "stratixiii_io_obuf"
234 
    )
235 
    port map(
236 
      i                          => dqs_buf,
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      oe                         => dqs_oe_reg_n,
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      dynamicterminationcontrol  => gnd(0),--dqs_oct_reg,
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      --seriesterminationcontrol   => gnd,
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      --parallelterminationcontrol => gnd,
241 
      o                          => dqs_pad,
242 
      obar                       => open
243 
    );
244 
 
245 
  dqsn_buf0 : stratixiii_io_obuf
246 
    generic map(
247 
      open_drain_output                => "false",
248 
      shift_series_termination_control => "false",
249 
      bus_hold                         => "false",
250 
      lpm_type                         => "stratixiii_io_obuf"
251 
    )
252 
    port map(
253 
      i                          => dqsn_buf,
254 
      oe                         => dqsn_oe_reg_n,
255 
      dynamicterminationcontrol  => gnd(0),--dqsn_oct_reg,
256 
      --seriesterminationcontrol   => gnd,
257 
      --parallelterminationcontrol => gnd,
258 
      o                          => dqsn_pad,
259 
      obar                       => open
260 
    );
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end;

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