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dimamali |
LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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LIBRARY altera_mf;
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USE altera_mf.all;
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ENTITY apll IS
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generic (
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freq : integer := 200;
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mult : integer := 8;
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div : integer := 5;
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rskew : integer := 0
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);
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PORT
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(
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areset : IN STD_LOGIC := '0';
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inclk0 : IN STD_LOGIC := '0';
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phasestep : IN STD_LOGIC := '0';
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phaseupdown : IN STD_LOGIC := '0';
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scanclk : IN STD_LOGIC := '1';
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c0 : OUT STD_LOGIC ;
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c1 : OUT STD_LOGIC ;
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c2 : OUT STD_LOGIC ;
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c3 : OUT STD_LOGIC ;
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c4 : OUT STD_LOGIC ;
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locked : OUT STD_LOGIC;
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phasedone : OUT STD_LOGIC
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);
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END apll;
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ARCHITECTURE SYN OF apll IS
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SIGNAL sub_wire0 : STD_LOGIC_VECTOR (9 DOWNTO 0);
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SIGNAL sub_wire1 : STD_LOGIC ;
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SIGNAL sub_wire2 : STD_LOGIC ;
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SIGNAL sub_wire3 : STD_LOGIC ;
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SIGNAL sub_wire4 : STD_LOGIC ;
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SIGNAL sub_wire5 : STD_LOGIC ;
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SIGNAL sub_wire6 : STD_LOGIC ;
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SIGNAL sub_wire7 : STD_LOGIC ;
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SIGNAL sub_wire8 : STD_LOGIC_VECTOR (1 DOWNTO 0);
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SIGNAL sub_wire9_bv : BIT_VECTOR (0 DOWNTO 0);
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SIGNAL sub_wire9 : STD_LOGIC_VECTOR (0 DOWNTO 0);
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signal phasecounter_reg : std_logic_vector(3 downto 0);
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attribute syn_keep : boolean;
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attribute syn_keep of phasecounter_reg : signal is true;
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attribute syn_preserve : boolean;
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attribute syn_preserve of phasecounter_reg : signal is true;
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constant period : integer := 1000000/freq;
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function set_phase(freq : in integer) return string is
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variable s : string(1 to 4) := "0000";
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variable f,r : integer;
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begin
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f := freq;
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while f /= 0 loop
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r := f mod 10;
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case r is
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when 0 => s := "0" & s(1 to 3);
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when 1 => s := "1" & s(1 to 3);
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when 2 => s := "2" & s(1 to 3);
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when 3 => s := "3" & s(1 to 3);
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when 4 => s := "4" & s(1 to 3);
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when 5 => s := "5" & s(1 to 3);
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when 6 => s := "6" & s(1 to 3);
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when 7 => s := "7" & s(1 to 3);
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when 8 => s := "8" & s(1 to 3);
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when 9 => s := "9" & s(1 to 3);
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when others =>
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end case;
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f := f / 10;
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end loop;
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return s;
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end function;
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type phasevec is array (1 to 3) of string(1 to 4);
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type phasevecarr is array (10 to 21) of phasevec;
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constant phasearr : phasevecarr := (
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("2500", "5000", "7500"), ("2273", "4545", "6818"), -- 100 & 110 MHz
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("2083", "4167", "6250"), ("1923", "3846", "5769"), -- 120 & 130 MHz
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("1786", "3571", "5357"), ("1667", "3333", "5000"), -- 140 & 150 MHz
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("1563", "3125", "4688"), ("1471", "2941", "4412"), -- 160 & 170 MHz
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("1389", "2778", "4167"), ("1316", "2632", "3947"), -- 180 & 190 MHz
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("1250", "2500", "3750"), ("1190", "2381", "3571")); -- 200 & 210 MHz
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--constant pshift_90 : string := phasearr((freq*mult)/(10*div))(1);
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constant pshift_90 : string := set_phase(100000/((4*freq*mult)/(10*div)));
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--constant pshift_180 : string := phasearr((freq*mult)/(10*div))(2);
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constant pshift_180 : string := set_phase(100000/((2*freq*mult)/(10*div)));
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--constant pshift_270 : string := phasearr((freq*mult)/(10*div))(3);
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constant pshift_270 : string := set_phase(300000/((4*freq*mult)/(10*div)));
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constant pshift_rclk : string := set_phase(rskew);
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COMPONENT altpll
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GENERIC (
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bandwidth_type : STRING;
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clk0_divide_by : NATURAL;
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clk0_duty_cycle : NATURAL;
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clk0_multiply_by : NATURAL;
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clk0_phase_shift : STRING;
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clk1_divide_by : NATURAL;
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clk1_duty_cycle : NATURAL;
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clk1_multiply_by : NATURAL;
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clk1_phase_shift : STRING;
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clk2_divide_by : NATURAL;
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clk2_duty_cycle : NATURAL;
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clk2_multiply_by : NATURAL;
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clk2_phase_shift : STRING;
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clk3_divide_by : NATURAL;
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clk3_duty_cycle : NATURAL;
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clk3_multiply_by : NATURAL;
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clk3_phase_shift : STRING;
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clk4_divide_by : NATURAL;
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clk4_duty_cycle : NATURAL;
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clk4_multiply_by : NATURAL;
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clk4_phase_shift : STRING;
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compensate_clock : STRING;
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inclk0_input_frequency : NATURAL;
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intended_device_family : STRING;
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lpm_hint : STRING;
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lpm_type : STRING;
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operation_mode : STRING;
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pll_type : STRING;
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port_activeclock : STRING;
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port_areset : STRING;
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port_clkbad0 : STRING;
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port_clkbad1 : STRING;
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port_clkloss : STRING;
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port_clkswitch : STRING;
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port_configupdate : STRING;
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port_fbin : STRING;
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port_fbout : STRING;
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port_inclk0 : STRING;
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port_inclk1 : STRING;
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port_locked : STRING;
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port_pfdena : STRING;
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port_phasecounterselect : STRING;
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port_phasedone : STRING;
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port_phasestep : STRING;
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port_phaseupdown : STRING;
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port_pllena : STRING;
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port_scanaclr : STRING;
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port_scanclk : STRING;
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port_scanclkena : STRING;
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port_scandata : STRING;
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port_scandataout : STRING;
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port_scandone : STRING;
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port_scanread : STRING;
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port_scanwrite : STRING;
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port_clk0 : STRING;
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port_clk1 : STRING;
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port_clk2 : STRING;
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port_clk3 : STRING;
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port_clk4 : STRING;
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port_clk5 : STRING;
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port_clk6 : STRING;
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port_clk7 : STRING;
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port_clk8 : STRING;
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port_clk9 : STRING;
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port_clkena0 : STRING;
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port_clkena1 : STRING;
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port_clkena2 : STRING;
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port_clkena3 : STRING;
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port_clkena4 : STRING;
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port_clkena5 : STRING;
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self_reset_on_loss_lock : STRING;
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using_fbmimicbidir_port : STRING;
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width_clock : NATURAL
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);
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PORT (
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phasestep : IN STD_LOGIC ;
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phaseupdown : IN STD_LOGIC ;
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inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
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phasecounterselect : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
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locked : OUT STD_LOGIC ;
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phasedone : OUT STD_LOGIC ;
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areset : IN STD_LOGIC ;
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clk : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
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scanclk : IN STD_LOGIC
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);
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END COMPONENT;
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BEGIN
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sub_wire9_bv(0 DOWNTO 0) <= "0";
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sub_wire9 <= To_stdlogicvector(sub_wire9_bv);
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sub_wire5 <= sub_wire0(4);
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sub_wire4 <= sub_wire0(3);
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sub_wire3 <= sub_wire0(2);
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sub_wire2 <= sub_wire0(1);
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sub_wire1 <= sub_wire0(0);
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c0 <= sub_wire1;
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c1 <= sub_wire2;
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c2 <= sub_wire3;
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c3 <= sub_wire4;
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c4 <= sub_wire5;
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locked <= sub_wire6;
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sub_wire7 <= inclk0;
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sub_wire8 <= sub_wire9(0 DOWNTO 0) & sub_wire7;
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-- quartus bug, cant be constant
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process(scanclk)
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begin
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if rising_edge(scanclk) then
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phasecounter_reg <= "0110"; --phasecounter;
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end if;
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end process;
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altpll_component : altpll
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GENERIC MAP (
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bandwidth_type => "AUTO",
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clk0_divide_by => div,--5,
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clk0_duty_cycle => 50,
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clk0_multiply_by => mult,--8,
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clk0_phase_shift => "0",
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clk1_divide_by => div,--5,
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clk1_duty_cycle => 50,
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clk1_multiply_by => mult,--8,
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clk1_phase_shift => pshift_90,--"1250",
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clk2_divide_by => div,--5,
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clk2_duty_cycle => 50,
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clk2_multiply_by => mult,--8,
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clk2_phase_shift => pshift_180,--"2500",
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clk3_divide_by => div,--5,
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clk3_duty_cycle => 50,
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clk3_multiply_by => mult,--8,
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clk3_phase_shift => pshift_270,--"3750",
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clk4_divide_by => div,
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clk4_duty_cycle => 50,
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clk4_multiply_by => mult,
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clk4_phase_shift => pshift_rclk,--"0",
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compensate_clock => "CLK0",
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inclk0_input_frequency => period,--8000,
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intended_device_family => "Stratix III",
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lpm_hint => "CBX_MODULE_PREFIX=apll",
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lpm_type => "altpll",
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operation_mode => "NORMAL",
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pll_type => "AUTO",
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port_activeclock => "PORT_UNUSED",
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port_areset => "PORT_USED",
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port_clkbad0 => "PORT_UNUSED",
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port_clkbad1 => "PORT_UNUSED",
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port_clkloss => "PORT_UNUSED",
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port_clkswitch => "PORT_UNUSED",
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port_configupdate => "PORT_UNUSED",
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port_fbin => "PORT_UNUSED",
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port_fbout => "PORT_UNUSED",
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port_inclk0 => "PORT_USED",
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port_inclk1 => "PORT_UNUSED",
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port_locked => "PORT_USED",
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port_pfdena => "PORT_UNUSED",
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port_phasecounterselect => "PORT_USED",
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port_phasedone => "PORT_USED",
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port_phasestep => "PORT_USED",
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port_phaseupdown => "PORT_USED",
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port_pllena => "PORT_UNUSED",
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port_scanaclr => "PORT_UNUSED",
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port_scanclk => "PORT_USED",
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port_scanclkena => "PORT_UNUSED",
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port_scandata => "PORT_UNUSED",
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port_scandataout => "PORT_UNUSED",
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port_scandone => "PORT_UNUSED",
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port_scanread => "PORT_UNUSED",
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port_scanwrite => "PORT_UNUSED",
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port_clk0 => "PORT_USED",
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port_clk1 => "PORT_USED",
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port_clk2 => "PORT_USED",
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port_clk3 => "PORT_USED",
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port_clk4 => "PORT_USED",
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port_clk5 => "PORT_UNUSED",
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port_clk6 => "PORT_UNUSED",
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port_clk7 => "PORT_UNUSED",
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port_clk8 => "PORT_UNUSED",
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port_clk9 => "PORT_UNUSED",
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port_clkena0 => "PORT_UNUSED",
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port_clkena1 => "PORT_UNUSED",
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port_clkena2 => "PORT_UNUSED",
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port_clkena3 => "PORT_UNUSED",
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port_clkena4 => "PORT_UNUSED",
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port_clkena5 => "PORT_UNUSED",
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self_reset_on_loss_lock => "ON",
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using_fbmimicbidir_port => "OFF",
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width_clock => 10
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)
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PORT MAP (
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phasestep => phasestep,
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phaseupdown => phaseupdown,
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inclk => sub_wire8,
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phasecounterselect => phasecounter_reg,
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areset => areset,
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scanclk => scanclk,
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clk => sub_wire0,
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locked => sub_wire6,
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phasedone => phasedone
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);
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END SYN;
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