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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [lib/] [techmap/] [unisim/] [grspwc_unisim.vhd] - Blame information for rev 2

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------------------------------------------------------------------------------
--  This file is a part of the GRLIB VHDL IP LIBRARY
--  Copyright (C) 2003, Gaisler Research
--
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License as published by
--  the Free Software Foundation; either version 2 of the License, or
--  (at your option) any later version.
--
--  This program is distributed in the hope that it will be useful,
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--  GNU General Public License for more details.
--
--  You should have received a copy of the GNU General Public License
--  along with this program; if not, write to the Free Software
--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
-----------------------------------------------------------------------------
-- Entity:      grspwc_unisim
-- File:        grspwc_unisim.vhd
-- Author:      Jiri Gaisler - Gaisler Research 
-- Description: tech wrapper for xilinx/unisim grspwc netlist
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.all;
 
entity grspwc_unisim is
  generic(
    sysfreq      : integer := 40000;
    usegen       : integer range 0 to 1  := 1;
    nsync        : integer range 1 to 2  := 1;
    rmap         : integer range 0 to 1  := 0;
    rmapcrc      : integer range 0 to 1  := 0;
    fifosize1    : integer range 4 to 32 := 32;
    fifosize2    : integer range 16 to 64 := 64;
    rxunaligned  : integer range 0 to 1 := 0;
    rmapbufs     : integer range 2 to 8 := 4;
    scantest     : integer range 0 to 1 := 0
  );
  port(
    rst          : in  std_ulogic;
    clk          : in  std_ulogic;
    txclk        : in  std_ulogic;
    --ahb mst in
    hgrant       : in  std_ulogic;
    hready       : in  std_ulogic;
    hresp        : in  std_logic_vector(1 downto 0);
    hrdata       : in  std_logic_vector(31 downto 0);
    --ahb mst out
    hbusreq      : out  std_ulogic;
    hlock        : out  std_ulogic;
    htrans       : out  std_logic_vector(1 downto 0);
    haddr        : out  std_logic_vector(31 downto 0);
    hwrite       : out  std_ulogic;
    hsize        : out  std_logic_vector(2 downto 0);
    hburst       : out  std_logic_vector(2 downto 0);
    hprot        : out  std_logic_vector(3 downto 0);
    hwdata       : out  std_logic_vector(31 downto 0);
    --apb slv in 
    psel         : in   std_ulogic;
    penable      : in   std_ulogic;
    paddr        : in   std_logic_vector(31 downto 0);
    pwrite       : in   std_ulogic;
    pwdata       : in   std_logic_vector(31 downto 0);
    --apb slv out
    prdata       : out  std_logic_vector(31 downto 0);
    di           : in std_logic_vector(1 downto 0);
    si           : in std_logic_vector(1 downto 0);
    do           : out std_logic_vector(1 downto 0);
    so           : out std_logic_vector(1 downto 0);
    --time iface
    tickin       : in   std_ulogic;
    tickout      : out  std_ulogic;
    --irq
    irq          : out  std_logic;
    --misc     
    clkdiv10     : in   std_logic_vector(7 downto 0);
    dcrstval     : in   std_logic_vector(9 downto 0);
    timerrstval  : in   std_logic_vector(11 downto 0);
    --rmapen
    rmapen       : in   std_ulogic;
    --clk bufs
    rxclki       : in std_logic_vector(1 downto 0);
    nrxclki      : in std_logic_vector(1 downto 0);
    rxclko       : out std_logic_vector(1 downto 0);
    --rx ahb fifo
    rxrenable    : out  std_ulogic;
    rxraddress   : out  std_logic_vector(4 downto 0);
    rxwrite      : out  std_ulogic;
    rxwdata      : out  std_logic_vector(31 downto 0);
    rxwaddress   : out  std_logic_vector(4 downto 0);
    rxrdata      : in   std_logic_vector(31 downto 0);
    --tx ahb fifo
    txrenable    : out  std_ulogic;
    txraddress   : out  std_logic_vector(4 downto 0);
    txwrite      : out  std_ulogic;
    txwdata      : out  std_logic_vector(31 downto 0);
    txwaddress   : out  std_logic_vector(4 downto 0);
    txrdata      : in   std_logic_vector(31 downto 0);
    --nchar fifo
    ncrenable    : out  std_ulogic;
    ncraddress   : out  std_logic_vector(5 downto 0);
    ncwrite      : out  std_ulogic;
    ncwdata      : out  std_logic_vector(8 downto 0);
    ncwaddress   : out  std_logic_vector(5 downto 0);
    ncrdata      : in   std_logic_vector(8 downto 0);
    --rmap buf
    rmrenable    : out  std_ulogic;
    rmraddress   : out  std_logic_vector(7 downto 0);
    rmwrite      : out  std_ulogic;
    rmwdata      : out  std_logic_vector(7 downto 0);
    rmwaddress   : out  std_logic_vector(7 downto 0);
    rmrdata      : in   std_logic_vector(7 downto 0);
    linkdis      : out  std_ulogic;
    testclk      : in   std_ulogic := '0';
    testrst      : in   std_ulogic := '0';
    testen       : in   std_ulogic := '0'
  );
end entity;
 
architecture rtl of grspwc_unisim is
 
component grspwc_unisim_16_16 is
port(
  rst :  in std_logic;
  clk :  in std_logic;
  txclk :  in std_logic;
  hgrant :  in std_logic;
  hready :  in std_logic;
  hresp : in std_logic_vector(1 downto 0);
  hrdata : in std_logic_vector(31 downto 0);
  hbusreq :  out std_logic;
  hlock :  out std_logic;
  htrans : out std_logic_vector(1 downto 0);
  haddr : out std_logic_vector(31 downto 0);
  hwrite :  out std_logic;
  hsize : out std_logic_vector(2 downto 0);
  hburst : out std_logic_vector(2 downto 0);
  hprot : out std_logic_vector(3 downto 0);
  hwdata : out std_logic_vector(31 downto 0);
  psel :  in std_logic;
  penable :  in std_logic;
  paddr : in std_logic_vector(31 downto 0);
  pwrite :  in std_logic;
  pwdata : in std_logic_vector(31 downto 0);
  prdata : out std_logic_vector(31 downto 0);
  di : in std_logic_vector(1 downto 0);
  si : in std_logic_vector(1 downto 0);
  do : out std_logic_vector(1 downto 0);
  so : out std_logic_vector(1 downto 0);
  tickin :  in std_logic;
  tickout :  out std_logic;
  irq :  out std_logic;
  clkdiv10 : in std_logic_vector(7 downto 0);
  dcrstval : in std_logic_vector(9 downto 0);
  timerrstval : in std_logic_vector(11 downto 0);
  rmapen :  in std_logic;
  rxclki : in std_logic_vector(1 downto 0);
  nrxclki : in std_logic_vector(1 downto 0);
  rxclko : out std_logic_vector(1 downto 0);
  rxrenable :  out std_logic;
  rxraddress : out std_logic_vector(4 downto 0);
  rxwrite :  out std_logic;
  rxwdata : out std_logic_vector(31 downto 0);
  rxwaddress : out std_logic_vector(4 downto 0);
  rxrdata : in std_logic_vector(31 downto 0);
  txrenable :  out std_logic;
  txraddress : out std_logic_vector(4 downto 0);
  txwrite :  out std_logic;
  txwdata : out std_logic_vector(31 downto 0);
  txwaddress : out std_logic_vector(4 downto 0);
  txrdata : in std_logic_vector(31 downto 0);
  ncrenable :  out std_logic;
  ncraddress : out std_logic_vector(5 downto 0);
  ncwrite :  out std_logic;
  ncwdata : out std_logic_vector(8 downto 0);
  ncwaddress : out std_logic_vector(5 downto 0);
  ncrdata : in std_logic_vector(8 downto 0);
  rmrenable :  out std_logic;
  rmraddress : out std_logic_vector(7 downto 0);
  rmwrite :  out std_logic;
  rmwdata : out std_logic_vector(7 downto 0);
  rmwaddress : out std_logic_vector(7 downto 0);
  rmrdata : in std_logic_vector(7 downto 0);
  linkdis :  out std_logic;
  testclk :  in std_logic;
  testrst :  in std_logic;
  testen :  in std_logic);
end component;
 
component grspwc_unisim_rmap_16_16
port(
  rst :  in std_logic;
  clk :  in std_logic;
  txclk :  in std_logic;
  hgrant :  in std_logic;
  hready :  in std_logic;
  hresp : in std_logic_vector(1 downto 0);
  hrdata : in std_logic_vector(31 downto 0);
  hbusreq :  out std_logic;
  hlock :  out std_logic;
  htrans : out std_logic_vector(1 downto 0);
  haddr : out std_logic_vector(31 downto 0);
  hwrite :  out std_logic;
  hsize : out std_logic_vector(2 downto 0);
  hburst : out std_logic_vector(2 downto 0);
  hprot : out std_logic_vector(3 downto 0);
  hwdata : out std_logic_vector(31 downto 0);
  psel :  in std_logic;
  penable :  in std_logic;
  paddr : in std_logic_vector(31 downto 0);
  pwrite :  in std_logic;
  pwdata : in std_logic_vector(31 downto 0);
  prdata : out std_logic_vector(31 downto 0);
  di : in std_logic_vector(1 downto 0);
  si : in std_logic_vector(1 downto 0);
  do : out std_logic_vector(1 downto 0);
  so : out std_logic_vector(1 downto 0);
  tickin :  in std_logic;
  tickout :  out std_logic;
  irq :  out std_logic;
  clkdiv10 : in std_logic_vector(7 downto 0);
  dcrstval : in std_logic_vector(9 downto 0);
  timerrstval : in std_logic_vector(11 downto 0);
  rmapen :  in std_logic;
  rxclki : in std_logic_vector(1 downto 0);
  nrxclki : in std_logic_vector(1 downto 0);
  rxclko : out std_logic_vector(1 downto 0);
  rxrenable :  out std_logic;
  rxraddress : out std_logic_vector(4 downto 0);
  rxwrite :  out std_logic;
  rxwdata : out std_logic_vector(31 downto 0);
  rxwaddress : out std_logic_vector(4 downto 0);
  rxrdata : in std_logic_vector(31 downto 0);
  txrenable :  out std_logic;
  txraddress : out std_logic_vector(4 downto 0);
  txwrite :  out std_logic;
  txwdata : out std_logic_vector(31 downto 0);
  txwaddress : out std_logic_vector(4 downto 0);
  txrdata : in std_logic_vector(31 downto 0);
  ncrenable :  out std_logic;
  ncraddress : out std_logic_vector(5 downto 0);
  ncwrite :  out std_logic;
  ncwdata : out std_logic_vector(8 downto 0);
  ncwaddress : out std_logic_vector(5 downto 0);
  ncrdata : in std_logic_vector(8 downto 0);
  rmrenable :  out std_logic;
  rmraddress : out std_logic_vector(7 downto 0);
  rmwrite :  out std_logic;
  rmwdata : out std_logic_vector(7 downto 0);
  rmwaddress : out std_logic_vector(7 downto 0);
  rmrdata : in std_logic_vector(7 downto 0);
  linkdis :  out std_logic;
  testclk :  in std_logic;
  testrst :  in std_logic;
  testen :  in std_logic);
end component;
 
begin
 
f16_16 : if (fifosize1 = 16) and (fifosize2 = 16) and (rmap = 0) generate
    grspwc0 : grspwc_unisim_16_16
    port map(
      rst          => rst,
      clk          => clk,
      txclk        => txclk,
      --ahb mst in
      hgrant       => hgrant,
      hready       => hready,
      hresp        => hresp,
      hrdata       => hrdata,
      --ahb mst out
      hbusreq      => hbusreq,
      hlock        => hlock,
      htrans       => htrans,
      haddr        => haddr,
      hwrite       => hwrite,
      hsize        => hsize,
      hburst       => hburst,
      hprot        => hprot,
      hwdata       => hwdata,
      --apb slv in 
      psel         => psel,
      penable      => penable,
      paddr        => paddr,
      pwrite       => pwrite,
      pwdata       => pwdata,
      --apb slv out
      prdata       => prdata,
      --spw in
      di           => di,
      si           => si,
      --spw out
      do           => do,
      so           => so,
      --time iface
      tickin       => tickin,
      tickout      => tickout,
      --clk bufs
      rxclki       => rxclki,
      nrxclki      => nrxclki,
      rxclko       => rxclko,
      --irq
      irq          => irq,
      --misc     
      clkdiv10     => clkdiv10,
      dcrstval     => dcrstval,
      timerrstval  => timerrstval,
      --rmapen    
      rmapen       => rmapen,
      --rx ahb fifo
      rxrenable    => rxrenable,
      rxraddress   => rxraddress,
      rxwrite      => rxwrite,
      rxwdata      => rxwdata,
      rxwaddress   => rxwaddress,
      rxrdata      => rxrdata,
      --tx ahb fifo
      txrenable    => txrenable,
      txraddress   => txraddress,
      txwrite      => txwrite,
      txwdata      => txwdata,
      txwaddress   => txwaddress,
      txrdata      => txrdata,
      --nchar fifo
      ncrenable    => ncrenable,
      ncraddress   => ncraddress,
      ncwrite      => ncwrite,
      ncwdata      => ncwdata,
      ncwaddress   => ncwaddress,
      ncrdata      => ncrdata,
      --rmap buf
      rmrenable    => rmrenable,
      rmraddress   => rmraddress,
      rmwrite      => rmwrite,
      rmwdata      => rmwdata,
      rmwaddress   => rmwaddress,
      rmrdata      => rmrdata,
      linkdis      => linkdis,
      testclk      => testclk,
      testrst      => testrst,
      testen       => testen
      );
end generate;
 
rmap_f16_16 : if (fifosize1 = 16) and (fifosize2 = 16) and (rmap /= 0) generate
    grspwc0 : grspwc_unisim_rmap_16_16
    port map(
      rst          => rst,
      clk          => clk,
      txclk        => txclk,
      --ahb mst in
      hgrant       => hgrant,
      hready       => hready,
      hresp        => hresp,
      hrdata       => hrdata,
      --ahb mst out
      hbusreq      => hbusreq,
      hlock        => hlock,
      htrans       => htrans,
      haddr        => haddr,
      hwrite       => hwrite,
      hsize        => hsize,
      hburst       => hburst,
      hprot        => hprot,
      hwdata       => hwdata,
      --apb slv in 
      psel         => psel,
      penable      => penable,
      paddr        => paddr,
      pwrite       => pwrite,
      pwdata       => pwdata,
      --apb slv out
      prdata       => prdata,
      --spw in
      di           => di,
      si           => si,
      --spw out
      do           => do,
      so           => so,
      --time iface
      tickin       => tickin,
      tickout      => tickout,
      --clk bufs
      rxclki       => rxclki,
      nrxclki      => nrxclki,
      rxclko       => rxclko,
      --irq
      irq          => irq,
      --misc     
      clkdiv10     => clkdiv10,
      dcrstval     => dcrstval,
      timerrstval  => timerrstval,
      --rmapen    
      rmapen       => rmapen,
      --rx ahb fifo
      rxrenable    => rxrenable,
      rxraddress   => rxraddress,
      rxwrite      => rxwrite,
      rxwdata      => rxwdata,
      rxwaddress   => rxwaddress,
      rxrdata      => rxrdata,
      --tx ahb fifo
      txrenable    => txrenable,
      txraddress   => txraddress,
      txwrite      => txwrite,
      txwdata      => txwdata,
      txwaddress   => txwaddress,
      txrdata      => txrdata,
      --nchar fifo
      ncrenable    => ncrenable,
      ncraddress   => ncraddress,
      ncwrite      => ncwrite,
      ncwdata      => ncwdata,
      ncwaddress   => ncwaddress,
      ncrdata      => ncrdata,
      --rmap buf
      rmrenable    => rmrenable,
      rmraddress   => rmraddress,
      rmwrite      => rmwrite,
      rmwdata      => rmwdata,
      rmwaddress   => rmwaddress,
      rmrdata      => rmrdata,
      linkdis      => linkdis,
      testclk      => testclk,
      testrst      => testrst,
      testen       => testen
      );
end generate;
 
-- pragma translate_off
 
nomap : if not ((fifosize1 = 16) and (fifosize2 = 16)) generate
 
  err : process
  begin
    assert false report "ERROR : AHB and RX fifos must be 16!"
    severity failure;
    wait;
  end process;
 
end generate;
 
-- pragma translate_on
 
end architecture;

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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [lib/] [techmap/] [unisim/] [grspwc_unisim.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	dimamali	`------------------------------------------------------------------------------`
2			`-- This file is a part of the GRLIB VHDL IP LIBRARY`
3			`-- Copyright (C) 2003, Gaisler Research`
4			`--`
5			`-- This program is free software; you can redistribute it and/or modify`
6			`-- it under the terms of the GNU General Public License as published by`
7			`-- the Free Software Foundation; either version 2 of the License, or`
8			`-- (at your option) any later version.`
9			`--`
10			`-- This program is distributed in the hope that it will be useful,`
11			`-- but WITHOUT ANY WARRANTY; without even the implied warranty of`
12			`-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
13			`-- GNU General Public License for more details.`
14			`--`
15			`-- You should have received a copy of the GNU General Public License`
16			`-- along with this program; if not, write to the Free Software`
17			`-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA`
18			`-----------------------------------------------------------------------------`
19			`-- Entity: grspwc_unisim`
20			`-- File: grspwc_unisim.vhd`
21			`-- Author: Jiri Gaisler - Gaisler Research`
22			`-- Description: tech wrapper for xilinx/unisim grspwc netlist`
23			`------------------------------------------------------------------------------`
24			`library ieee;`
25			`use ieee.std_logic_1164.all;`
26			`library unisim;`
27			`use unisim.all;`
28
29			`entity grspwc_unisim is`
30			`generic(`
31			`sysfreq : integer := 40000;`
32			`usegen : integer range 0 to 1 := 1;`
33			`nsync : integer range 1 to 2 := 1;`
34			`rmap : integer range 0 to 1 := 0;`
35			`rmapcrc : integer range 0 to 1 := 0;`
36			`fifosize1 : integer range 4 to 32 := 32;`
37			`fifosize2 : integer range 16 to 64 := 64;`
38			`rxunaligned : integer range 0 to 1 := 0;`
39			`rmapbufs : integer range 2 to 8 := 4;`
40			`scantest : integer range 0 to 1 := 0`
41			`);`
42			`port(`
43			`rst : in std_ulogic;`
44			`clk : in std_ulogic;`
45			`txclk : in std_ulogic;`
46			`--ahb mst in`
47			`hgrant : in std_ulogic;`
48			`hready : in std_ulogic;`
49			`hresp : in std_logic_vector(1 downto 0);`
50			`hrdata : in std_logic_vector(31 downto 0);`
51			`--ahb mst out`
52			`hbusreq : out std_ulogic;`
53			`hlock : out std_ulogic;`
54			`htrans : out std_logic_vector(1 downto 0);`
55			`haddr : out std_logic_vector(31 downto 0);`
56			`hwrite : out std_ulogic;`
57			`hsize : out std_logic_vector(2 downto 0);`
58			`hburst : out std_logic_vector(2 downto 0);`
59			`hprot : out std_logic_vector(3 downto 0);`
60			`hwdata : out std_logic_vector(31 downto 0);`
61			`--apb slv in`
62			`psel : in std_ulogic;`
63			`penable : in std_ulogic;`
64			`paddr : in std_logic_vector(31 downto 0);`
65			`pwrite : in std_ulogic;`
66			`pwdata : in std_logic_vector(31 downto 0);`
67			`--apb slv out`
68			`prdata : out std_logic_vector(31 downto 0);`
69			`di : in std_logic_vector(1 downto 0);`
70			`si : in std_logic_vector(1 downto 0);`
71			`do : out std_logic_vector(1 downto 0);`
72			`so : out std_logic_vector(1 downto 0);`
73			`--time iface`
74			`tickin : in std_ulogic;`
75			`tickout : out std_ulogic;`
76			`--irq`
77			`irq : out std_logic;`
78			`--misc`
79			`clkdiv10 : in std_logic_vector(7 downto 0);`
80			`dcrstval : in std_logic_vector(9 downto 0);`
81			`timerrstval : in std_logic_vector(11 downto 0);`
82			`--rmapen`
83			`rmapen : in std_ulogic;`
84			`--clk bufs`
85			`rxclki : in std_logic_vector(1 downto 0);`
86			`nrxclki : in std_logic_vector(1 downto 0);`
87			`rxclko : out std_logic_vector(1 downto 0);`
88			`--rx ahb fifo`
89			`rxrenable : out std_ulogic;`
90			`rxraddress : out std_logic_vector(4 downto 0);`
91			`rxwrite : out std_ulogic;`
92			`rxwdata : out std_logic_vector(31 downto 0);`
93			`rxwaddress : out std_logic_vector(4 downto 0);`
94			`rxrdata : in std_logic_vector(31 downto 0);`
95			`--tx ahb fifo`
96			`txrenable : out std_ulogic;`
97			`txraddress : out std_logic_vector(4 downto 0);`
98			`txwrite : out std_ulogic;`
99			`txwdata : out std_logic_vector(31 downto 0);`
100			`txwaddress : out std_logic_vector(4 downto 0);`
101			`txrdata : in std_logic_vector(31 downto 0);`
102			`--nchar fifo`
103			`ncrenable : out std_ulogic;`
104			`ncraddress : out std_logic_vector(5 downto 0);`
105			`ncwrite : out std_ulogic;`
106			`ncwdata : out std_logic_vector(8 downto 0);`
107			`ncwaddress : out std_logic_vector(5 downto 0);`
108			`ncrdata : in std_logic_vector(8 downto 0);`
109			`--rmap buf`
110			`rmrenable : out std_ulogic;`
111			`rmraddress : out std_logic_vector(7 downto 0);`
112			`rmwrite : out std_ulogic;`
113			`rmwdata : out std_logic_vector(7 downto 0);`
114			`rmwaddress : out std_logic_vector(7 downto 0);`
115			`rmrdata : in std_logic_vector(7 downto 0);`
116			`linkdis : out std_ulogic;`
117			`testclk : in std_ulogic := '0';`
118			`testrst : in std_ulogic := '0';`
119			`testen : in std_ulogic := '0'`
120			`);`
121			`end entity;`
122
123			`architecture rtl of grspwc_unisim is`
124
125			`component grspwc_unisim_16_16 is`
126			`port(`
127			`rst : in std_logic;`
128			`clk : in std_logic;`
129			`txclk : in std_logic;`
130			`hgrant : in std_logic;`
131			`hready : in std_logic;`
132			`hresp : in std_logic_vector(1 downto 0);`
133			`hrdata : in std_logic_vector(31 downto 0);`
134			`hbusreq : out std_logic;`
135			`hlock : out std_logic;`
136			`htrans : out std_logic_vector(1 downto 0);`
137			`haddr : out std_logic_vector(31 downto 0);`
138			`hwrite : out std_logic;`
139			`hsize : out std_logic_vector(2 downto 0);`
140			`hburst : out std_logic_vector(2 downto 0);`
141			`hprot : out std_logic_vector(3 downto 0);`
142			`hwdata : out std_logic_vector(31 downto 0);`
143			`psel : in std_logic;`
144			`penable : in std_logic;`
145			`paddr : in std_logic_vector(31 downto 0);`
146			`pwrite : in std_logic;`
147			`pwdata : in std_logic_vector(31 downto 0);`
148			`prdata : out std_logic_vector(31 downto 0);`
149			`di : in std_logic_vector(1 downto 0);`
150			`si : in std_logic_vector(1 downto 0);`
151			`do : out std_logic_vector(1 downto 0);`
152			`so : out std_logic_vector(1 downto 0);`
153			`tickin : in std_logic;`
154			`tickout : out std_logic;`
155			`irq : out std_logic;`
156			`clkdiv10 : in std_logic_vector(7 downto 0);`
157			`dcrstval : in std_logic_vector(9 downto 0);`
158			`timerrstval : in std_logic_vector(11 downto 0);`
159			`rmapen : in std_logic;`
160			`rxclki : in std_logic_vector(1 downto 0);`
161			`nrxclki : in std_logic_vector(1 downto 0);`
162			`rxclko : out std_logic_vector(1 downto 0);`
163			`rxrenable : out std_logic;`
164			`rxraddress : out std_logic_vector(4 downto 0);`
165			`rxwrite : out std_logic;`
166			`rxwdata : out std_logic_vector(31 downto 0);`
167			`rxwaddress : out std_logic_vector(4 downto 0);`
168			`rxrdata : in std_logic_vector(31 downto 0);`
169			`txrenable : out std_logic;`
170			`txraddress : out std_logic_vector(4 downto 0);`
171			`txwrite : out std_logic;`
172			`txwdata : out std_logic_vector(31 downto 0);`
173			`txwaddress : out std_logic_vector(4 downto 0);`
174			`txrdata : in std_logic_vector(31 downto 0);`
175			`ncrenable : out std_logic;`
176			`ncraddress : out std_logic_vector(5 downto 0);`
177			`ncwrite : out std_logic;`
178			`ncwdata : out std_logic_vector(8 downto 0);`
179			`ncwaddress : out std_logic_vector(5 downto 0);`
180			`ncrdata : in std_logic_vector(8 downto 0);`
181			`rmrenable : out std_logic;`
182			`rmraddress : out std_logic_vector(7 downto 0);`
183			`rmwrite : out std_logic;`
184			`rmwdata : out std_logic_vector(7 downto 0);`
185			`rmwaddress : out std_logic_vector(7 downto 0);`
186			`rmrdata : in std_logic_vector(7 downto 0);`
187			`linkdis : out std_logic;`
188			`testclk : in std_logic;`
189			`testrst : in std_logic;`
190			`testen : in std_logic);`
191			`end component;`
192
193			`component grspwc_unisim_rmap_16_16`
194			`port(`
195			`rst : in std_logic;`
196			`clk : in std_logic;`
197			`txclk : in std_logic;`
198			`hgrant : in std_logic;`
199			`hready : in std_logic;`
200			`hresp : in std_logic_vector(1 downto 0);`
201			`hrdata : in std_logic_vector(31 downto 0);`
202			`hbusreq : out std_logic;`
203			`hlock : out std_logic;`
204			`htrans : out std_logic_vector(1 downto 0);`
205			`haddr : out std_logic_vector(31 downto 0);`
206			`hwrite : out std_logic;`
207			`hsize : out std_logic_vector(2 downto 0);`
208			`hburst : out std_logic_vector(2 downto 0);`
209			`hprot : out std_logic_vector(3 downto 0);`
210			`hwdata : out std_logic_vector(31 downto 0);`
211			`psel : in std_logic;`
212			`penable : in std_logic;`
213			`paddr : in std_logic_vector(31 downto 0);`
214			`pwrite : in std_logic;`
215			`pwdata : in std_logic_vector(31 downto 0);`
216			`prdata : out std_logic_vector(31 downto 0);`
217			`di : in std_logic_vector(1 downto 0);`
218			`si : in std_logic_vector(1 downto 0);`
219			`do : out std_logic_vector(1 downto 0);`
220			`so : out std_logic_vector(1 downto 0);`
221			`tickin : in std_logic;`
222			`tickout : out std_logic;`
223			`irq : out std_logic;`
224			`clkdiv10 : in std_logic_vector(7 downto 0);`
225			`dcrstval : in std_logic_vector(9 downto 0);`
226			`timerrstval : in std_logic_vector(11 downto 0);`
227			`rmapen : in std_logic;`
228			`rxclki : in std_logic_vector(1 downto 0);`
229			`nrxclki : in std_logic_vector(1 downto 0);`
230			`rxclko : out std_logic_vector(1 downto 0);`
231			`rxrenable : out std_logic;`
232			`rxraddress : out std_logic_vector(4 downto 0);`
233			`rxwrite : out std_logic;`
234			`rxwdata : out std_logic_vector(31 downto 0);`
235			`rxwaddress : out std_logic_vector(4 downto 0);`
236			`rxrdata : in std_logic_vector(31 downto 0);`
237			`txrenable : out std_logic;`
238			`txraddress : out std_logic_vector(4 downto 0);`
239			`txwrite : out std_logic;`
240			`txwdata : out std_logic_vector(31 downto 0);`
241			`txwaddress : out std_logic_vector(4 downto 0);`
242			`txrdata : in std_logic_vector(31 downto 0);`
243			`ncrenable : out std_logic;`
244			`ncraddress : out std_logic_vector(5 downto 0);`
245			`ncwrite : out std_logic;`
246			`ncwdata : out std_logic_vector(8 downto 0);`
247			`ncwaddress : out std_logic_vector(5 downto 0);`
248			`ncrdata : in std_logic_vector(8 downto 0);`
249			`rmrenable : out std_logic;`
250			`rmraddress : out std_logic_vector(7 downto 0);`
251			`rmwrite : out std_logic;`
252			`rmwdata : out std_logic_vector(7 downto 0);`
253			`rmwaddress : out std_logic_vector(7 downto 0);`
254			`rmrdata : in std_logic_vector(7 downto 0);`
255			`linkdis : out std_logic;`
256			`testclk : in std_logic;`
257			`testrst : in std_logic;`
258			`testen : in std_logic);`
259			`end component;`
260
261			`begin`
262
263			`f16_16 : if (fifosize1 = 16) and (fifosize2 = 16) and (rmap = 0) generate`
264			`grspwc0 : grspwc_unisim_16_16`
265			`port map(`
266			`rst => rst,`
267			`clk => clk,`
268			`txclk => txclk,`
269			`--ahb mst in`
270			`hgrant => hgrant,`
271			`hready => hready,`
272			`hresp => hresp,`
273			`hrdata => hrdata,`
274			`--ahb mst out`
275			`hbusreq => hbusreq,`
276			`hlock => hlock,`
277			`htrans => htrans,`
278			`haddr => haddr,`
279			`hwrite => hwrite,`
280			`hsize => hsize,`
281			`hburst => hburst,`
282			`hprot => hprot,`
283			`hwdata => hwdata,`
284			`--apb slv in`
285			`psel => psel,`
286			`penable => penable,`
287			`paddr => paddr,`
288			`pwrite => pwrite,`
289			`pwdata => pwdata,`
290			`--apb slv out`
291			`prdata => prdata,`
292			`--spw in`
293			`di => di,`
294			`si => si,`
295			`--spw out`
296			`do => do,`
297			`so => so,`
298			`--time iface`
299			`tickin => tickin,`
300			`tickout => tickout,`
301			`--clk bufs`
302			`rxclki => rxclki,`
303			`nrxclki => nrxclki,`
304			`rxclko => rxclko,`
305			`--irq`
306			`irq => irq,`
307			`--misc`
308			`clkdiv10 => clkdiv10,`
309			`dcrstval => dcrstval,`
310			`timerrstval => timerrstval,`
311			`--rmapen`
312			`rmapen => rmapen,`
313			`--rx ahb fifo`
314			`rxrenable => rxrenable,`
315			`rxraddress => rxraddress,`
316			`rxwrite => rxwrite,`
317			`rxwdata => rxwdata,`
318			`rxwaddress => rxwaddress,`
319			`rxrdata => rxrdata,`
320			`--tx ahb fifo`
321			`txrenable => txrenable,`
322			`txraddress => txraddress,`
323			`txwrite => txwrite,`
324			`txwdata => txwdata,`
325			`txwaddress => txwaddress,`
326			`txrdata => txrdata,`
327			`--nchar fifo`
328			`ncrenable => ncrenable,`
329			`ncraddress => ncraddress,`
330			`ncwrite => ncwrite,`
331			`ncwdata => ncwdata,`
332			`ncwaddress => ncwaddress,`
333			`ncrdata => ncrdata,`
334			`--rmap buf`
335			`rmrenable => rmrenable,`
336			`rmraddress => rmraddress,`
337			`rmwrite => rmwrite,`
338			`rmwdata => rmwdata,`
339			`rmwaddress => rmwaddress,`
340			`rmrdata => rmrdata,`
341			`linkdis => linkdis,`
342			`testclk => testclk,`
343			`testrst => testrst,`
344			`testen => testen`
345			`);`
346			`end generate;`
347
348			`rmap_f16_16 : if (fifosize1 = 16) and (fifosize2 = 16) and (rmap /= 0) generate`
349			`grspwc0 : grspwc_unisim_rmap_16_16`
350			`port map(`
351			`rst => rst,`
352			`clk => clk,`
353			`txclk => txclk,`
354			`--ahb mst in`
355			`hgrant => hgrant,`
356			`hready => hready,`
357			`hresp => hresp,`
358			`hrdata => hrdata,`
359			`--ahb mst out`
360			`hbusreq => hbusreq,`
361			`hlock => hlock,`
362			`htrans => htrans,`
363			`haddr => haddr,`
364			`hwrite => hwrite,`
365			`hsize => hsize,`
366			`hburst => hburst,`
367			`hprot => hprot,`
368			`hwdata => hwdata,`
369			`--apb slv in`
370			`psel => psel,`
371			`penable => penable,`
372			`paddr => paddr,`
373			`pwrite => pwrite,`
374			`pwdata => pwdata,`
375			`--apb slv out`
376			`prdata => prdata,`
377			`--spw in`
378			`di => di,`
379			`si => si,`
380			`--spw out`
381			`do => do,`
382			`so => so,`
383			`--time iface`
384			`tickin => tickin,`
385			`tickout => tickout,`
386			`--clk bufs`
387			`rxclki => rxclki,`
388			`nrxclki => nrxclki,`
389			`rxclko => rxclko,`
390			`--irq`
391			`irq => irq,`
392			`--misc`
393			`clkdiv10 => clkdiv10,`
394			`dcrstval => dcrstval,`
395			`timerrstval => timerrstval,`
396			`--rmapen`
397			`rmapen => rmapen,`
398			`--rx ahb fifo`
399			`rxrenable => rxrenable,`
400			`rxraddress => rxraddress,`
401			`rxwrite => rxwrite,`
402			`rxwdata => rxwdata,`
403			`rxwaddress => rxwaddress,`
404			`rxrdata => rxrdata,`
405			`--tx ahb fifo`
406			`txrenable => txrenable,`
407			`txraddress => txraddress,`
408			`txwrite => txwrite,`
409			`txwdata => txwdata,`
410			`txwaddress => txwaddress,`
411			`txrdata => txrdata,`
412			`--nchar fifo`
413			`ncrenable => ncrenable,`
414			`ncraddress => ncraddress,`
415			`ncwrite => ncwrite,`
416			`ncwdata => ncwdata,`
417			`ncwaddress => ncwaddress,`
418			`ncrdata => ncrdata,`
419			`--rmap buf`
420			`rmrenable => rmrenable,`
421			`rmraddress => rmraddress,`
422			`rmwrite => rmwrite,`
423			`rmwdata => rmwdata,`
424			`rmwaddress => rmwaddress,`
425			`rmrdata => rmrdata,`
426			`linkdis => linkdis,`
427			`testclk => testclk,`
428			`testrst => testrst,`
429			`testen => testen`
430			`);`
431			`end generate;`
432
433			`-- pragma translate_off`
434
435			`nomap : if not ((fifosize1 = 16) and (fifosize2 = 16)) generate`
436
437			`err : process`
438			`begin`
439			`assert false report "ERROR : AHB and RX fifos must be 16!"`
440			`severity failure;`
441			`wait;`
442			`end process;`
443
444			`end generate;`
445
446			`-- pragma translate_on`
447
448			`end architecture;`