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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [lib/] [techmap/] [unisim/] [ssrctrl_unisim.vhd] - Blame information for rev 2

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1 2 dimamali 
------------------------------------------------------------------------------
2 
--  This file is a part of the GRLIB VHDL IP LIBRARY
3 
--  Copyright (C) 2003, Gaisler Research
4 
--
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--  This program is free software; you can redistribute it and/or modify
6 
--  it under the terms of the GNU General Public License as published by
7 
--  the Free Software Foundation; either version 2 of the License, or
8 
--  (at your option) any later version.
9 
--
10 
--  This program is distributed in the hope that it will be useful,
11 
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
12 
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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--  GNU General Public License for more details.
14 
--
15 
--  You should have received a copy of the GNU General Public License
16 
--  along with this program; if not, write to the Free Software
17 
--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
18 
--
19 
-----------------------------------------------------------------------------
20 
-- Entity:        ssrctrl_unisim
21 
-- file:          ssrctrl_unisim.vhd
22 
-- Description:   32-bit SSRAM memory controller with PROM 16-bit bus support
23 
------------------------------------------------------------------------------
24 
 
25 
library ieee;
26 
use ieee.std_logic_1164.all;
27 
library unisim;
28 
use unisim.vcomponents.all;
29 
 
30 
entity ssrctrl_unisim is
31 
port(
32 
  rst :  in std_logic;
33 
  clk :  in std_logic;
34 
  n_ahbsi_hsel : in std_logic_vector (0 to 15);
35 
  n_ahbsi_haddr : in std_logic_vector (31 downto 0);
36 
  n_ahbsi_hwrite :  in std_logic;
37 
  n_ahbsi_htrans : in std_logic_vector (1 downto 0);
38 
  n_ahbsi_hsize : in std_logic_vector (2 downto 0);
39 
  n_ahbsi_hburst : in std_logic_vector (2 downto 0);
40 
  n_ahbsi_hwdata : in std_logic_vector (31 downto 0);
41 
  n_ahbsi_hprot : in std_logic_vector (3 downto 0);
42 
  n_ahbsi_hready :  in std_logic;
43 
  n_ahbsi_hmaster : in std_logic_vector (3 downto 0);
44 
  n_ahbsi_hmastlock :  in std_logic;
45 
  n_ahbsi_hmbsel : in std_logic_vector (0 to 3);
46 
  n_ahbsi_hcache :  in std_logic;
47 
  n_ahbsi_hirq : in std_logic_vector (31 downto 0);
48 
  n_ahbso_hready :  out std_logic;
49 
  n_ahbso_hresp : out std_logic_vector (1 downto 0);
50 
  n_ahbso_hrdata : out std_logic_vector (31 downto 0);
51 
  n_ahbso_hsplit : out std_logic_vector (15 downto 0);
52 
  n_ahbso_hcache :  out std_logic;
53 
  n_ahbso_hirq : out std_logic_vector (31 downto 0);
54 
  n_apbi_psel : in std_logic_vector (0 to 15);
55 
  n_apbi_penable :  in std_logic;
56 
  n_apbi_paddr : in std_logic_vector (31 downto 0);
57 
  n_apbi_pwrite :  in std_logic;
58 
  n_apbi_pwdata : in std_logic_vector (31 downto 0);
59 
  n_apbi_pirq : in std_logic_vector (31 downto 0);
60 
  n_apbo_prdata : out std_logic_vector (31 downto 0);
61 
  n_apbo_pirq : out std_logic_vector (31 downto 0);
62 
  n_sri_data : in std_logic_vector (31 downto 0);
63 
  n_sri_brdyn :  in std_logic;
64 
  n_sri_bexcn :  in std_logic;
65 
  n_sri_writen :  in std_logic;
66 
  n_sri_wrn : in std_logic_vector (3 downto 0);
67 
  n_sri_bwidth : in std_logic_vector (1 downto 0);
68 
  n_sri_sd : in std_logic_vector (63 downto 0);
69 
  n_sri_cb : in std_logic_vector (7 downto 0);
70 
  n_sri_scb : in std_logic_vector (7 downto 0);
71 
  n_sri_edac :  in std_logic;
72 
  n_sro_address : out std_logic_vector (31 downto 0);
73 
  n_sro_data : out std_logic_vector (31 downto 0);
74 
  n_sro_sddata : out std_logic_vector (63 downto 0);
75 
  n_sro_ramsn : out std_logic_vector (7 downto 0);
76 
  n_sro_ramoen : out std_logic_vector (7 downto 0);
77 
  n_sro_ramn :  out std_logic;
78 
  n_sro_romn :  out std_logic;
79 
  n_sro_mben : out std_logic_vector (3 downto 0);
80 
  n_sro_iosn :  out std_logic;
81 
  n_sro_romsn : out std_logic_vector (7 downto 0);
82 
  n_sro_oen :  out std_logic;
83 
  n_sro_writen :  out std_logic;
84 
  n_sro_wrn : out std_logic_vector (3 downto 0);
85 
  n_sro_bdrive : out std_logic_vector (3 downto 0);
86 
  n_sro_vbdrive : out std_logic_vector (31 downto 0);
87 
  n_sro_svbdrive : out std_logic_vector (63 downto 0);
88 
  n_sro_read :  out std_logic;
89 
  n_sro_sa : out std_logic_vector (14 downto 0);
90 
  n_sro_cb : out std_logic_vector (7 downto 0);
91 
  n_sro_scb : out std_logic_vector (7 downto 0);
92 
  n_sro_vcdrive : out std_logic_vector (7 downto 0);
93 
  n_sro_svcdrive : out std_logic_vector (7 downto 0);
94 
  n_sro_ce :  out std_logic);
95 
end ssrctrl_unisim;
96 
 
97 
--
98 
library ieee;
99 
use ieee.std_logic_1164.all;
100 
library unisim;
101 
use unisim.vcomponents.all;
102 
 
103 
entity ssrctrl_unisim_netlist is
104 
port(
105 
  n_sro_vbdrive : out std_logic_vector (31 downto 0);
106 
  n_ahbso_hrdata : out std_logic_vector (31 downto 0);
107 
  iows_0 :  out std_logic;
108 
  iows_3 :  out std_logic;
109 
  romwws_0 :  out std_logic;
110 
  romwws_3 :  out std_logic;
111 
  romrws_0 :  out std_logic;
112 
  romrws_3 :  out std_logic;
113 
  NoName_cnst : in std_logic_vector (0 downto 0);
114 
  n_sri_bwidth : in std_logic_vector (1 downto 0);
115 
  n_apbi_pwdata_19 :  in std_logic;
116 
  n_apbi_pwdata_11 :  in std_logic;
117 
  n_apbi_pwdata_9 :  in std_logic;
118 
  n_apbi_pwdata_8 :  in std_logic;
119 
  n_apbi_pwdata_23 :  in std_logic;
120 
  n_apbi_pwdata_22 :  in std_logic;
121 
  n_apbi_pwdata_21 :  in std_logic;
122 
  n_apbi_pwdata_20 :  in std_logic;
123 
  n_apbi_pwdata_3 :  in std_logic;
124 
  n_apbi_pwdata_2 :  in std_logic;
125 
  n_apbi_pwdata_1 :  in std_logic;
126 
  n_apbi_pwdata_0 :  in std_logic;
127 
  n_apbi_pwdata_7 :  in std_logic;
128 
  n_apbi_pwdata_6 :  in std_logic;
129 
  n_apbi_pwdata_5 :  in std_logic;
130 
  n_apbi_pwdata_4 :  in std_logic;
131 
  n_apbi_psel : in std_logic_vector (0 downto 0);
132 
  n_apbi_paddr : in std_logic_vector (5 downto 2);
133 
  n_apbo_prdata_0 :  out std_logic;
134 
  n_apbo_prdata_4 :  out std_logic;
135 
  n_apbo_prdata_20 :  out std_logic;
136 
  n_apbo_prdata_23 :  out std_logic;
137 
  n_apbo_prdata_22 :  out std_logic;
138 
  n_apbo_prdata_21 :  out std_logic;
139 
  n_apbo_prdata_19 :  out std_logic;
140 
  n_apbo_prdata_7 :  out std_logic;
141 
  n_apbo_prdata_6 :  out std_logic;
142 
  n_apbo_prdata_5 :  out std_logic;
143 
  n_apbo_prdata_3 :  out std_logic;
144 
  n_apbo_prdata_2 :  out std_logic;
145 
  n_apbo_prdata_1 :  out std_logic;
146 
  n_apbo_prdata_11 :  out std_logic;
147 
  n_apbo_prdata_9 :  out std_logic;
148 
  n_apbo_prdata_8 :  out std_logic;
149 
  n_apbo_prdata_28 :  out std_logic;
150 
  n_sro_romsn : out std_logic_vector (0 downto 0);
151 
  n_ahbsi_hsel : in std_logic_vector (0 downto 0);
152 
  prstate_fast : out std_logic_vector (2 downto 2);
153 
  n_ahbsi_htrans : in std_logic_vector (1 downto 0);
154 
  ssrstate_1_m1 : inout std_logic_vector (4 downto 3) := (others => 'Z');
155 
  hsel_1 : in std_logic_vector (0 downto 0);
156 
  hmbsel_4 : out std_logic_vector (1 downto 1);
157 
  n_sro_bdrive : out std_logic_vector (3 downto 3);
158 
  ws_1_0 :  in std_logic;
159 
  ws_1_3 :  in std_logic;
160 
  ws : out std_logic_vector (3 downto 0);
161 
  ssrstate_1_2 :  in std_logic;
162 
  n_ahbsi_haddr : in std_logic_vector (31 downto 0);
163 
  n_ahbsi_hmbsel : in std_logic_vector (2 downto 0);
164 
  n_sri_data : in std_logic_vector (31 downto 0);
165 
  ssrstate : out std_logic_vector (4 downto 0);
166 
  n_ahbsi_hwdata : in std_logic_vector (31 downto 0);
167 
  n_ahbsi_hsize : in std_logic_vector (1 downto 0);
168 
  size : out std_logic_vector (1 downto 0);
169 
  n_sro_data : out std_logic_vector (31 downto 0);
170 
  n_sro_ramsn : out std_logic_vector (0 downto 0);
171 
  n_sro_wrn : out std_logic_vector (3 downto 0);
172 
  haddr_0 :  in std_logic;
173 
  bwn_1_0_o3_0 :  in std_logic;
174 
  hsize_1 : in std_logic_vector (1 downto 1);
175 
  prstate_1_i_o4_s : in std_logic_vector (2 downto 2);
176 
  prstate : out std_logic_vector (5 downto 0);
177 
  hmbsel : out std_logic_vector (2 downto 0);
178 
  n_sro_address : out std_logic_vector (31 downto 0);
179 
  hready_2 :  in std_logic;
180 
  n_ahbso_hready :  out std_logic;
181 
  ssrhready_8 :  in std_logic;
182 
  loadcount :  out std_logic;
183 
  n_sro_writen :  out std_logic;
184 
  ssrstatec :  in std_logic;
185 
  prhready :  out std_logic;
186 
  d_m2_0_a2_0 :  in std_logic;
187 
  ssrstate17_2_0_m6_i_a3_a2 :  out std_logic;
188 
  N_319_1 :  out std_logic;
189 
  ws_0_sqmuxa_c :  out std_logic;
190 
  N_365 :  in std_logic;
191 
  ws_0_sqmuxa_0_c :  out std_logic;
192 
  ws_2_sqmuxa_3_0_4 :  out std_logic;
193 
  change_1_sqmuxa_0 :  in std_logic;
194 
  d16mux_0_sqmuxa :  in std_logic;
195 
  ssrstate_2_sqmuxa_1 :  in std_logic;
196 
  un7_bus16en :  in std_logic;
197 
  N_646 :  in std_logic;
198 
  loadcount_1_sqmuxa :  in std_logic;
199 
  ssrstate_1_sqmuxa_1_0_m3_0_1 :  out std_logic;
200 
  n_apbi_penable :  in std_logic;
201 
  n_apbi_pwrite :  in std_logic;
202 
  d_m1_e_0_0 :  in std_logic;
203 
  hsel_1_0_L3 :  out std_logic;
204 
  ssrhready_8_f0_L8 :  out std_logic;
205 
  ssrstate_1_sqmuxa_1 :  in std_logic;
206 
  ssrhready :  out std_logic;
207 
  ssrhready_8_f0_L5 :  out std_logic;
208 
  ssrstate17_1_xx_mm_N_4 :  in std_logic;
209 
  ws_1_sqmuxa :  out std_logic;
210 
  ws_4_sqmuxa_0 :  in std_logic;
211 
  ws_2_sqmuxa_0 :  in std_logic;
212 
  ssrstate17_2_0_m6_i_1 :  out std_logic;
213 
  ws_2_sqmuxa_3_0_x :  out std_logic;
214 
  ws_3_sqmuxa_1 :  out std_logic;
215 
  ws_2_sqmuxa_3_0_2 :  out std_logic;
216 
  ssrstate_2_i :  out std_logic;
217 
  ws_2_sqmuxa_3_d :  out std_logic;
218 
  ws_0_sqmuxa_1 :  out std_logic;
219 
  g0_30 :  in std_logic;
220 
  hsel_4 :  in std_logic;
221 
  n_ahbsi_hready :  in std_logic;
222 
  hsel :  out std_logic;
223 
  g0_25 :  in std_logic;
224 
  bwn_0_sqmuxa_1 :  in std_logic;
225 
  prstate_2_rep1 :  out std_logic;
226 
  N_662 :  out std_logic;
227 
  ssrstate_6_sqmuxa :  out std_logic;
228 
  g0_52_x1 :  in std_logic;
229 
  g0_52_x0 :  in std_logic;
230 
  ssrhready_2_sqmuxa_0_0 :  out std_logic;
231 
  change_1_sqmuxa_N_3 :  out std_logic;
232 
  ssrstate6_xx_mm_m3 :  out std_logic;
233 
  ssrstate6_1_d_0_L1 :  out std_logic;
234 
  N_656 :  out std_logic;
235 
  hsel_5 :  out std_logic;
236 
  change_3_f0 :  in std_logic;
237 
  un1_ahbsi :  out std_logic;
238 
  change :  out std_logic;
239 
  n_ahbsi_hwrite :  in std_logic;
240 
  N_574_i :  in std_logic;
241 
  n_sro_iosn :  out std_logic;
242 
  N_618_i :  in std_logic;
243 
  clk :  in std_logic;
244 
  n_sro_oen :  out std_logic;
245 
  rst :  in std_logic;
246 
  bwn_1_sqmuxa_2_d :  in std_logic;
247 
  bwn_1_sqmuxa_2_d_0_2 :  in std_logic;
248 
  ssrstate_2_sqmuxa_i :  in std_logic;
249 
  g0_23 :  in std_logic;
250 
  N_371 :  out std_logic;
251 
  loadcount_7 :  in std_logic;
252 
  bus16en :  out std_logic;
253 
  d16muxc_0_4 :  out std_logic;
254 
  change_3_f1_d_0_0 :  in std_logic;
255 
  g0_1_0 :  in std_logic;
256 
  g0_44 :  in std_logic);
257 
end ssrctrl_unisim_netlist;
258 
 
259 
architecture beh of ssrctrl_unisim_netlist is
260 
  signal ACOUNT_QXU : std_logic_vector (9 downto 1);
261 
  signal ACOUNT_LM_0_1 : std_logic_vector (0 to 0);
262 
  signal ACOUNT_LM : std_logic_vector (9 downto 0);
263 
  signal WS_1_0_BM : std_logic_vector (1 to 1);
264 
  signal WS_1_0_RN_1 : std_logic_vector (1 to 1);
265 
  signal WS_1 : std_logic_vector (2 downto 1);
266 
  signal SSRSTATE_1_0_D_BM : std_logic_vector (3 to 3);
267 
  signal SSRSTATE_1_0_1 : std_logic_vector (3 to 3);
268 
  signal SSRSTATE_1 : std_logic_vector (3 downto 2);
269 
  signal BWN_1_0_O3 : std_logic_vector (1 to 1);
270 
  signal PRSTATE_I : std_logic_vector (1 to 1);
271 
  signal HWDATAOUT_1 : std_logic_vector (31 downto 0);
272 
  signal ROMWIDTH : std_logic_vector (1 downto 0);
273 
  signal ROMWIDTH_1 : std_logic_vector (1 downto 0);
274 
  signal DATA16 : std_logic_vector (15 downto 0);
275 
  signal HRDATA : std_logic_vector (31 downto 0);
276 
  signal HWDATA : std_logic_vector (31 downto 0);
277 
  signal HADDR : std_logic_vector (11 downto 2);
278 
  signal SSRSTATE_1_0_D_AM : std_logic_vector (3 to 3);
279 
  signal HMBSEL_4_X1 : std_logic_vector (1 to 1);
280 
  signal WS_1_2_0_D : std_logic_vector (2 downto 1);
281 
  signal WS_1_0_AM_1 : std_logic_vector (1 to 1);
282 
  signal BWN_1_0_0 : std_logic_vector (3 to 3);
283 
  signal IOWS_1 : std_logic_vector (3 downto 0);
284 
  signal ACOUNT_S : std_logic_vector (9 downto 1);
285 
  signal SSRSTATE_11 : std_logic_vector (0 to 0);
286 
  signal SSRSTATE23_U_0_AM : std_logic_vector (4 to 4);
287 
  signal SSRSTATE23_U_0_BM : std_logic_vector (4 to 4);
288 
  signal ROMRWS : std_logic_vector (2 downto 1);
289 
  signal IOWS : std_logic_vector (2 downto 1);
290 
  signal ROMWWS : std_logic_vector (2 downto 1);
291 
  signal D16MUX : std_logic_vector (1 downto 0);
292 
  signal ACOUNT_CRY : std_logic_vector (8 downto 1);
293 
  signal ROMSN_1_IV_L1 : std_logic ;
294 
  signal CHANGE_3 : std_logic ;
295 
  signal ROMSN_1 : std_logic ;
296 
  signal PRHREADY_6 : std_logic ;
297 
  signal N_635_I_1 : std_logic ;
298 
  signal N_635_I : std_logic ;
299 
  signal D16MUXC_0_1 : std_logic ;
300 
  signal D16MUXC_0_1_0 : std_logic ;
301 
  signal D16MUXC_0_4_INT_73 : std_logic ;
302 
  signal D16MUXC_0 : std_logic ;
303 
  signal N_371_INT_71 : std_logic ;
304 
  signal WS_1_L1 : std_logic ;
305 
  signal WS_1_L1_0 : std_logic ;
306 
  signal SSRSTATE_1_M2S2_0 : std_logic ;
307 
  signal IOSN_9_IV_L1 : std_logic ;
308 
  signal PRSTATE_0_INT_27 : std_logic ;
309 
  signal IOSN_9 : std_logic ;
310 
  signal N_317 : std_logic ;
311 
  signal N_619_I_L1 : std_logic ;
312 
  signal N_619_I : std_logic ;
313 
  signal N_620_I : std_logic ;
314 
  signal PRSTATE_1_INT_28 : std_logic ;
315 
  signal RST_I : std_logic ;
316 
  signal OEN_1 : std_logic ;
317 
  signal OEN_1_SQMUXA_2_I : std_logic ;
318 
  signal BWN_1_SQMUXA_3_I : std_logic ;
319 
  signal N_617_I : std_logic ;
320 
  signal N_599_I : std_logic ;
321 
  signal SSRSTATE_9 : std_logic ;
322 
  signal BEXCEN_1_SQMUXA_I : std_logic ;
323 
  signal DATA16_0_SQMUXA : std_logic ;
324 
  signal HMBSEL_0_SQMUXA : std_logic ;
325 
  signal HWRITE : std_logic ;
326 
  signal SSRSTATE_1_INT_21 : std_logic ;
327 
  signal HMBSEL_0_INT_33 : std_logic ;
328 
  signal HMBSEL_2_INT_35 : std_logic ;
329 
  signal BDRIVE_1 : std_logic ;
330 
  signal N_SRO_ADDRESS_2_INT_38 : std_logic ;
331 
  signal N_SRO_ADDRESS_3_INT_39 : std_logic ;
332 
  signal N_SRO_ADDRESS_4_INT_40 : std_logic ;
333 
  signal N_SRO_ADDRESS_5_INT_41 : std_logic ;
334 
  signal N_SRO_ADDRESS_6_INT_42 : std_logic ;
335 
  signal N_SRO_ADDRESS_7_INT_43 : std_logic ;
336 
  signal N_SRO_ADDRESS_8_INT_44 : std_logic ;
337 
  signal N_SRO_ADDRESS_9_INT_45 : std_logic ;
338 
  signal N_SRO_ADDRESS_10_INT_46 : std_logic ;
339 
  signal OEN_1_SQMUXA_2_I_L4 : std_logic ;
340 
  signal PRSTATE_1 : std_logic ;
341 
  signal OEN_1_SQMUXA_2_I_L6 : std_logic ;
342 
  signal N_654 : std_logic ;
343 
  signal SSRSTATE_2_INT_22 : std_logic ;
344 
  signal SSRSTATE_12_1 : std_logic ;
345 
  signal WS_1_0_BM_L1 : std_logic ;
346 
  signal WS_1_0_BM_L3 : std_logic ;
347 
  signal UN1_AHBSI_INT_68 : std_logic ;
348 
  signal HSEL_5_INT_67 : std_logic ;
349 
  signal WS_1_0_BM_L5 : std_logic ;
350 
  signal HMBSEL_4_1_INT_14 : std_logic ;
351 
  signal N_619_I_L1_L1 : std_logic ;
352 
  signal SSRSTATE6_XX_MM_M3_INT_64 : std_logic ;
353 
  signal HMBSEL_1_INT_34 : std_logic ;
354 
  signal SSRSTATE_6_SQMUXA_1 : std_logic ;
355 
  signal N_SRO_ADDRESS_0_INT_36 : std_logic ;
356 
  signal SIZE_0_INT_25 : std_logic ;
357 
  signal BWN_1_0_O3_0_L1 : std_logic ;
358 
  signal BWN_1_0_O3_0_L3 : std_logic ;
359 
  signal BWN_1_0_O3_0_L5 : std_logic ;
360 
  signal PRSTATE_2_REP1_INT_59 : std_logic ;
361 
  signal PRSTATEC_0_REP1 : std_logic ;
362 
  signal N_336 : std_logic ;
363 
  signal PRSTATEC_0_FAST : std_logic ;
364 
  signal WS_1_INT_17 : std_logic ;
365 
  signal BDRIVE_1_IV_M9_I_A4_0_2_1 : std_logic ;
366 
  signal BDRIVE_1_IV_M9_I_A4_0_2_2_1 : std_logic ;
367 
  signal BDRIVE_0_SQMUXA_2_C : std_logic ;
368 
  signal BDRIVE_1_IV_M9_I_A4_0_2_2_L1 : std_logic ;
369 
  signal BDRIVE_1_TZ : std_logic ;
370 
  signal BDRIVE_1_IV_M9_I_A4_0_2_2_1_L1 : std_logic ;
371 
  signal N_SRO_BDRIVE_3_INT_15 : std_logic ;
372 
  signal BDRIVE_1_IV_M9_I_A4_0_2_2_1_L3 : std_logic ;
373 
  signal N_668 : std_logic ;
374 
  signal BDRIVE_1_SQMUXA : std_logic ;
375 
  signal N_662_INT_60 : std_logic ;
376 
  signal SSRSTATE6_XX_MM_M3_L1 : std_logic ;
377 
  signal PRSTATE_5_INT_32 : std_logic ;
378 
  signal SSRSTATE_4_INT_24 : std_logic ;
379 
  signal SSRSTATE6_XX_MM_M3_L3 : std_logic ;
380 
  signal WS_2_SQMUXA_3_0_SX : std_logic ;
381 
  signal WS_0_SQMUXA_1_INT_57 : std_logic ;
382 
  signal WS_2_SQMUXA_3_D_INT_56 : std_logic ;
383 
  signal SSRSTATE17_2_0_M6_I_A3_A0_1 : std_logic ;
384 
  signal CHANGE_3_F1_D_0_L1 : std_logic ;
385 
  signal CHANGE_INT_69 : std_logic ;
386 
  signal PRSTATE_2_INT_29 : std_logic ;
387 
  signal WRITEN_2_SQMUXA_L1 : std_logic ;
388 
  signal WRITEN_2_SQMUXA_L3 : std_logic ;
389 
  signal WRITEN_2_SQMUXA_L5 : std_logic ;
390 
  signal WRITEN_2_SQMUXA_TZ_0 : std_logic ;
391 
  signal BWN_1_SQMUXA_2_D_0 : std_logic ;
392 
  signal WRITEN_2_SQMUXA : std_logic ;
393 
  signal WS_3_SQMUXA_1_INT_53 : std_logic ;
394 
  signal WS_1_L1_L1 : std_logic ;
395 
  signal WS_2_INT_18 : std_logic ;
396 
  signal WS_2_SQMUXA_3_0_2_L1 : std_logic ;
397 
  signal WS_2_SQMUXA_3_0_2_INT_54 : std_logic ;
398 
  signal WS_0_INT_16 : std_logic ;
399 
  signal SSRSTATE_3_INT_23 : std_logic ;
400 
  signal SSRSTATE6_1_D_0_L1_INT_65 : std_logic ;
401 
  signal WS_3_SQMUXA_0_1 : std_logic ;
402 
  signal WS_3_SQMUXA_1_A0_2 : std_logic ;
403 
  signal N_SRO_ROMSN_0_INT_12 : std_logic ;
404 
  signal PRSTATE_8_1 : std_logic ;
405 
  signal N_656_INT_66 : std_logic ;
406 
  signal N_SRO_IOSN_INT_70 : std_logic ;
407 
  signal PRSTATE_FAST_2_INT_13 : std_logic ;
408 
  signal BEXCEN_1_SQMUXA_I_1 : std_logic ;
409 
  signal HSEL_INT_58 : std_logic ;
410 
  signal PRSTATE_12_M7_I_A6_0 : std_logic ;
411 
  signal PRSTATE_12_I : std_logic ;
412 
  signal HWRITE_1 : std_logic ;
413 
  signal PRSTATE_12_0 : std_logic ;
414 
  signal PRSTATE_12_M7_I_A6 : std_logic ;
415 
  signal PRSTATE_4_INT_31 : std_logic ;
416 
  signal SIZE_1_INT_26 : std_logic ;
417 
  signal PRSTATE_1_SQMUXA : std_logic ;
418 
  signal BUS16EN_INT_72 : std_logic ;
419 
  signal N_382 : std_logic ;
420 
  signal N_383 : std_logic ;
421 
  signal N_384 : std_logic ;
422 
  signal N_385 : std_logic ;
423 
  signal N_386 : std_logic ;
424 
  signal N_387 : std_logic ;
425 
  signal N_388 : std_logic ;
426 
  signal N_389 : std_logic ;
427 
  signal N_390 : std_logic ;
428 
  signal N_391 : std_logic ;
429 
  signal N_392 : std_logic ;
430 
  signal N_393 : std_logic ;
431 
  signal N_394 : std_logic ;
432 
  signal N_395 : std_logic ;
433 
  signal N_396 : std_logic ;
434 
  signal N_397 : std_logic ;
435 
  signal N_626_I : std_logic ;
436 
  signal N_625_I : std_logic ;
437 
  signal N_624_I : std_logic ;
438 
  signal N_623_I : std_logic ;
439 
  signal N_630_I : std_logic ;
440 
  signal N_629_I : std_logic ;
441 
  signal N_628_I : std_logic ;
442 
  signal N_627_I : std_logic ;
443 
  signal ROMWRITE_1 : std_logic ;
444 
  signal IOEN_1 : std_logic ;
445 
  signal SSRSTATE_6_SQMUXA_INT_61 : std_logic ;
446 
  signal BDRIVE_1_IV_0_A0 : std_logic ;
447 
  signal BDRIVE_1_IV_0_A1 : std_logic ;
448 
  signal BDRIVE_1_IV_M9_I_0_0 : std_logic ;
449 
  signal NN_1 : std_logic ;
450 
  signal NN_2 : std_logic ;
451 
  signal NN_3 : std_logic ;
452 
  signal NN_4 : std_logic ;
453 
  signal NN_5 : std_logic ;
454 
  signal NN_6 : std_logic ;
455 
  signal NN_7 : std_logic ;
456 
  signal NN_8 : std_logic ;
457 
  signal NN_9 : std_logic ;
458 
  signal D16MUXC_1 : std_logic ;
459 
  signal D16MUXC_2 : std_logic ;
460 
  signal D16MUXC : std_logic ;
461 
  signal BDRIVE_1_IV_0_1 : std_logic ;
462 
  signal BDRIVE_1_IV_M9_I_0 : std_logic ;
463 
  signal RBDRIVEC_18 : std_logic ;
464 
  signal SSRSTATE_5_I : std_logic ;
465 
  signal SSRSTATEC_0 : std_logic ;
466 
  signal SSRSTATE23_1 : std_logic ;
467 
  signal WS_3_INT_19 : std_logic ;
468 
  signal PRSTATEC_1 : std_logic ;
469 
  signal N_337_I : std_logic ;
470 
  signal PRSTATEC_0 : std_logic ;
471 
  signal PRSTATE_3_INT_30 : std_logic ;
472 
  signal PRSTATEC : std_logic ;
473 
  signal N_342 : std_logic ;
474 
  signal PRSTATESR_0 : std_logic ;
475 
  signal PRSTATES_I : std_logic ;
476 
  signal N_SRO_ADDRESS_11_INT_47 : std_logic ;
477 
  signal WRITEN_0_SQMUXA_0_2 : std_logic ;
478 
  signal WRITEN_0_SQMUXA_D : std_logic ;
479 
  signal RBDRIVEC : std_logic ;
480 
  signal SSRSTATE_2_I_INT_55 : std_logic ;
481 
  signal HADDR_0_SQMUXA_A0_0 : std_logic ;
482 
  signal WRITEN_0_SQMUXA_0_0 : std_logic ;
483 
  signal BDRIVE_1_SQMUXA_2 : std_logic ;
484 
  signal WS_0_SQMUXA_0_0_0 : std_logic ;
485 
  signal CHANGE_1_SQMUXA_N_3_INT_63 : std_logic ;
486 
  signal SSRHREADY_2_SQMUXA_0_0_INT_62 : std_logic ;
487 
  signal N_362 : std_logic ;
488 
  signal N_363 : std_logic ;
489 
  signal SETBDRIVE : std_logic ;
490 
  signal N_341 : std_logic ;
491 
  signal BDRIVE_0_SQMUXA_2_0_0 : std_logic ;
492 
  signal BDRIVE_1_IV_0_A4_0 : std_logic ;
493 
  signal SSRSTATE_0_INT_20 : std_logic ;
494 
  signal PRHREADY_0_SQMUXA : std_logic ;
495 
  signal SSRSTATE10 : std_logic ;
496 
  signal WS_0_SQMUXA_0_C_INT_50 : std_logic ;
497 
  signal N_SRO_ADDRESS_1_INT_37 : std_logic ;
498 
  signal UN17_BUS16EN : std_logic ;
499 
  signal WS_1_SQMUXA_INT_52 : std_logic ;
500 
  signal SSRSTATE_3 : std_logic ;
501 
  signal WS_0_SQMUXA_C_INT_49 : std_logic ;
502 
  signal ROMWRITE : std_logic ;
503 
  signal IOEN : std_logic ;
504 
  signal N_APBO_PRDATA_28_INT_11 : std_logic ;
505 
  signal NN_10 : std_logic ;
506 
  signal N_481 : std_logic ;
507 
  signal N_480 : std_logic ;
508 
  signal IOWS_3_INT_6 : std_logic ;
509 
  signal IOWS_0_INT_5 : std_logic ;
510 
  signal ROMRWS_3_INT_10 : std_logic ;
511 
  signal ROMRWS_0_INT_9 : std_logic ;
512 
  signal ROMWWS_3_INT_8 : std_logic ;
513 
  signal ROMWWS_0_INT_7 : std_logic ;
514 
  signal SSRHREADY_INT_51 : std_logic ;
515 
  signal PRHREADY_INT_48 : std_logic ;
516 
  signal NN_11 : std_logic ;
517 
begin
518 
  II_r_acount_qxuHAKL1HAKR: LUT1
519 
  generic map(
520 
    INIT => X"2"
521 
  )
522 
  port map (
523 
    I0 => N_SRO_ADDRESS_3_INT_39,
524 
    O => ACOUNT_QXU(1));
525 
  II_r_acount_qxuHAKL2HAKR: LUT1
526 
  generic map(
527 
    INIT => X"2"
528 
  )
529 
  port map (
530 
    I0 => N_SRO_ADDRESS_4_INT_40,
531 
    O => ACOUNT_QXU(2));
532 
  II_r_acount_qxuHAKL3HAKR: LUT1
533 
  generic map(
534 
    INIT => X"2"
535 
  )
536 
  port map (
537 
    I0 => N_SRO_ADDRESS_5_INT_41,
538 
    O => ACOUNT_QXU(3));
539 
  II_r_acount_qxuHAKL4HAKR: LUT1
540 
  generic map(
541 
    INIT => X"2"
542 
  )
543 
  port map (
544 
    I0 => N_SRO_ADDRESS_6_INT_42,
545 
    O => ACOUNT_QXU(4));
546 
  II_r_acount_qxuHAKL5HAKR: LUT1
547 
  generic map(
548 
    INIT => X"2"
549 
  )
550 
  port map (
551 
    I0 => N_SRO_ADDRESS_7_INT_43,
552 
    O => ACOUNT_QXU(5));
553 
  II_r_acount_qxuHAKL6HAKR: LUT1
554 
  generic map(
555 
    INIT => X"2"
556 
  )
557 
  port map (
558 
    I0 => N_SRO_ADDRESS_8_INT_44,
559 
    O => ACOUNT_QXU(6));
560 
  II_r_acount_qxuHAKL7HAKR: LUT1
561 
  generic map(
562 
    INIT => X"2"
563 
  )
564 
  port map (
565 
    I0 => N_SRO_ADDRESS_9_INT_45,
566 
    O => ACOUNT_QXU(7));
567 
  II_r_acount_qxuHAKL8HAKR: LUT1
568 
  generic map(
569 
    INIT => X"2"
570 
  )
571 
  port map (
572 
    I0 => N_SRO_ADDRESS_10_INT_46,
573 
    O => ACOUNT_QXU(8));
574 
  II_ctrl_v_romsn_1_iv: LUT4_L
575 
  generic map(
576 
    INIT => X"0EEE"
577 
  )
578 
  port map (
579 
    I0 => ROMSN_1_IV_L1,
580 
    I1 => CHANGE_3,
581 
    I2 => HMBSEL_0_INT_33,
582 
    I3 => PRSTATE_0_INT_27,
583 
    LO => ROMSN_1);
584 
  II_v_prstate_1_i_o4_0HAKL2HAKR: LUT4_L
585 
  generic map(
586 
    INIT => X"80AA"
587 
  )
588 
  port map (
589 
    I0 => g0_44,
590 
    I1 => g0_1_0,
591 
    I2 => change_3_f1_d_0_0,
592 
    I3 => prstate_1_i_o4_s(2),
593 
    LO => PRHREADY_6);
594 
  II_v_N_635_i: LUT4_L
595 
  generic map(
596 
    INIT => X"888B"
597 
  )
598 
  port map (
599 
    I0 => D16MUXC_0_4_INT_73,
600 
    I1 => PRSTATE_1_INT_28,
601 
    I2 => PRSTATE_2_INT_29,
602 
    I3 => N_635_I_1,
603 
    LO => N_635_I);
604 
  II_r_d16muxc_0: LUT4_L
605 
  generic map(
606 
    INIT => X"8000"
607 
  )
608 
  port map (
609 
    I0 => BUS16EN_INT_72,
610 
    I1 => D16MUXC_0_1,
611 
    I2 => D16MUXC_0_1_0,
612 
    I3 => D16MUXC_0_4_INT_73,
613 
    LO => D16MUXC_0);
614 
  II_r_acount_lm_0HAKL0HAKR: LUT3_L
615 
  generic map(
616 
    INIT => X"1D"
617 
  )
618 
  port map (
619 
    I0 => N_SRO_ADDRESS_2_INT_38,
620 
    I1 => loadcount_7,
621 
    I2 => ACOUNT_LM_0_1(0),
622 
    LO => ACOUNT_LM(0));
623 
  II_ctrl_v_ws_1_0HAKL1HAKR: LUT3_L
624 
  generic map(
625 
    INIT => X"D8"
626 
  )
627 
  port map (
628 
    I0 => N_371_INT_71,
629 
    I1 => WS_1_0_BM(1),
630 
    I2 => WS_1_0_RN_1(1),
631 
    LO => WS_1(1));
632 
  II_ctrl_v_ws_1HAKL2HAKR: LUT4_L
633 
  generic map(
634 
    INIT => X"1141"
635 
  )
636 
  port map (
637 
    I0 => N_371_INT_71,
638 
    I1 => WS_1_L1,
639 
    I2 => g0_23,
640 
    I3 => WS_1_L1_0,
641 
    LO => WS_1(2));
642 
  II_ctrl_v_ssrstate_1_0HAKL3HAKR: LUT4_L
643 
  generic map(
644 
    INIT => X"B333"
645 
  )
646 
  port map (
647 
    I0 => SSRSTATE_1_0_D_BM(3),
648 
    I1 => SSRSTATE_1_0_1(3),
649 
    I2 => SSRSTATE_1_M2S2_0,
650 
    I3 => ssrstate_2_sqmuxa_i,
651 
    LO => SSRSTATE_1(3));
652 
  II_ctrl_v_iosn_9_iv: LUT4_L
653 
  generic map(
654 
    INIT => X"0EEE"
655 
  )
656 
  port map (
657 
    I0 => IOSN_9_IV_L1,
658 
    I1 => CHANGE_3,
659 
    I2 => HMBSEL_2_INT_35,
660 
    I3 => PRSTATE_0_INT_27,
661 
    LO => IOSN_9);
662 
  II_ctrl_v_N_619_i: LUT4_L
663 
  generic map(
664 
    INIT => X"AFBF"
665 
  )
666 
  port map (
667 
    I0 => N_317,
668 
    I1 => N_619_I_L1,
669 
    I2 => BWN_1_0_O3(1),
670 
    I3 => bwn_1_sqmuxa_2_d_0_2,
671 
    LO => N_619_I);
672 
  II_ctrl_v_N_620_i: LUT4_L
673 
  generic map(
674 
    INIT => X"73FF"
675 
  )
676 
  port map (
677 
    I0 => hsize_1(1),
678 
    I1 => bwn_1_0_o3_0,
679 
    I2 => haddr_0,
680 
    I3 => bwn_1_sqmuxa_2_d,
681 
    LO => N_620_I);
682 
  II_r_prstate_iHAKL1HAKR: INV port map (
683 
      I => PRSTATE_1_INT_28,
684 
      O => PRSTATE_I(1));
685 
  II_ctrl_v_rst_i: INV port map (
686 
      I => rst,
687 
      O => RST_I);
688 
  II_r_oen: FDPE port map (
689 
      Q => n_sro_oen,
690 
      D => OEN_1,
691 
      C => clk,
692 
      PRE => RST_I,
693 
      CE => OEN_1_SQMUXA_2_I);
694 
  II_r_bwnHAKL0HAKR: FDE port map (
695 
      Q => n_sro_wrn(0),
696 
      D => N_620_I,
697 
      C => clk,
698 
      CE => BWN_1_SQMUXA_3_I);
699 
  II_r_bwnHAKL1HAKR: FDE port map (
700 
      Q => n_sro_wrn(1),
701 
      D => N_619_I,
702 
      C => clk,
703 
      CE => BWN_1_SQMUXA_3_I);
704 
  II_r_bwnHAKL2HAKR: FDE port map (
705 
      Q => n_sro_wrn(2),
706 
      D => N_618_i,
707 
      C => clk,
708 
      CE => BWN_1_SQMUXA_3_I);
709 
  II_r_bwnHAKL3HAKR: FDE port map (
710 
      Q => n_sro_wrn(3),
711 
      D => N_617_I,
712 
      C => clk,
713 
      CE => BWN_1_SQMUXA_3_I);
714 
  II_r_iosn: FDPE port map (
715 
      Q => N_SRO_IOSN_INT_70,
716 
      D => IOSN_9,
717 
      C => clk,
718 
      PRE => RST_I,
719 
      CE => N_599_I);
720 
  II_r_ramsn: FDPE port map (
721 
      Q => n_sro_ramsn(0),
722 
      D => N_574_i,
723 
      C => clk,
724 
      PRE => RST_I,
725 
      CE => SSRSTATE_9);
726 
  II_r_hwdataoutHAKL0HAKR: FDE port map (
727 
      Q => n_sro_data(0),
728 
      D => HWDATAOUT_1(0),
729 
      C => clk,
730 
      CE => PRSTATE_I(1));
731 
  II_r_hwdataoutHAKL1HAKR: FDE port map (
732 
      Q => n_sro_data(1),
733 
      D => HWDATAOUT_1(1),
734 
      C => clk,
735 
      CE => PRSTATE_I(1));
736 
  II_r_hwdataoutHAKL2HAKR: FDE port map (
737 
      Q => n_sro_data(2),
738 
      D => HWDATAOUT_1(2),
739 
      C => clk,
740 
      CE => PRSTATE_I(1));
741 
  II_r_hwdataoutHAKL3HAKR: FDE port map (
742 
      Q => n_sro_data(3),
743 
      D => HWDATAOUT_1(3),
744 
      C => clk,
745 
      CE => PRSTATE_I(1));
746 
  II_r_hwdataoutHAKL4HAKR: FDE port map (
747 
      Q => n_sro_data(4),
748 
      D => HWDATAOUT_1(4),
749 
      C => clk,
750 
      CE => PRSTATE_I(1));
751 
  II_r_hwdataoutHAKL5HAKR: FDE port map (
752 
      Q => n_sro_data(5),
753 
      D => HWDATAOUT_1(5),
754 
      C => clk,
755 
      CE => PRSTATE_I(1));
756 
  II_r_hwdataoutHAKL6HAKR: FDE port map (
757 
      Q => n_sro_data(6),
758 
      D => HWDATAOUT_1(6),
759 
      C => clk,
760 
      CE => PRSTATE_I(1));
761 
  II_r_hwdataoutHAKL7HAKR: FDE port map (
762 
      Q => n_sro_data(7),
763 
      D => HWDATAOUT_1(7),
764 
      C => clk,
765 
      CE => PRSTATE_I(1));
766 
  II_r_hwdataoutHAKL8HAKR: FDE port map (
767 
      Q => n_sro_data(8),
768 
      D => HWDATAOUT_1(8),
769 
      C => clk,
770 
      CE => PRSTATE_I(1));
771 
  II_r_hwdataoutHAKL9HAKR: FDE port map (
772 
      Q => n_sro_data(9),
773 
      D => HWDATAOUT_1(9),
774 
      C => clk,
775 
      CE => PRSTATE_I(1));
776 
  II_r_hwdataoutHAKL10HAKR: FDE port map (
777 
      Q => n_sro_data(10),
778 
      D => HWDATAOUT_1(10),
779 
      C => clk,
780 
      CE => PRSTATE_I(1));
781 
  II_r_hwdataoutHAKL11HAKR: FDE port map (
782 
      Q => n_sro_data(11),
783 
      D => HWDATAOUT_1(11),
784 
      C => clk,
785 
      CE => PRSTATE_I(1));
786 
  II_r_hwdataoutHAKL12HAKR: FDE port map (
787 
      Q => n_sro_data(12),
788 
      D => HWDATAOUT_1(12),
789 
      C => clk,
790 
      CE => PRSTATE_I(1));
791 
  II_r_hwdataoutHAKL13HAKR: FDE port map (
792 
      Q => n_sro_data(13),
793 
      D => HWDATAOUT_1(13),
794 
      C => clk,
795 
      CE => PRSTATE_I(1));
796 
  II_r_hwdataoutHAKL14HAKR: FDE port map (
797 
      Q => n_sro_data(14),
798 
      D => HWDATAOUT_1(14),
799 
      C => clk,
800 
      CE => PRSTATE_I(1));
801 
  II_r_hwdataoutHAKL15HAKR: FDE port map (
802 
      Q => n_sro_data(15),
803 
      D => HWDATAOUT_1(15),
804 
      C => clk,
805 
      CE => PRSTATE_I(1));
806 
  II_r_hwdataoutHAKL16HAKR: FDE port map (
807 
      Q => n_sro_data(16),
808 
      D => HWDATAOUT_1(16),
809 
      C => clk,
810 
      CE => PRSTATE_I(1));
811 
  II_r_hwdataoutHAKL17HAKR: FDE port map (
812 
      Q => n_sro_data(17),
813 
      D => HWDATAOUT_1(17),
814 
      C => clk,
815 
      CE => PRSTATE_I(1));
816 
  II_r_hwdataoutHAKL18HAKR: FDE port map (
817 
      Q => n_sro_data(18),
818 
      D => HWDATAOUT_1(18),
819 
      C => clk,
820 
      CE => PRSTATE_I(1));
821 
  II_r_hwdataoutHAKL19HAKR: FDE port map (
822 
      Q => n_sro_data(19),
823 
      D => HWDATAOUT_1(19),
824 
      C => clk,
825 
      CE => PRSTATE_I(1));
826 
  II_r_hwdataoutHAKL20HAKR: FDE port map (
827 
      Q => n_sro_data(20),
828 
      D => HWDATAOUT_1(20),
829 
      C => clk,
830 
      CE => PRSTATE_I(1));
831 
  II_r_hwdataoutHAKL21HAKR: FDE port map (
832 
      Q => n_sro_data(21),
833 
      D => HWDATAOUT_1(21),
834 
      C => clk,
835 
      CE => PRSTATE_I(1));
836 
  II_r_hwdataoutHAKL22HAKR: FDE port map (
837 
      Q => n_sro_data(22),
838 
      D => HWDATAOUT_1(22),
839 
      C => clk,
840 
      CE => PRSTATE_I(1));
841 
  II_r_hwdataoutHAKL23HAKR: FDE port map (
842 
      Q => n_sro_data(23),
843 
      D => HWDATAOUT_1(23),
844 
      C => clk,
845 
      CE => PRSTATE_I(1));
846 
  II_r_hwdataoutHAKL24HAKR: FDE port map (
847 
      Q => n_sro_data(24),
848 
      D => HWDATAOUT_1(24),
849 
      C => clk,
850 
      CE => PRSTATE_I(1));
851 
  II_r_hwdataoutHAKL25HAKR: FDE port map (
852 
      Q => n_sro_data(25),
853 
      D => HWDATAOUT_1(25),
854 
      C => clk,
855 
      CE => PRSTATE_I(1));
856 
  II_r_hwdataoutHAKL26HAKR: FDE port map (
857 
      Q => n_sro_data(26),
858 
      D => HWDATAOUT_1(26),
859 
      C => clk,
860 
      CE => PRSTATE_I(1));
861 
  II_r_hwdataoutHAKL27HAKR: FDE port map (
862 
      Q => n_sro_data(27),
863 
      D => HWDATAOUT_1(27),
864 
      C => clk,
865 
      CE => PRSTATE_I(1));
866 
  II_r_hwdataoutHAKL28HAKR: FDE port map (
867 
      Q => n_sro_data(28),
868 
      D => HWDATAOUT_1(28),
869 
      C => clk,
870 
      CE => PRSTATE_I(1));
871 
  II_r_hwdataoutHAKL29HAKR: FDE port map (
872 
      Q => n_sro_data(29),
873 
      D => HWDATAOUT_1(29),
874 
      C => clk,
875 
      CE => PRSTATE_I(1));
876 
  II_r_hwdataoutHAKL30HAKR: FDE port map (
877 
      Q => n_sro_data(30),
878 
      D => HWDATAOUT_1(30),
879 
      C => clk,
880 
      CE => PRSTATE_I(1));
881 
  II_r_hwdataoutHAKL31HAKR: FDE port map (
882 
      Q => n_sro_data(31),
883 
      D => HWDATAOUT_1(31),
884 
      C => clk,
885 
      CE => PRSTATE_I(1));
886 
  II_r_mcfg1_romwidthHAKL0HAKR: FDE port map (
887 
      Q => ROMWIDTH(0),
888 
      D => ROMWIDTH_1(0),
889 
      C => clk,
890 
      CE => BEXCEN_1_SQMUXA_I);
891 
  II_r_mcfg1_romwidthHAKL1HAKR: FDE port map (
892 
      Q => ROMWIDTH(1),
893 
      D => ROMWIDTH_1(1),
894 
      C => clk,
895 
      CE => BEXCEN_1_SQMUXA_I);
896 
  II_r_data16HAKL0HAKR: FDE port map (
897 
      Q => DATA16(0),
898 
      D => HRDATA(16),
899 
      C => clk,
900 
      CE => DATA16_0_SQMUXA);
901 
  II_r_data16HAKL1HAKR: FDE port map (
902 
      Q => DATA16(1),
903 
      D => HRDATA(17),
904 
      C => clk,
905 
      CE => DATA16_0_SQMUXA);
906 
  II_r_data16HAKL2HAKR: FDE port map (
907 
      Q => DATA16(2),
908 
      D => HRDATA(18),
909 
      C => clk,
910 
      CE => DATA16_0_SQMUXA);
911 
  II_r_data16HAKL3HAKR: FDE port map (
912 
      Q => DATA16(3),
913 
      D => HRDATA(19),
914 
      C => clk,
915 
      CE => DATA16_0_SQMUXA);
916 
  II_r_data16HAKL4HAKR: FDE port map (
917 
      Q => DATA16(4),
918 
      D => HRDATA(20),
919 
      C => clk,
920 
      CE => DATA16_0_SQMUXA);
921 
  II_r_data16HAKL5HAKR: FDE port map (
922 
      Q => DATA16(5),
923 
      D => HRDATA(21),
924 
      C => clk,
925 
      CE => DATA16_0_SQMUXA);
926 
  II_r_data16HAKL6HAKR: FDE port map (
927 
      Q => DATA16(6),
928 
      D => HRDATA(22),
929 
      C => clk,
930 
      CE => DATA16_0_SQMUXA);
931 
  II_r_data16HAKL7HAKR: FDE port map (
932 
      Q => DATA16(7),
933 
      D => HRDATA(23),
934 
      C => clk,
935 
      CE => DATA16_0_SQMUXA);
936 
  II_r_data16HAKL8HAKR: FDE port map (
937 
      Q => DATA16(8),
938 
      D => HRDATA(24),
939 
      C => clk,
940 
      CE => DATA16_0_SQMUXA);
941 
  II_r_data16HAKL9HAKR: FDE port map (
942 
      Q => DATA16(9),
943 
      D => HRDATA(25),
944 
      C => clk,
945 
      CE => DATA16_0_SQMUXA);
946 
  II_r_data16HAKL10HAKR: FDE port map (
947 
      Q => DATA16(10),
948 
      D => HRDATA(26),
949 
      C => clk,
950 
      CE => DATA16_0_SQMUXA);
951 
  II_r_data16HAKL11HAKR: FDE port map (
952 
      Q => DATA16(11),
953 
      D => HRDATA(27),
954 
      C => clk,
955 
      CE => DATA16_0_SQMUXA);
956 
  II_r_data16HAKL12HAKR: FDE port map (
957 
      Q => DATA16(12),
958 
      D => HRDATA(28),
959 
      C => clk,
960 
      CE => DATA16_0_SQMUXA);
961 
  II_r_data16HAKL13HAKR: FDE port map (
962 
      Q => DATA16(13),
963 
      D => HRDATA(29),
964 
      C => clk,
965 
      CE => DATA16_0_SQMUXA);
966 
  II_r_data16HAKL14HAKR: FDE port map (
967 
      Q => DATA16(14),
968 
      D => HRDATA(30),
969 
      C => clk,
970 
      CE => DATA16_0_SQMUXA);
971 
  II_r_data16HAKL15HAKR: FDE port map (
972 
      Q => DATA16(15),
973 
      D => HRDATA(31),
974 
      C => clk,
975 
      CE => DATA16_0_SQMUXA);
976 
  II_r_sizeHAKL0HAKR: FDE port map (
977 
      Q => SIZE_0_INT_25,
978 
      D => n_ahbsi_hsize(0),
979 
      C => clk,
980 
      CE => HMBSEL_0_SQMUXA);
981 
  II_r_sizeHAKL1HAKR: FDE port map (
982 
      Q => SIZE_1_INT_26,
983 
      D => n_ahbsi_hsize(1),
984 
      C => clk,
985 
      CE => HMBSEL_0_SQMUXA);
986 
  II_r_hwrite: FDE port map (
987 
      Q => HWRITE,
988 
      D => n_ahbsi_hwrite,
989 
      C => clk,
990 
      CE => HMBSEL_0_SQMUXA);
991 
  II_r_hwdataHAKL0HAKR: FDE port map (
992 
      Q => HWDATA(0),
993 
      D => n_ahbsi_hwdata(0),
994 
      C => clk,
995 
      CE => SSRSTATE_1_INT_21);
996 
  II_r_hwdataHAKL1HAKR: FDE port map (
997 
      Q => HWDATA(1),
998 
      D => n_ahbsi_hwdata(1),
999 
      C => clk,
1000 
      CE => SSRSTATE_1_INT_21);
1001 
  II_r_hwdataHAKL2HAKR: FDE port map (
1002 
      Q => HWDATA(2),
1003 
      D => n_ahbsi_hwdata(2),
1004 
      C => clk,
1005 
      CE => SSRSTATE_1_INT_21);
1006 
  II_r_hwdataHAKL3HAKR: FDE port map (
1007 
      Q => HWDATA(3),
1008 
      D => n_ahbsi_hwdata(3),
1009 
      C => clk,
1010 
      CE => SSRSTATE_1_INT_21);
1011 
  II_r_hwdataHAKL4HAKR: FDE port map (
1012 
      Q => HWDATA(4),
1013 
      D => n_ahbsi_hwdata(4),
1014 
      C => clk,
1015 
      CE => SSRSTATE_1_INT_21);
1016 
  II_r_hwdataHAKL5HAKR: FDE port map (
1017 
      Q => HWDATA(5),
1018 
      D => n_ahbsi_hwdata(5),
1019 
      C => clk,
1020 
      CE => SSRSTATE_1_INT_21);
1021 
  II_r_hwdataHAKL6HAKR: FDE port map (
1022 
      Q => HWDATA(6),
1023 
      D => n_ahbsi_hwdata(6),
1024 
      C => clk,
1025 
      CE => SSRSTATE_1_INT_21);
1026 
  II_r_hwdataHAKL7HAKR: FDE port map (
1027 
      Q => HWDATA(7),
1028 
      D => n_ahbsi_hwdata(7),
1029 
      C => clk,
1030 
      CE => SSRSTATE_1_INT_21);
1031 
  II_r_hwdataHAKL8HAKR: FDE port map (
1032 
      Q => HWDATA(8),
1033 
      D => n_ahbsi_hwdata(8),
1034 
      C => clk,
1035 
      CE => SSRSTATE_1_INT_21);
1036 
  II_r_hwdataHAKL9HAKR: FDE port map (
1037 
      Q => HWDATA(9),
1038 
      D => n_ahbsi_hwdata(9),
1039 
      C => clk,
1040 
      CE => SSRSTATE_1_INT_21);
1041 
  II_r_hwdataHAKL10HAKR: FDE port map (
1042 
      Q => HWDATA(10),
1043 
      D => n_ahbsi_hwdata(10),
1044 
      C => clk,
1045 
      CE => SSRSTATE_1_INT_21);
1046 
  II_r_hwdataHAKL11HAKR: FDE port map (
1047 
      Q => HWDATA(11),
1048 
      D => n_ahbsi_hwdata(11),
1049 
      C => clk,
1050 
      CE => SSRSTATE_1_INT_21);
1051 
  II_r_hwdataHAKL12HAKR: FDE port map (
1052 
      Q => HWDATA(12),
1053 
      D => n_ahbsi_hwdata(12),
1054 
      C => clk,
1055 
      CE => SSRSTATE_1_INT_21);
1056 
  II_r_hwdataHAKL13HAKR: FDE port map (
1057 
      Q => HWDATA(13),
1058 
      D => n_ahbsi_hwdata(13),
1059 
      C => clk,
1060 
      CE => SSRSTATE_1_INT_21);
1061 
  II_r_hwdataHAKL14HAKR: FDE port map (
1062 
      Q => HWDATA(14),
1063 
      D => n_ahbsi_hwdata(14),
1064 
      C => clk,
1065 
      CE => SSRSTATE_1_INT_21);
1066 
  II_r_hwdataHAKL15HAKR: FDE port map (
1067 
      Q => HWDATA(15),
1068 
      D => n_ahbsi_hwdata(15),
1069 
      C => clk,
1070 
      CE => SSRSTATE_1_INT_21);
1071 
  II_r_hwdataHAKL16HAKR: FDE port map (
1072 
      Q => HWDATA(16),
1073 
      D => n_ahbsi_hwdata(16),
1074 
      C => clk,
1075 
      CE => SSRSTATE_1_INT_21);
1076 
  II_r_hwdataHAKL17HAKR: FDE port map (
1077 
      Q => HWDATA(17),
1078 
      D => n_ahbsi_hwdata(17),
1079 
      C => clk,
1080 
      CE => SSRSTATE_1_INT_21);
1081 
  II_r_hwdataHAKL18HAKR: FDE port map (
1082 
      Q => HWDATA(18),
1083 
      D => n_ahbsi_hwdata(18),
1084 
      C => clk,
1085 
      CE => SSRSTATE_1_INT_21);
1086 
  II_r_hwdataHAKL19HAKR: FDE port map (
1087 
      Q => HWDATA(19),
1088 
      D => n_ahbsi_hwdata(19),
1089 
      C => clk,
1090 
      CE => SSRSTATE_1_INT_21);
1091 
  II_r_hwdataHAKL20HAKR: FDE port map (
1092 
      Q => HWDATA(20),
1093 
      D => n_ahbsi_hwdata(20),
1094 
      C => clk,
1095 
      CE => SSRSTATE_1_INT_21);
1096 
  II_r_hwdataHAKL21HAKR: FDE port map (
1097 
      Q => HWDATA(21),
1098 
      D => n_ahbsi_hwdata(21),
1099 
      C => clk,
1100 
      CE => SSRSTATE_1_INT_21);
1101 
  II_r_hwdataHAKL22HAKR: FDE port map (
1102 
      Q => HWDATA(22),
1103 
      D => n_ahbsi_hwdata(22),
1104 
      C => clk,
1105 
      CE => SSRSTATE_1_INT_21);
1106 
  II_r_hwdataHAKL23HAKR: FDE port map (
1107 
      Q => HWDATA(23),
1108 
      D => n_ahbsi_hwdata(23),
1109 
      C => clk,
1110 
      CE => SSRSTATE_1_INT_21);
1111 
  II_r_hwdataHAKL24HAKR: FDE port map (
1112 
      Q => HWDATA(24),
1113 
      D => n_ahbsi_hwdata(24),
1114 
      C => clk,
1115 
      CE => SSRSTATE_1_INT_21);
1116 
  II_r_hwdataHAKL25HAKR: FDE port map (
1117 
      Q => HWDATA(25),
1118 
      D => n_ahbsi_hwdata(25),
1119 
      C => clk,
1120 
      CE => SSRSTATE_1_INT_21);
1121 
  II_r_hwdataHAKL26HAKR: FDE port map (
1122 
      Q => HWDATA(26),
1123 
      D => n_ahbsi_hwdata(26),
1124 
      C => clk,
1125 
      CE => SSRSTATE_1_INT_21);
1126 
  II_r_hwdataHAKL27HAKR: FDE port map (
1127 
      Q => HWDATA(27),
1128 
      D => n_ahbsi_hwdata(27),
1129 
      C => clk,
1130 
      CE => SSRSTATE_1_INT_21);
1131 
  II_r_hwdataHAKL28HAKR: FDE port map (
1132 
      Q => HWDATA(28),
1133 
      D => n_ahbsi_hwdata(28),
1134 
      C => clk,
1135 
      CE => SSRSTATE_1_INT_21);
1136 
  II_r_hwdataHAKL29HAKR: FDE port map (
1137 
      Q => HWDATA(29),
1138 
      D => n_ahbsi_hwdata(29),
1139 
      C => clk,
1140 
      CE => SSRSTATE_1_INT_21);
1141 
  II_r_hwdataHAKL30HAKR: FDE port map (
1142 
      Q => HWDATA(30),
1143 
      D => n_ahbsi_hwdata(30),
1144 
      C => clk,
1145 
      CE => SSRSTATE_1_INT_21);
1146 
  II_r_hwdataHAKL31HAKR: FDE port map (
1147 
      Q => HWDATA(31),
1148 
      D => n_ahbsi_hwdata(31),
1149 
      C => clk,
1150 
      CE => SSRSTATE_1_INT_21);
1151 
  II_r_hrdataHAKL22HAKR: FD port map (
1152 
      Q => HRDATA(22),
1153 
      D => n_sri_data(22),
1154 
      C => clk);
1155 
  II_r_hrdataHAKL23HAKR: FD port map (
1156 
      Q => HRDATA(23),
1157 
      D => n_sri_data(23),
1158 
      C => clk);
1159 
  II_r_hrdataHAKL24HAKR: FD port map (
1160 
      Q => HRDATA(24),
1161 
      D => n_sri_data(24),
1162 
      C => clk);
1163 
  II_r_hrdataHAKL25HAKR: FD port map (
1164 
      Q => HRDATA(25),
1165 
      D => n_sri_data(25),
1166 
      C => clk);
1167 
  II_r_hrdataHAKL26HAKR: FD port map (
1168 
      Q => HRDATA(26),
1169 
      D => n_sri_data(26),
1170 
      C => clk);
1171 
  II_r_hrdataHAKL27HAKR: FD port map (
1172 
      Q => HRDATA(27),
1173 
      D => n_sri_data(27),
1174 
      C => clk);
1175 
  II_r_hrdataHAKL28HAKR: FD port map (
1176 
      Q => HRDATA(28),
1177 
      D => n_sri_data(28),
1178 
      C => clk);
1179 
  II_r_hrdataHAKL29HAKR: FD port map (
1180 
      Q => HRDATA(29),
1181 
      D => n_sri_data(29),
1182 
      C => clk);
1183 
  II_r_hrdataHAKL30HAKR: FD port map (
1184 
      Q => HRDATA(30),
1185 
      D => n_sri_data(30),
1186 
      C => clk);
1187 
  II_r_hrdataHAKL31HAKR: FD port map (
1188 
      Q => HRDATA(31),
1189 
      D => n_sri_data(31),
1190 
      C => clk);
1191 
  II_r_hrdataHAKL7HAKR: FD port map (
1192 
      Q => HRDATA(7),
1193 
      D => n_sri_data(7),
1194 
      C => clk);
1195 
  II_r_hrdataHAKL8HAKR: FD port map (
1196 
      Q => HRDATA(8),
1197 
      D => n_sri_data(8),
1198 
      C => clk);
1199 
  II_r_hrdataHAKL9HAKR: FD port map (
1200 
      Q => HRDATA(9),
1201 
      D => n_sri_data(9),
1202 
      C => clk);
1203 
  II_r_hrdataHAKL10HAKR: FD port map (
1204 
      Q => HRDATA(10),
1205 
      D => n_sri_data(10),
1206 
      C => clk);
1207 
  II_r_hrdataHAKL11HAKR: FD port map (
1208 
      Q => HRDATA(11),
1209 
      D => n_sri_data(11),
1210 
      C => clk);
1211 
  II_r_hrdataHAKL12HAKR: FD port map (
1212 
      Q => HRDATA(12),
1213 
      D => n_sri_data(12),
1214 
      C => clk);
1215 
  II_r_hrdataHAKL13HAKR: FD port map (
1216 
      Q => HRDATA(13),
1217 
      D => n_sri_data(13),
1218 
      C => clk);
1219 
  II_r_hrdataHAKL14HAKR: FD port map (
1220 
      Q => HRDATA(14),
1221 
      D => n_sri_data(14),
1222 
      C => clk);
1223 
  II_r_hrdataHAKL15HAKR: FD port map (
1224 
      Q => HRDATA(15),
1225 
      D => n_sri_data(15),
1226 
      C => clk);
1227 
  II_r_hrdataHAKL16HAKR: FD port map (
1228 
      Q => HRDATA(16),
1229 
      D => n_sri_data(16),
1230 
      C => clk);
1231 
  II_r_hrdataHAKL17HAKR: FD port map (
1232 
      Q => HRDATA(17),
1233 
      D => n_sri_data(17),
1234 
      C => clk);
1235 
  II_r_hrdataHAKL18HAKR: FD port map (
1236 
      Q => HRDATA(18),
1237 
      D => n_sri_data(18),
1238 
      C => clk);
1239 
  II_r_hrdataHAKL19HAKR: FD port map (
1240 
      Q => HRDATA(19),
1241 
      D => n_sri_data(19),
1242 
      C => clk);
1243 
  II_r_hrdataHAKL20HAKR: FD port map (
1244 
      Q => HRDATA(20),
1245 
      D => n_sri_data(20),
1246 
      C => clk);
1247 
  II_r_hrdataHAKL21HAKR: FD port map (
1248 
      Q => HRDATA(21),
1249 
      D => n_sri_data(21),
1250 
      C => clk);
1251 
  II_r_hrdataHAKL0HAKR: FD port map (
1252 
      Q => HRDATA(0),
1253 
      D => n_sri_data(0),
1254 
      C => clk);
1255 
  II_r_hrdataHAKL1HAKR: FD port map (
1256 
      Q => HRDATA(1),
1257 
      D => n_sri_data(1),
1258 
      C => clk);
1259 
  II_r_hrdataHAKL2HAKR: FD port map (
1260 
      Q => HRDATA(2),
1261 
      D => n_sri_data(2),
1262 
      C => clk);
1263 
  II_r_hrdataHAKL3HAKR: FD port map (
1264 
      Q => HRDATA(3),
1265 
      D => n_sri_data(3),
1266 
      C => clk);
1267 
  II_r_hrdataHAKL4HAKR: FD port map (
1268 
      Q => HRDATA(4),
1269 
      D => n_sri_data(4),
1270 
      C => clk);
1271 
  II_r_hrdataHAKL5HAKR: FD port map (
1272 
      Q => HRDATA(5),
1273 
      D => n_sri_data(5),
1274 
      C => clk);
1275 
  II_r_hrdataHAKL6HAKR: FD port map (
1276 
      Q => HRDATA(6),
1277 
      D => n_sri_data(6),
1278 
      C => clk);
1279 
  II_r_hmbselHAKL0HAKR: FDCE port map (
1280 
      Q => HMBSEL_0_INT_33,
1281 
      D => n_ahbsi_hmbsel(0),
1282 
      C => clk,
1283 
      CLR => RST_I,
1284 
      CE => HMBSEL_0_SQMUXA);
1285 
  II_r_haddrHAKL21HAKR: FDE port map (
1286 
      Q => n_sro_address(21),
1287 
      D => n_ahbsi_haddr(21),
1288 
      C => clk,
1289 
      CE => HMBSEL_0_SQMUXA);
1290 
  II_r_haddrHAKL22HAKR: FDE port map (
1291 
      Q => n_sro_address(22),
1292 
      D => n_ahbsi_haddr(22),
1293 
      C => clk,
1294 
      CE => HMBSEL_0_SQMUXA);
1295 
  II_r_haddrHAKL23HAKR: FDE port map (
1296 
      Q => n_sro_address(23),
1297 
      D => n_ahbsi_haddr(23),
1298 
      C => clk,
1299 
      CE => HMBSEL_0_SQMUXA);
1300 
  II_r_haddrHAKL24HAKR: FDE port map (
1301 
      Q => n_sro_address(24),
1302 
      D => n_ahbsi_haddr(24),
1303 
      C => clk,
1304 
      CE => HMBSEL_0_SQMUXA);
1305 
  II_r_haddrHAKL25HAKR: FDE port map (
1306 
      Q => n_sro_address(25),
1307 
      D => n_ahbsi_haddr(25),
1308 
      C => clk,
1309 
      CE => HMBSEL_0_SQMUXA);
1310 
  II_r_haddrHAKL26HAKR: FDE port map (
1311 
      Q => n_sro_address(26),
1312 
      D => n_ahbsi_haddr(26),
1313 
      C => clk,
1314 
      CE => HMBSEL_0_SQMUXA);
1315 
  II_r_haddrHAKL27HAKR: FDE port map (
1316 
      Q => n_sro_address(27),
1317 
      D => n_ahbsi_haddr(27),
1318 
      C => clk,
1319 
      CE => HMBSEL_0_SQMUXA);
1320 
  II_r_haddrHAKL28HAKR: FDE port map (
1321 
      Q => n_sro_address(28),
1322 
      D => n_ahbsi_haddr(28),
1323 
      C => clk,
1324 
      CE => HMBSEL_0_SQMUXA);
1325 
  II_r_haddrHAKL29HAKR: FDE port map (
1326 
      Q => n_sro_address(29),
1327 
      D => n_ahbsi_haddr(29),
1328 
      C => clk,
1329 
      CE => HMBSEL_0_SQMUXA);
1330 
  II_r_haddrHAKL30HAKR: FDE port map (
1331 
      Q => n_sro_address(30),
1332 
      D => n_ahbsi_haddr(30),
1333 
      C => clk,
1334 
      CE => HMBSEL_0_SQMUXA);
1335 
  II_r_haddrHAKL31HAKR: FDE port map (
1336 
      Q => n_sro_address(31),
1337 
      D => n_ahbsi_haddr(31),
1338 
      C => clk,
1339 
      CE => HMBSEL_0_SQMUXA);
1340 
  II_r_hmbselHAKL2HAKR: FDCE port map (
1341 
      Q => HMBSEL_2_INT_35,
1342 
      D => n_ahbsi_hmbsel(2),
1343 
      C => clk,
1344 
      CLR => RST_I,
1345 
      CE => HMBSEL_0_SQMUXA);
1346 
  II_r_hmbselHAKL1HAKR: FDCE port map (
1347 
      Q => HMBSEL_1_INT_34,
1348 
      D => n_ahbsi_hmbsel(1),
1349 
      C => clk,
1350 
      CLR => RST_I,
1351 
      CE => HMBSEL_0_SQMUXA);
1352 
  II_r_haddrHAKL6HAKR: FDE port map (
1353 
      Q => HADDR(6),
1354 
      D => n_ahbsi_haddr(6),
1355 
      C => clk,
1356 
      CE => HMBSEL_0_SQMUXA);
1357 
  II_r_haddrHAKL7HAKR: FDE port map (
1358 
      Q => HADDR(7),
1359 
      D => n_ahbsi_haddr(7),
1360 
      C => clk,
1361 
      CE => HMBSEL_0_SQMUXA);
1362 
  II_r_haddrHAKL8HAKR: FDE port map (
1363 
      Q => HADDR(8),
1364 
      D => n_ahbsi_haddr(8),
1365 
      C => clk,
1366 
      CE => HMBSEL_0_SQMUXA);
1367 
  II_r_haddrHAKL9HAKR: FDE port map (
1368 
      Q => HADDR(9),
1369 
      D => n_ahbsi_haddr(9),
1370 
      C => clk,
1371 
      CE => HMBSEL_0_SQMUXA);
1372 
  II_r_haddrHAKL10HAKR: FDE port map (
1373 
      Q => HADDR(10),
1374 
      D => n_ahbsi_haddr(10),
1375 
      C => clk,
1376 
      CE => HMBSEL_0_SQMUXA);
1377 
  II_r_haddrHAKL11HAKR: FDE port map (
1378 
      Q => HADDR(11),
1379 
      D => n_ahbsi_haddr(11),
1380 
      C => clk,
1381 
      CE => HMBSEL_0_SQMUXA);
1382 
  II_r_haddrHAKL12HAKR: FDE port map (
1383 
      Q => n_sro_address(12),
1384 
      D => n_ahbsi_haddr(12),
1385 
      C => clk,
1386 
      CE => HMBSEL_0_SQMUXA);
1387 
  II_r_haddrHAKL13HAKR: FDE port map (
1388 
      Q => n_sro_address(13),
1389 
      D => n_ahbsi_haddr(13),
1390 
      C => clk,
1391 
      CE => HMBSEL_0_SQMUXA);
1392 
  II_r_haddrHAKL14HAKR: FDE port map (
1393 
      Q => n_sro_address(14),
1394 
      D => n_ahbsi_haddr(14),
1395 
      C => clk,
1396 
      CE => HMBSEL_0_SQMUXA);
1397 
  II_r_haddrHAKL15HAKR: FDE port map (
1398 
      Q => n_sro_address(15),
1399 
      D => n_ahbsi_haddr(15),
1400 
      C => clk,
1401 
      CE => HMBSEL_0_SQMUXA);
1402 
  II_r_haddrHAKL16HAKR: FDE port map (
1403 
      Q => n_sro_address(16),
1404 
      D => n_ahbsi_haddr(16),
1405 
      C => clk,
1406 
      CE => HMBSEL_0_SQMUXA);
1407 
  II_r_haddrHAKL17HAKR: FDE port map (
1408 
      Q => n_sro_address(17),
1409 
      D => n_ahbsi_haddr(17),
1410 
      C => clk,
1411 
      CE => HMBSEL_0_SQMUXA);
1412 
  II_r_haddrHAKL18HAKR: FDE port map (
1413 
      Q => n_sro_address(18),
1414 
      D => n_ahbsi_haddr(18),
1415 
      C => clk,
1416 
      CE => HMBSEL_0_SQMUXA);
1417 
  II_r_haddrHAKL19HAKR: FDE port map (
1418 
      Q => n_sro_address(19),
1419 
      D => n_ahbsi_haddr(19),
1420 
      C => clk,
1421 
      CE => HMBSEL_0_SQMUXA);
1422 
  II_r_haddrHAKL20HAKR: FDE port map (
1423 
      Q => n_sro_address(20),
1424 
      D => n_ahbsi_haddr(20),
1425 
      C => clk,
1426 
      CE => HMBSEL_0_SQMUXA);
1427 
  II_r_ssrstateHAKL4HAKR: FD port map (
1428 
      Q => SSRSTATE_4_INT_24,
1429 
      D => ssrstate_1_2,
1430 
      C => clk);
1431 
  II_r_ssrstateHAKL3HAKR: FD port map (
1432 
      Q => SSRSTATE_3_INT_23,
1433 
      D => SSRSTATE_1(3),
1434 
      C => clk);
1435 
  II_r_ssrstateHAKL2HAKR: FD port map (
1436 
      Q => SSRSTATE_2_INT_22,
1437 
      D => SSRSTATE_1(2),
1438 
      C => clk);
1439 
  II_r_haddrHAKL0HAKR: FDE port map (
1440 
      Q => N_SRO_ADDRESS_0_INT_36,
1441 
      D => n_ahbsi_haddr(0),
1442 
      C => clk,
1443 
      CE => HMBSEL_0_SQMUXA);
1444 
  II_r_haddrHAKL2HAKR: FDE port map (
1445 
      Q => HADDR(2),
1446 
      D => n_ahbsi_haddr(2),
1447 
      C => clk,
1448 
      CE => HMBSEL_0_SQMUXA);
1449 
  II_r_haddrHAKL3HAKR: FDE port map (
1450 
      Q => HADDR(3),
1451 
      D => n_ahbsi_haddr(3),
1452 
      C => clk,
1453 
      CE => HMBSEL_0_SQMUXA);
1454 
  II_r_haddrHAKL4HAKR: FDE port map (
1455 
      Q => HADDR(4),
1456 
      D => n_ahbsi_haddr(4),
1457 
      C => clk,
1458 
      CE => HMBSEL_0_SQMUXA);
1459 
  II_r_haddrHAKL5HAKR: FDE port map (
1460 
      Q => HADDR(5),
1461 
      D => n_ahbsi_haddr(5),
1462 
      C => clk,
1463 
      CE => HMBSEL_0_SQMUXA);
1464 
  II_r_wsHAKL2HAKR: FD port map (
1465 
      Q => WS_2_INT_18,
1466 
      D => WS_1(2),
1467 
      C => clk);
1468 
  II_r_wsHAKL3HAKR: FD port map (
1469 
      Q => WS_3_INT_19,
1470 
      D => ws_1_3,
1471 
      C => clk);
1472 
  II_r_wsHAKL0HAKR: FD port map (
1473 
      Q => WS_0_INT_16,
1474 
      D => ws_1_0,
1475 
      C => clk);
1476 
  II_r_wsHAKL1HAKR: FD port map (
1477 
      Q => WS_1_INT_17,
1478 
      D => WS_1(1),
1479 
      C => clk);
1480 
  II_r_bdrive: FDP port map (
1481 
      Q => N_SRO_BDRIVE_3_INT_15,
1482 
      D => BDRIVE_1,
1483 
      C => clk,
1484 
      PRE => RST_I);
1485 
  II_r_change: FDC port map (
1486 
      Q => CHANGE_INT_69,
1487 
      D => CHANGE_3,
1488 
      C => clk,
1489 
      CLR => RST_I);
1490 
  II_r_acountHAKL0HAKR: FD port map (
1491 
      Q => N_SRO_ADDRESS_2_INT_38,
1492 
      D => ACOUNT_LM(0),
1493 
      C => clk);
1494 
  II_r_acountHAKL1HAKR: FD port map (
1495 
      Q => N_SRO_ADDRESS_3_INT_39,
1496 
      D => ACOUNT_LM(1),
1497 
      C => clk);
1498 
  II_r_acountHAKL2HAKR: FD port map (
1499 
      Q => N_SRO_ADDRESS_4_INT_40,
1500 
      D => ACOUNT_LM(2),
1501 
      C => clk);
1502 
  II_r_acountHAKL3HAKR: FD port map (
1503 
      Q => N_SRO_ADDRESS_5_INT_41,
1504 
      D => ACOUNT_LM(3),
1505 
      C => clk);
1506 
  II_r_acountHAKL4HAKR: FD port map (
1507 
      Q => N_SRO_ADDRESS_6_INT_42,
1508 
      D => ACOUNT_LM(4),
1509 
      C => clk);
1510 
  II_r_acountHAKL5HAKR: FD port map (
1511 
      Q => N_SRO_ADDRESS_7_INT_43,
1512 
      D => ACOUNT_LM(5),
1513 
      C => clk);
1514 
  II_r_acountHAKL6HAKR: FD port map (
1515 
      Q => N_SRO_ADDRESS_8_INT_44,
1516 
      D => ACOUNT_LM(6),
1517 
      C => clk);
1518 
  II_r_acountHAKL7HAKR: FD port map (
1519 
      Q => N_SRO_ADDRESS_9_INT_45,
1520 
      D => ACOUNT_LM(7),
1521 
      C => clk);
1522 
  II_r_acountHAKL8HAKR: FD port map (
1523 
      Q => N_SRO_ADDRESS_10_INT_46,
1524 
      D => ACOUNT_LM(8),
1525 
      C => clk);
1526 
  II_r_acountHAKL9HAKR: FD port map (
1527 
      Q => N_SRO_ADDRESS_11_INT_47,
1528 
      D => ACOUNT_LM(9),
1529 
      C => clk);
1530 
  II_v_oen_1_sqmuxa_2_i_L4: LUT4_L
1531 
  generic map(
1532 
    INIT => X"0400"
1533 
  )
1534 
  port map (
1535 
    I0 => UN1_AHBSI_INT_68,
1536 
    I1 => change_3_f0,
1537 
    I2 => HMBSEL_4_1_INT_14,
1538 
    I3 => HSEL_5_INT_67,
1539 
    LO => OEN_1_SQMUXA_2_I_L4);
1540 
  II_v_oen_1_sqmuxa_2_i_L6: LUT4_L
1541 
  generic map(
1542 
    INIT => X"4303"
1543 
  )
1544 
  port map (
1545 
    I0 => OEN_1_SQMUXA_2_I_L4,
1546 
    I1 => PRSTATE_5_INT_32,
1547 
    I2 => PRSTATE_1,
1548 
    I3 => hsel_1(0),
1549 
    LO => OEN_1_SQMUXA_2_I_L6);
1550 
  II_v_oen_1_sqmuxa_2_i: LUT4
1551 
  generic map(
1552 
    INIT => X"DFCC"
1553 
  )
1554 
  port map (
1555 
    I0 => N_654,
1556 
    I1 => OEN_1_SQMUXA_2_I_L6,
1557 
    I2 => SSRSTATE_2_INT_22,
1558 
    I3 => SSRSTATE_12_1,
1559 
    O => OEN_1_SQMUXA_2_I);
1560 
  II_ctrl_v_ssrstate_1_0_1HAKL3HAKR: LUT3
1561 
  generic map(
1562 
    INIT => X"35"
1563 
  )
1564 
  port map (
1565 
    I0 => SSRSTATE_1_0_D_AM(3),
1566 
    I1 => ssrstate_1_m1(3),
1567 
    I2 => ssrstate_2_sqmuxa_i,
1568 
    O => SSRSTATE_1_0_1(3));
1569 
  II_ctrl_v_ws_1_0_bm_L1: LUT3
1570 
  generic map(
1571 
    INIT => X"40"
1572 
  )
1573 
  port map (
1574 
    I0 => n_ahbsi_htrans(0),
1575 
    I1 => n_ahbsi_htrans(1),
1576 
    I2 => SSRSTATE_1_INT_21,
1577 
    O => WS_1_0_BM_L1);
1578 
  II_ctrl_v_ws_1_0_bm_L3: LUT2
1579 
  generic map(
1580 
    INIT => X"4"
1581 
  )
1582 
  port map (
1583 
    I0 => N_656_INT_66,
1584 
    I1 => rst,
1585 
    O => WS_1_0_BM_L3);
1586 
  II_ctrl_v_ws_1_0_bm_L5: LUT4
1587 
  generic map(
1588 
    INIT => X"0E00"
1589 
  )
1590 
  port map (
1591 
    I0 => SSRSTATE6_1_D_0_L1_INT_65,
1592 
    I1 => WS_1_0_BM_L1,
1593 
    I2 => UN1_AHBSI_INT_68,
1594 
    I3 => HSEL_5_INT_67,
1595 
    O => WS_1_0_BM_L5);
1596 
  II_ctrl_v_ws_1_0_bmHAKL1HAKR: LUT4
1597 
  generic map(
1598 
    INIT => X"80AA"
1599 
  )
1600 
  port map (
1601 
    I0 => WS_1_0_BM_L3,
1602 
    I1 => WS_1_0_BM_L5,
1603 
    I2 => HMBSEL_4_1_INT_14,
1604 
    I3 => SSRSTATE6_XX_MM_M3_INT_64,
1605 
    O => WS_1_0_BM(1));
1606 
  II_ctrl_v_N_619_i_L1_L1: LUT2
1607 
  generic map(
1608 
    INIT => X"4"
1609 
  )
1610 
  port map (
1611 
    I0 => CHANGE_1_SQMUXA_N_3_INT_63,
1612 
    I1 => SSRHREADY_2_SQMUXA_0_0_INT_62,
1613 
    O => N_619_I_L1_L1);
1614 
  II_ctrl_v_N_619_i_L1: LUT4
1615 
  generic map(
1616 
    INIT => X"80CC"
1617 
  )
1618 
  port map (
1619 
    I0 => N_619_I_L1_L1,
1620 
    I1 => n_ahbsi_hwrite,
1621 
    I2 => HMBSEL_4_1_INT_14,
1622 
    I3 => SSRSTATE6_XX_MM_M3_INT_64,
1623 
    O => N_619_I_L1);
1624 
  II_ctrl_v_hmbsel_4HAKL1HAKR: LUT3
1625 
  generic map(
1626 
    INIT => X"B8"
1627 
  )
1628 
  port map (
1629 
    I0 => HMBSEL_4_X1(1),
1630 
    I1 => n_ahbsi_htrans(1),
1631 
    I2 => HMBSEL_1_INT_34,
1632 
    O => HMBSEL_4_1_INT_14);
1633 
  II_v_ssrstate_6_sqmuxa: LUT4
1634 
  generic map(
1635 
    INIT => X"0035"
1636 
  )
1637 
  port map (
1638 
    I0 => g0_52_x0,
1639 
    I1 => g0_52_x1,
1640 
    I2 => n_ahbsi_htrans(1),
1641 
    I3 => SSRSTATE_6_SQMUXA_1,
1642 
    O => SSRSTATE_6_SQMUXA_INT_61);
1643 
  II_v_ssrstate_6_sqmuxa_1: LUT2
1644 
  generic map(
1645 
    INIT => X"7"
1646 
  )
1647 
  port map (
1648 
    I0 => n_ahbsi_htrans(0),
1649 
    I1 => SSRSTATE_2_INT_22,
1650 
    O => SSRSTATE_6_SQMUXA_1);
1651 
  II_ctrl_v_bwn_1_0_o3_0_L1: LUT2
1652 
  generic map(
1653 
    INIT => X"1"
1654 
  )
1655 
  port map (
1656 
    I0 => N_SRO_ADDRESS_0_INT_36,
1657 
    I1 => SIZE_0_INT_25,
1658 
    O => BWN_1_0_O3_0_L1);
1659 
  II_ctrl_v_bwn_1_0_o3_0_L3: LUT2
1660 
  generic map(
1661 
    INIT => X"1"
1662 
  )
1663 
  port map (
1664 
    I0 => n_ahbsi_haddr(0),
1665 
    I1 => n_ahbsi_hsize(0),
1666 
    O => BWN_1_0_O3_0_L3);
1667 
  II_ctrl_v_bwn_1_0_o3_0_L5: LUT4_L
1668 
  generic map(
1669 
    INIT => X"00E4"
1670 
  )
1671 
  port map (
1672 
    I0 => N_662_INT_60,
1673 
    I1 => BWN_1_0_O3_0_L1,
1674 
    I2 => BWN_1_0_O3_0_L3,
1675 
    I3 => hsize_1(1),
1676 
    LO => BWN_1_0_O3_0_L5);
1677 
  II_ctrl_v_bwn_1_0_o3_0HAKL1HAKR: LUT4
1678 
  generic map(
1679 
    INIT => X"5540"
1680 
  )
1681 
  port map (
1682 
    I0 => BWN_1_0_O3_0_L5,
1683 
    I1 => rst,
1684 
    I2 => PRSTATE_2_REP1_INT_59,
1685 
    I3 => bwn_0_sqmuxa_1,
1686 
    O => BWN_1_0_O3(1));
1687 
  II_r_prstate_2_rep1: FDR port map (
1688 
      Q => PRSTATE_2_REP1_INT_59,
1689 
      D => PRSTATEC_0_REP1,
1690 
      C => clk,
1691 
      R => RST_I);
1692 
  II_r_prstatec_0_rep1: LUT4_L
1693 
  generic map(
1694 
    INIT => X"A2A0"
1695 
  )
1696 
  port map (
1697 
    I0 => N_336,
1698 
    I1 => CHANGE_3,
1699 
    I2 => PRSTATE_0_INT_27,
1700 
    I3 => prstate_1_i_o4_s(2),
1701 
    LO => PRSTATEC_0_REP1);
1702 
  II_r_prstate_fastHAKL2HAKR: FDR port map (
1703 
      Q => PRSTATE_FAST_2_INT_13,
1704 
      D => PRSTATEC_0_FAST,
1705 
      C => clk,
1706 
      R => RST_I);
1707 
  II_r_prstatec_0_fast: LUT4_L
1708 
  generic map(
1709 
    INIT => X"A2A0"
1710 
  )
1711 
  port map (
1712 
    I0 => N_336,
1713 
    I1 => CHANGE_3,
1714 
    I2 => PRSTATE_0_INT_27,
1715 
    I3 => prstate_1_i_o4_s(2),
1716 
    LO => PRSTATEC_0_FAST);
1717 
  II_ctrl_v_ws_1_0_rnHAKL1HAKR: LUT4_L
1718 
  generic map(
1719 
    INIT => X"4EE4"
1720 
  )
1721 
  port map (
1722 
    I0 => g0_25,
1723 
    I1 => WS_1_2_0_D(1),
1724 
    I2 => WS_1_0_AM_1(1),
1725 
    I3 => WS_1_INT_17,
1726 
    LO => WS_1_0_RN_1(1));
1727 
  II_ctrl_v_bdrive_1_iv_m9_i_a4_0_2_2_L1: LUT4_L
1728 
  generic map(
1729 
    INIT => X"3100"
1730 
  )
1731 
  port map (
1732 
    I0 => BDRIVE_1_IV_M9_I_A4_0_2_1,
1733 
    I1 => BDRIVE_1_IV_M9_I_A4_0_2_2_1,
1734 
    I2 => SSRSTATE_1_INT_21,
1735 
    I3 => BDRIVE_0_SQMUXA_2_C,
1736 
    LO => BDRIVE_1_IV_M9_I_A4_0_2_2_L1);
1737 
  II_ctrl_v_bdrive_1_iv_m9_i_a4_0_2_2: LUT4
1738 
  generic map(
1739 
    INIT => X"D5F5"
1740 
  )
1741 
  port map (
1742 
    I0 => BDRIVE_1_IV_M9_I_A4_0_2_2_L1,
1743 
    I1 => UN1_AHBSI_INT_68,
1744 
    I2 => BDRIVE_1_IV_M9_I_A4_0_2_1,
1745 
    I3 => HSEL_5_INT_67,
1746 
    O => BDRIVE_1_TZ);
1747 
  II_ctrl_v_bdrive_1_iv_m9_i_a4_0_2_2_1_L1: LUT2
1748 
  generic map(
1749 
    INIT => X"1"
1750 
  )
1751 
  port map (
1752 
    I0 => SSRSTATE_0_INT_20,
1753 
    I1 => SSRSTATE_1_INT_21,
1754 
    O => BDRIVE_1_IV_M9_I_A4_0_2_2_1_L1);
1755 
  II_ctrl_v_bdrive_1_iv_m9_i_a4_0_2_2_1_L3: LUT4_L
1756 
  generic map(
1757 
    INIT => X"1015"
1758 
  )
1759 
  port map (
1760 
    I0 => N_SRO_BDRIVE_3_INT_15,
1761 
    I1 => D16MUXC_0_4_INT_73,
1762 
    I2 => PRSTATE_1_INT_28,
1763 
    I3 => PRSTATE_2_REP1_INT_59,
1764 
    LO => BDRIVE_1_IV_M9_I_A4_0_2_2_1_L3);
1765 
  II_ctrl_v_bdrive_1_iv_m9_i_a4_0_2_2_1: LUT4_L
1766 
  generic map(
1767 
    INIT => X"0F8F"
1768 
  )
1769 
  port map (
1770 
    I0 => N_668,
1771 
    I1 => BDRIVE_1_IV_M9_I_A4_0_2_2_1_L1,
1772 
    I2 => BDRIVE_1_IV_M9_I_A4_0_2_2_1_L3,
1773 
    I3 => BDRIVE_1_SQMUXA,
1774 
    LO => BDRIVE_1_IV_M9_I_A4_0_2_2_1);
1775 
  II_ctrl_v_romsn_1_iv_L1: LUT4_L
1776 
  generic map(
1777 
    INIT => X"27FF"
1778 
  )
1779 
  port map (
1780 
    I0 => N_662_INT_60,
1781 
    I1 => n_ahbsi_hmbsel(0),
1782 
    I2 => HMBSEL_0_INT_33,
1783 
    I3 => prstate_1_i_o4_s(2),
1784 
    LO => ROMSN_1_IV_L1);
1785 
  II_ctrl_v_iosn_9_iv_L1: LUT4_L
1786 
  generic map(
1787 
    INIT => X"27FF"
1788 
  )
1789 
  port map (
1790 
    I0 => N_662_INT_60,
1791 
    I1 => n_ahbsi_hmbsel(2),
1792 
    I2 => HMBSEL_2_INT_35,
1793 
    I3 => prstate_1_i_o4_s(2),
1794 
    LO => IOSN_9_IV_L1);
1795 
  II_ctrl_v_ssrstate6_xx_mm_m3_L1: LUT2
1796 
  generic map(
1797 
    INIT => X"7"
1798 
  )
1799 
  port map (
1800 
    I0 => HMBSEL_1_INT_34,
1801 
    I1 => HSEL_INT_58,
1802 
    O => SSRSTATE6_XX_MM_M3_L1);
1803 
  II_ctrl_v_ssrstate6_xx_mm_m3_L3: LUT4
1804 
  generic map(
1805 
    INIT => X"4FFF"
1806 
  )
1807 
  port map (
1808 
    I0 => n_ahbsi_hmbsel(1),
1809 
    I1 => n_ahbsi_hready,
1810 
    I2 => PRSTATE_5_INT_32,
1811 
    I3 => SSRSTATE_4_INT_24,
1812 
    O => SSRSTATE6_XX_MM_M3_L3);
1813 
  II_ctrl_v_ssrstate6_xx_mm_m3: LUT4
1814 
  generic map(
1815 
    INIT => X"CEFE"
1816 
  )
1817 
  port map (
1818 
    I0 => SSRSTATE6_XX_MM_M3_L1,
1819 
    I1 => SSRSTATE6_XX_MM_M3_L3,
1820 
    I2 => n_ahbsi_hready,
1821 
    I3 => hsel_4,
1822 
    O => SSRSTATE6_XX_MM_M3_INT_64);
1823 
  II_v_ws_2_sqmuxa_3_0: LUT4
1824 
  generic map(
1825 
    INIT => X"0700"
1826 
  )
1827 
  port map (
1828 
    I0 => g0_30,
1829 
    I1 => WS_0_SQMUXA_1_INT_57,
1830 
    I2 => WS_2_SQMUXA_3_0_SX,
1831 
    I3 => WS_2_SQMUXA_3_D_INT_56,
1832 
    O => N_371_INT_71);
1833 
  II_v_ws_2_sqmuxa_3_0_sx: LUT4_L
1834 
  generic map(
1835 
    INIT => X"CF4F"
1836 
  )
1837 
  port map (
1838 
    I0 => SSRSTATE_2_I_INT_55,
1839 
    I1 => WS_0_SQMUXA_1_INT_57,
1840 
    I2 => WS_2_SQMUXA_3_0_2_INT_54,
1841 
    I3 => WS_3_SQMUXA_1_INT_53,
1842 
    LO => WS_2_SQMUXA_3_0_SX);
1843 
  II_v_ws_2_sqmuxa_3_0_x: LUT3_L
1844 
  generic map(
1845 
    INIT => X"70"
1846 
  )
1847 
  port map (
1848 
    I0 => g0_30,
1849 
    I1 => WS_0_SQMUXA_1_INT_57,
1850 
    I2 => WS_2_SQMUXA_3_D_INT_56,
1851 
    LO => ws_2_sqmuxa_3_0_x);
1852 
  II_ctrl_v_hmbsel_4_x1HAKL1HAKR: LUT4_L
1853 
  generic map(
1854 
    INIT => X"BF80"
1855 
  )
1856 
  port map (
1857 
    I0 => n_ahbsi_hmbsel(1),
1858 
    I1 => n_ahbsi_hready,
1859 
    I2 => n_ahbsi_hsel(0),
1860 
    I3 => HMBSEL_1_INT_34,
1861 
    LO => HMBSEL_4_X1(1));
1862 
  II_un1_v_ssrstate17_2_0_m6_i_1: LUT4
1863 
  generic map(
1864 
    INIT => X"4F0F"
1865 
  )
1866 
  port map (
1867 
    I0 => n_ahbsi_hready,
1868 
    I1 => n_ahbsi_htrans(0),
1869 
    I2 => SSRSTATE_2_INT_22,
1870 
    I3 => SSRSTATE17_2_0_M6_I_A3_A0_1,
1871 
    O => ssrstate17_2_0_m6_i_1);
1872 
  II_ctrl_v_change_3_f1_d_0_L1: LUT4_L
1873 
  generic map(
1874 
    INIT => X"4440"
1875 
  )
1876 
  port map (
1877 
    I0 => UN1_AHBSI_INT_68,
1878 
    I1 => HSEL_5_INT_67,
1879 
    I2 => SSRSTATE_1_INT_21,
1880 
    I3 => SSRSTATE_2_INT_22,
1881 
    LO => CHANGE_3_F1_D_0_L1);
1882 
  II_ctrl_v_change_3_f1_d_0: LUT4
1883 
  generic map(
1884 
    INIT => X"00F2"
1885 
  )
1886 
  port map (
1887 
    I0 => CHANGE_3_F1_D_0_L1,
1888 
    I1 => HMBSEL_4_1_INT_14,
1889 
    I2 => CHANGE_INT_69,
1890 
    I3 => SSRSTATE_4_INT_24,
1891 
    O => CHANGE_3);
1892 
  II_ctrl_un1_v_ssrstate17: LUT4
1893 
  generic map(
1894 
    INIT => X"E000"
1895 
  )
1896 
  port map (
1897 
    I0 => n_ahbsi_htrans(0),
1898 
    I1 => n_ahbsi_htrans(1),
1899 
    I2 => HMBSEL_4_1_INT_14,
1900 
    I3 => HSEL_5_INT_67,
1901 
    O => N_654);
1902 
  II_un1_v_writen_2_sqmuxa_L1: LUT2
1903 
  generic map(
1904 
    INIT => X"1"
1905 
  )
1906 
  port map (
1907 
    I0 => PRSTATE_1_INT_28,
1908 
    I1 => PRSTATE_2_INT_29,
1909 
    O => WRITEN_2_SQMUXA_L1);
1910 
  II_un1_v_writen_2_sqmuxa_L3: LUT2
1911 
  generic map(
1912 
    INIT => X"4"
1913 
  )
1914 
  port map (
1915 
    I0 => n_ahbsi_htrans(0),
1916 
    I1 => n_ahbsi_htrans(1),
1917 
    O => WRITEN_2_SQMUXA_L3);
1918 
  II_un1_v_writen_2_sqmuxa_L5: LUT4
1919 
  generic map(
1920 
    INIT => X"7F00"
1921 
  )
1922 
  port map (
1923 
    I0 => WRITEN_2_SQMUXA_L3,
1924 
    I1 => HMBSEL_4_1_INT_14,
1925 
    I2 => HSEL_5_INT_67,
1926 
    I3 => SSRSTATE_2_INT_22,
1927 
    O => WRITEN_2_SQMUXA_L5);
1928 
  II_un1_v_writen_2_sqmuxa: LUT4
1929 
  generic map(
1930 
    INIT => X"7555"
1931 
  )
1932 
  port map (
1933 
    I0 => WRITEN_2_SQMUXA_L1,
1934 
    I1 => WRITEN_2_SQMUXA_L5,
1935 
    I2 => WRITEN_2_SQMUXA_TZ_0,
1936 
    I3 => BWN_1_SQMUXA_2_D_0,
1937 
    O => WRITEN_2_SQMUXA);
1938 
  II_ctrl_v_ws_1_L1_L1: LUT3_L
1939 
  generic map(
1940 
    INIT => X"37"
1941 
  )
1942 
  port map (
1943 
    I0 => g0_30,
1944 
    I1 => WS_0_SQMUXA_1_INT_57,
1945 
    I2 => WS_3_SQMUXA_1_INT_53,
1946 
    LO => WS_1_L1_L1);
1947 
  II_ctrl_v_ws_1_L1: LUT4_L
1948 
  generic map(
1949 
    INIT => X"B11B"
1950 
  )
1951 
  port map (
1952 
    I0 => g0_25,
1953 
    I1 => WS_1_2_0_D(2),
1954 
    I2 => WS_1_L1_L1,
1955 
    I3 => WS_2_INT_18,
1956 
    LO => WS_1_L1);
1957 
  II_v_ws_2_sqmuxa_3_0_2_L1: LUT4
1958 
  generic map(
1959 
    INIT => X"0013"
1960 
  )
1961 
  port map (
1962 
    I0 => N_SRO_ROMSN_0_INT_12,
1963 
    I1 => PRSTATE_1_INT_28,
1964 
    I2 => ws_2_sqmuxa_0,
1965 
    I3 => ws_4_sqmuxa_0,
1966 
    O => WS_2_SQMUXA_3_0_2_L1);
1967 
  II_v_ws_2_sqmuxa_3_0_2: LUT4
1968 
  generic map(
1969 
    INIT => X"003B"
1970 
  )
1971 
  port map (
1972 
    I0 => WS_2_SQMUXA_3_0_2_L1,
1973 
    I1 => rst,
1974 
    I2 => PRSTATE_3_INT_30,
1975 
    I3 => WS_1_SQMUXA_INT_52,
1976 
    O => WS_2_SQMUXA_3_0_2_INT_54);
1977 
  II_ctrl_v_ws_1_L1_0: LUT3
1978 
  generic map(
1979 
    INIT => X"57"
1980 
  )
1981 
  port map (
1982 
    I0 => g0_25,
1983 
    I1 => WS_0_INT_16,
1984 
    I2 => WS_1_INT_17,
1985 
    O => WS_1_L1_0);
1986 
  II_ctrl_v_ssrhready_8_f0_L5: LUT3_L
1987 
  generic map(
1988 
    INIT => X"2F"
1989 
  )
1990 
  port map (
1991 
    I0 => n_ahbsi_htrans(0),
1992 
    I1 => ssrstate17_1_xx_mm_N_4,
1993 
    I2 => SSRSTATE_1_INT_21,
1994 
    LO => ssrhready_8_f0_L5);
1995 
  II_ctrl_v_ssrhready_8_f0_L8: LUT4
1996 
  generic map(
1997 
    INIT => X"0013"
1998 
  )
1999 
  port map (
2000 
    I0 => D16MUXC_0_4_INT_73,
2001 
    I1 => SSRHREADY_INT_51,
2002 
    I2 => SSRSTATE_3_INT_23,
2003 
    I3 => ssrstate_1_sqmuxa_1,
2004 
    O => ssrhready_8_f0_L8);
2005 
  II_un1_v_hsel_1_0_L3: LUT2_L
2006 
  generic map(
2007 
    INIT => X"1"
2008 
  )
2009 
  port map (
2010 
    I0 => n_ahbsi_hmbsel(0),
2011 
    I1 => n_ahbsi_hmbsel(2),
2012 
    LO => hsel_1_0_L3);
2013 
  II_un1_v_ssrstate6_1_d_0_L1: LUT3
2014 
  generic map(
2015 
    INIT => X"40"
2016 
  )
2017 
  port map (
2018 
    I0 => n_ahbsi_htrans(0),
2019 
    I1 => n_ahbsi_htrans(1),
2020 
    I2 => SSRSTATE_2_INT_22,
2021 
    O => SSRSTATE6_1_D_0_L1_INT_65);
2022 
  II_v_ws_3_sqmuxa_0: LUT4
2023 
  generic map(
2024 
    INIT => X"8B03"
2025 
  )
2026 
  port map (
2027 
    I0 => n_ahbsi_hmbsel(1),
2028 
    I1 => n_ahbsi_hready,
2029 
    I2 => WS_3_SQMUXA_0_1,
2030 
    I3 => WS_3_SQMUXA_1_A0_2,
2031 
    O => WS_3_SQMUXA_1_INT_53);
2032 
  II_v_ws_3_sqmuxa_0_1: LUT3
2033 
  generic map(
2034 
    INIT => X"7F"
2035 
  )
2036 
  port map (
2037 
    I0 => d_m1_e_0_0,
2038 
    I1 => n_ahbsi_htrans(0),
2039 
    I2 => SSRSTATE_1_INT_21,
2040 
    O => WS_3_SQMUXA_0_1);
2041 
  II_un1_r_prstate_8: LUT4
2042 
  generic map(
2043 
    INIT => X"0301"
2044 
  )
2045 
  port map (
2046 
    I0 => N_SRO_ROMSN_0_INT_12,
2047 
    I1 => PRSTATE_0_INT_27,
2048 
    I2 => PRSTATE_5_INT_32,
2049 
    I3 => PRSTATE_8_1,
2050 
    O => N_656_INT_66);
2051 
  II_un1_r_prstate_8_1: LUT3_L
2052 
  generic map(
2053 
    INIT => X"57"
2054 
  )
2055 
  port map (
2056 
    I0 => N_SRO_IOSN_INT_70,
2057 
    I1 => PRSTATE_4_INT_31,
2058 
    I2 => PRSTATE_FAST_2_INT_13,
2059 
    LO => PRSTATE_8_1);
2060 
  II_v_mcfg1_bexcen_1_sqmuxa_i: LUT4
2061 
  generic map(
2062 
    INIT => X"B333"
2063 
  )
2064 
  port map (
2065 
    I0 => n_apbi_pwrite,
2066 
    I1 => rst,
2067 
    I2 => N_APBO_PRDATA_28_INT_11,
2068 
    I3 => BEXCEN_1_SQMUXA_I_1,
2069 
    O => BEXCEN_1_SQMUXA_I);
2070 
  II_v_mcfg1_bexcen_1_sqmuxa_i_1: LUT4
2071 
  generic map(
2072 
    INIT => X"1000"
2073 
  )
2074 
  port map (
2075 
    I0 => n_apbi_paddr(4),
2076 
    I1 => n_apbi_paddr(5),
2077 
    I2 => n_apbi_penable,
2078 
    I3 => n_apbi_psel(0),
2079 
    O => BEXCEN_1_SQMUXA_I_1);
2080 
  II_un1_v_ssrstate_1_sqmuxa_1_0_m3_0_1: LUT4
2081 
  generic map(
2082 
    INIT => X"0D08"
2083 
  )
2084 
  port map (
2085 
    I0 => n_ahbsi_hready,
2086 
    I1 => n_ahbsi_hsel(0),
2087 
    I2 => n_ahbsi_htrans(0),
2088 
    I3 => HSEL_INT_58,
2089 
    O => ssrstate_1_sqmuxa_1_0_m3_0_1);
2090 
  II_un1_r_prstate: LUT4
2091 
  generic map(
2092 
    INIT => X"1911"
2093 
  )
2094 
  port map (
2095 
    I0 => PRSTATE_5_INT_32,
2096 
    I1 => PRSTATE_1,
2097 
    I2 => PRSTATE_12_M7_I_A6_0,
2098 
    I3 => hsel_1(0),
2099 
    O => PRSTATE_12_I);
2100 
  II_un1_r_prstate_1_0: LUT4
2101 
  generic map(
2102 
    INIT => X"0343"
2103 
  )
2104 
  port map (
2105 
    I0 => HWRITE_1,
2106 
    I1 => PRSTATE_5_INT_32,
2107 
    I2 => PRSTATE_12_0,
2108 
    I3 => PRSTATE_12_M7_I_A6,
2109 
    O => PRSTATE_1);
2110 
  II_ctrl_v_ws_1_0_am_1HAKL1HAKR: LUT4_L
2111 
  generic map(
2112 
    INIT => X"0515"
2113 
  )
2114 
  port map (
2115 
    I0 => WS_0_INT_16,
2116 
    I1 => g0_30,
2117 
    I2 => WS_0_SQMUXA_1_INT_57,
2118 
    I3 => WS_3_SQMUXA_1_INT_53,
2119 
    LO => WS_1_0_AM_1(1));
2120 
  II_r_d16muxc_0_1_0: LUT4
2121 
  generic map(
2122 
    INIT => X"0110"
2123 
  )
2124 
  port map (
2125 
    I0 => PRSTATE_1_INT_28,
2126 
    I1 => PRSTATE_4_INT_31,
2127 
    I2 => SIZE_0_INT_25,
2128 
    I3 => SIZE_1_INT_26,
2129 
    O => D16MUXC_0_1_0);
2130 
  II_r_acount_lm_0_1HAKL0HAKR: LUT3
2131 
  generic map(
2132 
    INIT => X"27"
2133 
  )
2134 
  port map (
2135 
    I0 => N_662_INT_60,
2136 
    I1 => n_ahbsi_haddr(2),
2137 
    I2 => HADDR(2),
2138 
    O => ACOUNT_LM_0_1(0));
2139 
  II_v_N_635_i_1: LUT3_L
2140 
  generic map(
2141 
    INIT => X"0D"
2142 
  )
2143 
  port map (
2144 
    I0 => SSRSTATE_1_INT_21,
2145 
    I1 => loadcount_1_sqmuxa,
2146 
    I2 => ssrstate_1_sqmuxa_1,
2147 
    LO => N_635_I_1);
2148 
  II_ctrl_v_oen_1_iv: LUT3_L
2149 
  generic map(
2150 
    INIT => X"E2"
2151 
  )
2152 
  port map (
2153 
    I0 => SSRSTATE6_XX_MM_M3_INT_64,
2154 
    I1 => PRSTATE_12_I,
2155 
    I2 => PRSTATE_1_SQMUXA,
2156 
    LO => OEN_1);
2157 
  II_ctrl_v_N_617_i: LUT4_L
2158 
  generic map(
2159 
    INIT => X"0FBF"
2160 
  )
2161 
  port map (
2162 
    I0 => N_646,
2163 
    I1 => n_ahbsi_hwrite,
2164 
    I2 => BWN_1_0_0(3),
2165 
    I3 => bwn_1_sqmuxa_2_d_0_2,
2166 
    LO => N_617_I);
2167 
  II_ctrl_v_hwdataout_1_0HAKL0HAKR: LUT4_L
2168 
  generic map(
2169 
    INIT => X"E2F0"
2170 
  )
2171 
  port map (
2172 
    I0 => n_ahbsi_hwdata(0),
2173 
    I1 => BUS16EN_INT_72,
2174 
    I2 => HWDATA(0),
2175 
    I3 => PRSTATE_2_INT_29,
2176 
    LO => HWDATAOUT_1(0));
2177 
  II_ctrl_v_hwdataout_1_0HAKL1HAKR: LUT4_L
2178 
  generic map(
2179 
    INIT => X"E2F0"
2180 
  )
2181 
  port map (
2182 
    I0 => n_ahbsi_hwdata(1),
2183 
    I1 => BUS16EN_INT_72,
2184 
    I2 => HWDATA(1),
2185 
    I3 => PRSTATE_2_INT_29,
2186 
    LO => HWDATAOUT_1(1));
2187 
  II_ctrl_v_hwdataout_1_0HAKL2HAKR: LUT4_L
2188 
  generic map(
2189 
    INIT => X"E2F0"
2190 
  )
2191 
  port map (
2192 
    I0 => n_ahbsi_hwdata(2),
2193 
    I1 => BUS16EN_INT_72,
2194 
    I2 => HWDATA(2),
2195 
    I3 => PRSTATE_2_INT_29,
2196 
    LO => HWDATAOUT_1(2));
2197 
  II_ctrl_v_hwdataout_1_0HAKL3HAKR: LUT4_L
2198 
  generic map(
2199 
    INIT => X"E2F0"
2200 
  )
2201 
  port map (
2202 
    I0 => n_ahbsi_hwdata(3),
2203 
    I1 => BUS16EN_INT_72,
2204 
    I2 => HWDATA(3),
2205 
    I3 => PRSTATE_2_INT_29,
2206 
    LO => HWDATAOUT_1(3));
2207 
  II_ctrl_v_hwdataout_1_0HAKL4HAKR: LUT4_L
2208 
  generic map(
2209 
    INIT => X"E2F0"
2210 
  )
2211 
  port map (
2212 
    I0 => n_ahbsi_hwdata(4),
2213 
    I1 => BUS16EN_INT_72,
2214 
    I2 => HWDATA(4),
2215 
    I3 => PRSTATE_2_INT_29,
2216 
    LO => HWDATAOUT_1(4));
2217 
  II_ctrl_v_hwdataout_1_0HAKL5HAKR: LUT4_L
2218 
  generic map(
2219 
    INIT => X"E2F0"
2220 
  )
2221 
  port map (
2222 
    I0 => n_ahbsi_hwdata(5),
2223 
    I1 => BUS16EN_INT_72,
2224 
    I2 => HWDATA(5),
2225 
    I3 => PRSTATE_2_INT_29,
2226 
    LO => HWDATAOUT_1(5));
2227 
  II_ctrl_v_hwdataout_1_0HAKL6HAKR: LUT4_L
2228 
  generic map(
2229 
    INIT => X"E2F0"
2230 
  )
2231 
  port map (
2232 
    I0 => n_ahbsi_hwdata(6),
2233 
    I1 => BUS16EN_INT_72,
2234 
    I2 => HWDATA(6),
2235 
    I3 => PRSTATE_2_INT_29,
2236 
    LO => HWDATAOUT_1(6));
2237 
  II_ctrl_v_hwdataout_1_0HAKL7HAKR: LUT4_L
2238 
  generic map(
2239 
    INIT => X"E2F0"
2240 
  )
2241 
  port map (
2242 
    I0 => n_ahbsi_hwdata(7),
2243 
    I1 => BUS16EN_INT_72,
2244 
    I2 => HWDATA(7),
2245 
    I3 => PRSTATE_2_INT_29,
2246 
    LO => HWDATAOUT_1(7));
2247 
  II_ctrl_v_hwdataout_1_0HAKL8HAKR: LUT4_L
2248 
  generic map(
2249 
    INIT => X"E2F0"
2250 
  )
2251 
  port map (
2252 
    I0 => n_ahbsi_hwdata(8),
2253 
    I1 => BUS16EN_INT_72,
2254 
    I2 => HWDATA(8),
2255 
    I3 => PRSTATE_2_INT_29,
2256 
    LO => HWDATAOUT_1(8));
2257 
  II_ctrl_v_hwdataout_1_0HAKL9HAKR: LUT4_L
2258 
  generic map(
2259 
    INIT => X"E2F0"
2260 
  )
2261 
  port map (
2262 
    I0 => n_ahbsi_hwdata(9),
2263 
    I1 => BUS16EN_INT_72,
2264 
    I2 => HWDATA(9),
2265 
    I3 => PRSTATE_2_INT_29,
2266 
    LO => HWDATAOUT_1(9));
2267 
  II_ctrl_v_hwdataout_1_0HAKL10HAKR: LUT4_L
2268 
  generic map(
2269 
    INIT => X"E2F0"
2270 
  )
2271 
  port map (
2272 
    I0 => n_ahbsi_hwdata(10),
2273 
    I1 => BUS16EN_INT_72,
2274 
    I2 => HWDATA(10),
2275 
    I3 => PRSTATE_2_INT_29,
2276 
    LO => HWDATAOUT_1(10));
2277 
  II_ctrl_v_hwdataout_1_0HAKL11HAKR: LUT4_L
2278 
  generic map(
2279 
    INIT => X"E2F0"
2280 
  )
2281 
  port map (
2282 
    I0 => n_ahbsi_hwdata(11),
2283 
    I1 => BUS16EN_INT_72,
2284 
    I2 => HWDATA(11),
2285 
    I3 => PRSTATE_2_INT_29,
2286 
    LO => HWDATAOUT_1(11));
2287 
  II_ctrl_v_hwdataout_1_0HAKL12HAKR: LUT4_L
2288 
  generic map(
2289 
    INIT => X"E2F0"
2290 
  )
2291 
  port map (
2292 
    I0 => n_ahbsi_hwdata(12),
2293 
    I1 => BUS16EN_INT_72,
2294 
    I2 => HWDATA(12),
2295 
    I3 => PRSTATE_2_INT_29,
2296 
    LO => HWDATAOUT_1(12));
2297 
  II_ctrl_v_hwdataout_1_0HAKL13HAKR: LUT4_L
2298 
  generic map(
2299 
    INIT => X"E2F0"
2300 
  )
2301 
  port map (
2302 
    I0 => n_ahbsi_hwdata(13),
2303 
    I1 => BUS16EN_INT_72,
2304 
    I2 => HWDATA(13),
2305 
    I3 => PRSTATE_2_INT_29,
2306 
    LO => HWDATAOUT_1(13));
2307 
  II_ctrl_v_hwdataout_1_0HAKL14HAKR: LUT4_L
2308 
  generic map(
2309 
    INIT => X"E2F0"
2310 
  )
2311 
  port map (
2312 
    I0 => n_ahbsi_hwdata(14),
2313 
    I1 => BUS16EN_INT_72,
2314 
    I2 => HWDATA(14),
2315 
    I3 => PRSTATE_2_INT_29,
2316 
    LO => HWDATAOUT_1(14));
2317 
  II_ctrl_v_hwdataout_1_0HAKL15HAKR: LUT4_L
2318 
  generic map(
2319 
    INIT => X"E2F0"
2320 
  )
2321 
  port map (
2322 
    I0 => n_ahbsi_hwdata(15),
2323 
    I1 => BUS16EN_INT_72,
2324 
    I2 => HWDATA(15),
2325 
    I3 => PRSTATE_2_INT_29,
2326 
    LO => HWDATAOUT_1(15));
2327 
  II_ctrl_v_hwdataout_1_0HAKL16HAKR: LUT3_L
2328 
  generic map(
2329 
    INIT => X"AC"
2330 
  )
2331 
  port map (
2332 
    I0 => N_382,
2333 
    I1 => HWDATA(16),
2334 
    I2 => PRSTATE_2_INT_29,
2335 
    LO => HWDATAOUT_1(16));
2336 
  II_ctrl_v_hwdataout_1_0HAKL17HAKR: LUT3_L
2337 
  generic map(
2338 
    INIT => X"AC"
2339 
  )
2340 
  port map (
2341 
    I0 => N_383,
2342 
    I1 => HWDATA(17),
2343 
    I2 => PRSTATE_2_INT_29,
2344 
    LO => HWDATAOUT_1(17));
2345 
  II_ctrl_v_hwdataout_1_0HAKL18HAKR: LUT3_L
2346 
  generic map(
2347 
    INIT => X"AC"
2348 
  )
2349 
  port map (
2350 
    I0 => N_384,
2351 
    I1 => HWDATA(18),
2352 
    I2 => PRSTATE_2_INT_29,
2353 
    LO => HWDATAOUT_1(18));
2354 
  II_ctrl_v_hwdataout_1_0HAKL19HAKR: LUT3_L
2355 
  generic map(
2356 
    INIT => X"AC"
2357 
  )
2358 
  port map (
2359 
    I0 => N_385,
2360 
    I1 => HWDATA(19),
2361 
    I2 => PRSTATE_2_INT_29,
2362 
    LO => HWDATAOUT_1(19));
2363 
  II_ctrl_v_hwdataout_1_0HAKL20HAKR: LUT3_L
2364 
  generic map(
2365 
    INIT => X"AC"
2366 
  )
2367 
  port map (
2368 
    I0 => N_386,
2369 
    I1 => HWDATA(20),
2370 
    I2 => PRSTATE_2_INT_29,
2371 
    LO => HWDATAOUT_1(20));
2372 
  II_ctrl_v_hwdataout_1_0HAKL21HAKR: LUT3_L
2373 
  generic map(
2374 
    INIT => X"AC"
2375 
  )
2376 
  port map (
2377 
    I0 => N_387,
2378 
    I1 => HWDATA(21),
2379 
    I2 => PRSTATE_2_INT_29,
2380 
    LO => HWDATAOUT_1(21));
2381 
  II_ctrl_v_hwdataout_1_0HAKL22HAKR: LUT3_L
2382 
  generic map(
2383 
    INIT => X"AC"
2384 
  )
2385 
  port map (
2386 
    I0 => N_388,
2387 
    I1 => HWDATA(22),
2388 
    I2 => PRSTATE_2_INT_29,
2389 
    LO => HWDATAOUT_1(22));
2390 
  II_ctrl_v_hwdataout_1_0HAKL23HAKR: LUT3_L
2391 
  generic map(
2392 
    INIT => X"AC"
2393 
  )
2394 
  port map (
2395 
    I0 => N_389,
2396 
    I1 => HWDATA(23),
2397 
    I2 => PRSTATE_2_INT_29,
2398 
    LO => HWDATAOUT_1(23));
2399 
  II_ctrl_v_hwdataout_1_0HAKL24HAKR: LUT3_L
2400 
  generic map(
2401 
    INIT => X"AC"
2402 
  )
2403 
  port map (
2404 
    I0 => N_390,
2405 
    I1 => HWDATA(24),
2406 
    I2 => PRSTATE_2_INT_29,
2407 
    LO => HWDATAOUT_1(24));
2408 
  II_ctrl_v_hwdataout_1_0HAKL25HAKR: LUT3_L
2409 
  generic map(
2410 
    INIT => X"AC"
2411 
  )
2412 
  port map (
2413 
    I0 => N_391,
2414 
    I1 => HWDATA(25),
2415 
    I2 => PRSTATE_2_INT_29,
2416 
    LO => HWDATAOUT_1(25));
2417 
  II_ctrl_v_hwdataout_1_0HAKL26HAKR: LUT3_L
2418 
  generic map(
2419 
    INIT => X"AC"
2420 
  )
2421 
  port map (
2422 
    I0 => N_392,
2423 
    I1 => HWDATA(26),
2424 
    I2 => PRSTATE_2_INT_29,
2425 
    LO => HWDATAOUT_1(26));
2426 
  II_ctrl_v_hwdataout_1_0HAKL27HAKR: LUT3_L
2427 
  generic map(
2428 
    INIT => X"AC"
2429 
  )
2430 
  port map (
2431 
    I0 => N_393,
2432 
    I1 => HWDATA(27),
2433 
    I2 => PRSTATE_2_INT_29,
2434 
    LO => HWDATAOUT_1(27));
2435 
  II_ctrl_v_hwdataout_1_0HAKL28HAKR: LUT3_L
2436 
  generic map(
2437 
    INIT => X"AC"
2438 
  )
2439 
  port map (
2440 
    I0 => N_394,
2441 
    I1 => HWDATA(28),
2442 
    I2 => PRSTATE_2_INT_29,
2443 
    LO => HWDATAOUT_1(28));
2444 
  II_ctrl_v_hwdataout_1_0HAKL29HAKR: LUT3_L
2445 
  generic map(
2446 
    INIT => X"AC"
2447 
  )
2448 
  port map (
2449 
    I0 => N_395,
2450 
    I1 => HWDATA(29),
2451 
    I2 => PRSTATE_2_INT_29,
2452 
    LO => HWDATAOUT_1(29));
2453 
  II_ctrl_v_hwdataout_1_0HAKL30HAKR: LUT3_L
2454 
  generic map(
2455 
    INIT => X"AC"
2456 
  )
2457 
  port map (
2458 
    I0 => N_396,
2459 
    I1 => HWDATA(30),
2460 
    I2 => PRSTATE_2_INT_29,
2461 
    LO => HWDATAOUT_1(30));
2462 
  II_ctrl_v_hwdataout_1_0HAKL31HAKR: LUT3_L
2463 
  generic map(
2464 
    INIT => X"AC"
2465 
  )
2466 
  port map (
2467 
    I0 => N_397,
2468 
    I1 => HWDATA(31),
2469 
    I2 => PRSTATE_2_INT_29,
2470 
    LO => HWDATAOUT_1(31));
2471 
  II_ctrl_v_mcfg1_N_626_i: LUT2_L
2472 
  generic map(
2473 
    INIT => X"B"
2474 
  )
2475 
  port map (
2476 
    I0 => n_apbi_pwdata_4,
2477 
    I1 => rst,
2478 
    LO => N_626_I);
2479 
  II_ctrl_v_mcfg1_N_625_i: LUT2_L
2480 
  generic map(
2481 
    INIT => X"B"
2482 
  )
2483 
  port map (
2484 
    I0 => n_apbi_pwdata_5,
2485 
    I1 => rst,
2486 
    LO => N_625_I);
2487 
  II_ctrl_v_mcfg1_N_624_i: LUT2_L
2488 
  generic map(
2489 
    INIT => X"B"
2490 
  )
2491 
  port map (
2492 
    I0 => n_apbi_pwdata_6,
2493 
    I1 => rst,
2494 
    LO => N_624_I);
2495 
  II_ctrl_v_mcfg1_N_623_i: LUT2_L
2496 
  generic map(
2497 
    INIT => X"B"
2498 
  )
2499 
  port map (
2500 
    I0 => n_apbi_pwdata_7,
2501 
    I1 => rst,
2502 
    LO => N_623_I);
2503 
  II_ctrl_v_mcfg1_N_630_i: LUT2_L
2504 
  generic map(
2505 
    INIT => X"B"
2506 
  )
2507 
  port map (
2508 
    I0 => n_apbi_pwdata_0,
2509 
    I1 => rst,
2510 
    LO => N_630_I);
2511 
  II_ctrl_v_mcfg1_N_629_i: LUT2_L
2512 
  generic map(
2513 
    INIT => X"B"
2514 
  )
2515 
  port map (
2516 
    I0 => n_apbi_pwdata_1,
2517 
    I1 => rst,
2518 
    LO => N_629_I);
2519 
  II_ctrl_v_mcfg1_N_628_i: LUT2_L
2520 
  generic map(
2521 
    INIT => X"B"
2522 
  )
2523 
  port map (
2524 
    I0 => n_apbi_pwdata_2,
2525 
    I1 => rst,
2526 
    LO => N_628_I);
2527 
  II_ctrl_v_mcfg1_N_627_i: LUT2_L
2528 
  generic map(
2529 
    INIT => X"B"
2530 
  )
2531 
  port map (
2532 
    I0 => n_apbi_pwdata_3,
2533 
    I1 => rst,
2534 
    LO => N_627_I);
2535 
  II_ctrl_v_mcfg1_iows_1HAKL0HAKR: LUT2_L
2536 
  generic map(
2537 
    INIT => X"8"
2538 
  )
2539 
  port map (
2540 
    I0 => n_apbi_pwdata_20,
2541 
    I1 => rst,
2542 
    LO => IOWS_1(0));
2543 
  II_ctrl_v_mcfg1_iows_1HAKL1HAKR: LUT2_L
2544 
  generic map(
2545 
    INIT => X"8"
2546 
  )
2547 
  port map (
2548 
    I0 => n_apbi_pwdata_21,
2549 
    I1 => rst,
2550 
    LO => IOWS_1(1));
2551 
  II_ctrl_v_mcfg1_iows_1HAKL2HAKR: LUT2_L
2552 
  generic map(
2553 
    INIT => X"8"
2554 
  )
2555 
  port map (
2556 
    I0 => n_apbi_pwdata_22,
2557 
    I1 => rst,
2558 
    LO => IOWS_1(2));
2559 
  II_ctrl_v_mcfg1_iows_1HAKL3HAKR: LUT2_L
2560 
  generic map(
2561 
    INIT => X"8"
2562 
  )
2563 
  port map (
2564 
    I0 => n_apbi_pwdata_23,
2565 
    I1 => rst,
2566 
    LO => IOWS_1(3));
2567 
  II_ctrl_v_mcfg1_romwidth_1_0HAKL0HAKR: LUT3_L
2568 
  generic map(
2569 
    INIT => X"AC"
2570 
  )
2571 
  port map (
2572 
    I0 => n_apbi_pwdata_8,
2573 
    I1 => n_sri_bwidth(0),
2574 
    I2 => rst,
2575 
    LO => ROMWIDTH_1(0));
2576 
  II_ctrl_v_mcfg1_romwidth_1_0HAKL1HAKR: LUT3_L
2577 
  generic map(
2578 
    INIT => X"AC"
2579 
  )
2580 
  port map (
2581 
    I0 => n_apbi_pwdata_9,
2582 
    I1 => n_sri_bwidth(1),
2583 
    I2 => rst,
2584 
    LO => ROMWIDTH_1(1));
2585 
  II_ctrl_v_mcfg1_romwrite_1: LUT2_L
2586 
  generic map(
2587 
    INIT => X"8"
2588 
  )
2589 
  port map (
2590 
    I0 => n_apbi_pwdata_11,
2591 
    I1 => rst,
2592 
    LO => ROMWRITE_1);
2593 
  II_ctrl_v_mcfg1_ioen_1: LUT2_L
2594 
  generic map(
2595 
    INIT => X"8"
2596 
  )
2597 
  port map (
2598 
    I0 => n_apbi_pwdata_19,
2599 
    I1 => rst,
2600 
    LO => IOEN_1);
2601 
  II_ctrl_v_ssrstate_1_0HAKL2HAKR: LUT4_L
2602 
  generic map(
2603 
    INIT => X"8A80"
2604 
  )
2605 
  port map (
2606 
    I0 => rst,
2607 
    I1 => D16MUXC_0_4_INT_73,
2608 
    I2 => SSRSTATE_3_INT_23,
2609 
    I3 => SSRSTATE_6_SQMUXA_INT_61,
2610 
    LO => SSRSTATE_1(2));
2611 
  II_ctrl_v_bdrive_1_iv_m9_i: LUT4_L
2612 
  generic map(
2613 
    INIT => X"1000"
2614 
  )
2615 
  port map (
2616 
    I0 => BDRIVE_1_IV_0_A0,
2617 
    I1 => BDRIVE_1_IV_0_A1,
2618 
    I2 => BDRIVE_1_IV_M9_I_0_0,
2619 
    I3 => BDRIVE_1_TZ,
2620 
    LO => BDRIVE_1);
2621 
  II_r_acount_lm_0HAKL1HAKR: LUT3_L
2622 
  generic map(
2623 
    INIT => X"D8"
2624 
  )
2625 
  port map (
2626 
    I0 => loadcount_7,
2627 
    I1 => NN_1,
2628 
    I2 => ACOUNT_S(1),
2629 
    LO => ACOUNT_LM(1));
2630 
  II_r_acount_lm_0HAKL2HAKR: LUT3_L
2631 
  generic map(
2632 
    INIT => X"D8"
2633 
  )
2634 
  port map (
2635 
    I0 => loadcount_7,
2636 
    I1 => NN_2,
2637 
    I2 => ACOUNT_S(2),
2638 
    LO => ACOUNT_LM(2));
2639 
  II_r_acount_lm_0HAKL3HAKR: LUT3_L
2640 
  generic map(
2641 
    INIT => X"D8"
2642 
  )
2643 
  port map (
2644 
    I0 => loadcount_7,
2645 
    I1 => NN_3,
2646 
    I2 => ACOUNT_S(3),
2647 
    LO => ACOUNT_LM(3));
2648 
  II_r_acount_lm_0HAKL4HAKR: LUT3_L
2649 
  generic map(
2650 
    INIT => X"D8"
2651 
  )
2652 
  port map (
2653 
    I0 => loadcount_7,
2654 
    I1 => NN_4,
2655 
    I2 => ACOUNT_S(4),
2656 
    LO => ACOUNT_LM(4));
2657 
  II_r_acount_lm_0HAKL5HAKR: LUT3_L
2658 
  generic map(
2659 
    INIT => X"D8"
2660 
  )
2661 
  port map (
2662 
    I0 => loadcount_7,
2663 
    I1 => NN_5,
2664 
    I2 => ACOUNT_S(5),
2665 
    LO => ACOUNT_LM(5));
2666 
  II_r_acount_lm_0HAKL6HAKR: LUT3_L
2667 
  generic map(
2668 
    INIT => X"D8"
2669 
  )
2670 
  port map (
2671 
    I0 => loadcount_7,
2672 
    I1 => NN_6,
2673 
    I2 => ACOUNT_S(6),
2674 
    LO => ACOUNT_LM(6));
2675 
  II_r_acount_lm_0HAKL7HAKR: LUT3_L
2676 
  generic map(
2677 
    INIT => X"D8"
2678 
  )
2679 
  port map (
2680 
    I0 => loadcount_7,
2681 
    I1 => NN_7,
2682 
    I2 => ACOUNT_S(7),
2683 
    LO => ACOUNT_LM(7));
2684 
  II_r_acount_lm_0HAKL8HAKR: LUT3_L
2685 
  generic map(
2686 
    INIT => X"D8"
2687 
  )
2688 
  port map (
2689 
    I0 => loadcount_7,
2690 
    I1 => NN_8,
2691 
    I2 => ACOUNT_S(8),
2692 
    LO => ACOUNT_LM(8));
2693 
  II_r_acount_lm_0HAKL9HAKR: LUT3_L
2694 
  generic map(
2695 
    INIT => X"D8"
2696 
  )
2697 
  port map (
2698 
    I0 => loadcount_7,
2699 
    I1 => NN_9,
2700 
    I2 => ACOUNT_S(9),
2701 
    LO => ACOUNT_LM(9));
2702 
  II_r_d16muxc: LUT3_L
2703 
  generic map(
2704 
    INIT => X"40"
2705 
  )
2706 
  port map (
2707 
    I0 => un7_bus16en,
2708 
    I1 => D16MUXC_1,
2709 
    I2 => D16MUXC_2,
2710 
    LO => D16MUXC);
2711 
  II_rbdrivec_18: LUT4_L
2712 
  generic map(
2713 
    INIT => X"4000"
2714 
  )
2715 
  port map (
2716 
    I0 => BDRIVE_1_IV_0_A0,
2717 
    I1 => BDRIVE_1_IV_0_1,
2718 
    I2 => BDRIVE_1_IV_M9_I_0,
2719 
    I3 => BDRIVE_1_TZ,
2720 
    LO => RBDRIVEC_18);
2721 
  II_r_ssrstatec_0: LUT4_L
2722 
  generic map(
2723 
    INIT => X"0B08"
2724 
  )
2725 
  port map (
2726 
    I0 => NoName_cnst(0),
2727 
    I1 => SSRSTATE_5_I,
2728 
    I2 => ssrstate_2_sqmuxa_1,
2729 
    I3 => SSRSTATE_11(0),
2730 
    LO => SSRSTATEC_0);
2731 
  II_r_prstatec_1: LUT4_L
2732 
  generic map(
2733 
    INIT => X"0008"
2734 
  )
2735 
  port map (
2736 
    I0 => SSRSTATE23_1,
2737 
    I1 => PRSTATE_1_INT_28,
2738 
    I2 => WS_0_INT_16,
2739 
    I3 => WS_3_INT_19,
2740 
    LO => PRSTATEC_1);
2741 
  II_v_N_337_i: LUT3_L
2742 
  generic map(
2743 
    INIT => X"74"
2744 
  )
2745 
  port map (
2746 
    I0 => D16MUXC_0_4_INT_73,
2747 
    I1 => PRSTATE_1_INT_28,
2748 
    I2 => PRSTATE_2_INT_29,
2749 
    LO => N_337_I);
2750 
  II_r_prstatec_0: LUT4_L
2751 
  generic map(
2752 
    INIT => X"A2A0"
2753 
  )
2754 
  port map (
2755 
    I0 => N_336,
2756 
    I1 => CHANGE_3,
2757 
    I2 => PRSTATE_0_INT_27,
2758 
    I3 => prstate_1_i_o4_s(2),
2759 
    LO => PRSTATEC_0);
2760 
  II_r_prstatec: LUT3_L
2761 
  generic map(
2762 
    INIT => X"0E"
2763 
  )
2764 
  port map (
2765 
    I0 => PRSTATE_3_INT_30,
2766 
    I1 => PRSTATE_4_INT_31,
2767 
    I2 => d16mux_0_sqmuxa,
2768 
    LO => PRSTATEC);
2769 
  II_v_prstate_1_0_a3_0HAKL4HAKR: LUT4_L
2770 
  generic map(
2771 
    INIT => X"0200"
2772 
  )
2773 
  port map (
2774 
    I0 => rst,
2775 
    I1 => HWRITE_1,
2776 
    I2 => CHANGE_3,
2777 
    I3 => prstate_1_i_o4_s(2),
2778 
    LO => N_342);
2779 
  II_r_prstates_i: LUT4_L
2780 
  generic map(
2781 
    INIT => X"8FCF"
2782 
  )
2783 
  port map (
2784 
    I0 => CHANGE_3,
2785 
    I1 => PRSTATE_5_INT_32,
2786 
    I2 => PRSTATESR_0,
2787 
    I3 => hsel_1(0),
2788 
    LO => PRSTATES_I);
2789 
  II_r_acount_qxuHAKL9HAKR: LUT1
2790 
  generic map(
2791 
    INIT => X"2"
2792 
  )
2793 
  port map (
2794 
    I0 => N_SRO_ADDRESS_11_INT_47,
2795 
    O => ACOUNT_QXU(9));
2796 
  II_un1_v_ssrstate23_u_0HAKL4HAKR: MUXF5 port map (
2797 
      I0 => SSRSTATE23_U_0_AM(4),
2798 
      I1 => SSRSTATE23_U_0_BM(4),
2799 
      S => SSRSTATE_5_I,
2800 
      O => ssrstate_1_m1(4));
2801 
  II_v_bwn_1_sqmuxa_3_i: LUT4
2802 
  generic map(
2803 
    INIT => X"D555"
2804 
  )
2805 
  port map (
2806 
    I0 => bwn_0_sqmuxa_1,
2807 
    I1 => BWN_1_SQMUXA_2_D_0,
2808 
    I2 => WRITEN_0_SQMUXA_0_2,
2809 
    I3 => WRITEN_0_SQMUXA_D,
2810 
    O => BWN_1_SQMUXA_3_I);
2811 
  II_rbdrivec_19: LUT4
2812 
  generic map(
2813 
    INIT => X"4000"
2814 
  )
2815 
  port map (
2816 
    I0 => BDRIVE_1_IV_0_A0,
2817 
    I1 => BDRIVE_1_IV_0_1,
2818 
    I2 => BDRIVE_1_IV_M9_I_0,
2819 
    I3 => BDRIVE_1_TZ,
2820 
    O => RBDRIVEC);
2821 
  II_ctrl_v_ssrstate_1_m2s2_0: LUT4_L
2822 
  generic map(
2823 
    INIT => X"0010"
2824 
  )
2825 
  port map (
2826 
    I0 => NoName_cnst(0),
2827 
    I1 => SSRSTATE_1_INT_21,
2828 
    I2 => change_1_sqmuxa_0,
2829 
    I3 => SSRSTATE_6_SQMUXA_INT_61,
2830 
    LO => SSRSTATE_1_M2S2_0);
2831 
  II_ctrl_v_bwn_1_0_0HAKL3HAKR: LUT3
2832 
  generic map(
2833 
    INIT => X"C8"
2834 
  )
2835 
  port map (
2836 
    I0 => hsize_1(1),
2837 
    I1 => BWN_1_0_O3(1),
2838 
    I2 => haddr_0,
2839 
    O => BWN_1_0_0(3));
2840 
  II_v_ws_2_sqmuxa_3_0_4: LUT4
2841 
  generic map(
2842 
    INIT => X"30B0"
2843 
  )
2844 
  port map (
2845 
    I0 => SSRSTATE_2_I_INT_55,
2846 
    I1 => WS_0_SQMUXA_1_INT_57,
2847 
    I2 => WS_2_SQMUXA_3_0_2_INT_54,
2848 
    I3 => WS_3_SQMUXA_1_INT_53,
2849 
    O => ws_2_sqmuxa_3_0_4);
2850 
  II_un1_v_N_599_i: LUT4
2851 
  generic map(
2852 
    INIT => X"FF8F"
2853 
  )
2854 
  port map (
2855 
    I0 => D16MUXC_0_4_INT_73,
2856 
    I1 => PRSTATE_1_INT_28,
2857 
    I2 => HADDR_0_SQMUXA_A0_0,
2858 
    I3 => PRSTATE_1_SQMUXA,
2859 
    O => N_599_I);
2860 
  II_ctrl_v_ssrstate_1_0_d_bmHAKL3HAKR: LUT2
2861 
  generic map(
2862 
    INIT => X"1"
2863 
  )
2864 
  port map (
2865 
    I0 => n_ahbsi_hwrite,
2866 
    I1 => ssrstate_1_sqmuxa_1,
2867 
    O => SSRSTATE_1_0_D_BM(3));
2868 
  II_ctrl_v_ssrstate_1_0_d_amHAKL3HAKR: LUT3
2869 
  generic map(
2870 
    INIT => X"20"
2871 
  )
2872 
  port map (
2873 
    I0 => rst,
2874 
    I1 => D16MUXC_0_4_INT_73,
2875 
    I2 => SSRSTATE_3_INT_23,
2876 
    O => SSRSTATE_1_0_D_AM(3));
2877 
  II_v_writen_0_sqmuxa_0_2: LUT4
2878 
  generic map(
2879 
    INIT => X"0E00"
2880 
  )
2881 
  port map (
2882 
    I0 => n_ahbsi_hwrite,
2883 
    I1 => SSRSTATE6_XX_MM_M3_INT_64,
2884 
    I2 => ssrstate_1_sqmuxa_1,
2885 
    I3 => WRITEN_0_SQMUXA_0_0,
2886 
    O => WRITEN_0_SQMUXA_0_2);
2887 
  II_un1_r_ssrstate_12_1: LUT4
2888 
  generic map(
2889 
    INIT => X"0111"
2890 
  )
2891 
  port map (
2892 
    I0 => SSRSTATE_3_INT_23,
2893 
    I1 => BDRIVE_1_SQMUXA_2,
2894 
    I2 => WS_0_SQMUXA_0_0_0,
2895 
    I3 => WS_0_SQMUXA_0_C_INT_50,
2896 
    O => SSRSTATE_12_1);
2897 
  II_v_ws_2_sqmuxa_3_d: LUT4
2898 
  generic map(
2899 
    INIT => X"4FFF"
2900 
  )
2901 
  port map (
2902 
    I0 => UN1_AHBSI_INT_68,
2903 
    I1 => HSEL_5_INT_67,
2904 
    I2 => SSRSTATE_1_INT_21,
2905 
    I3 => WS_0_SQMUXA_1_INT_57,
2906 
    O => WS_2_SQMUXA_3_D_INT_56);
2907 
  II_un1_v_writen_2_sqmuxa_tz_0: LUT4
2908 
  generic map(
2909 
    INIT => X"00E0"
2910 
  )
2911 
  port map (
2912 
    I0 => n_ahbsi_hwrite,
2913 
    I1 => SSRSTATE6_XX_MM_M3_INT_64,
2914 
    I2 => SSRSTATE_2_I_INT_55,
2915 
    I3 => WS_3_SQMUXA_1_INT_53,
2916 
    O => WRITEN_2_SQMUXA_TZ_0);
2917 
  II_un1_r_ssrstate_9: LUT4
2918 
  generic map(
2919 
    INIT => X"0070"
2920 
  )
2921 
  port map (
2922 
    I0 => N_654,
2923 
    I1 => SSRSTATE_2_INT_22,
2924 
    I2 => SSRSTATE_2_I_INT_55,
2925 
    I3 => WS_3_SQMUXA_1_INT_53,
2926 
    O => SSRSTATE_9);
2927 
  II_ctrl_v_bdrive_1_iv_m9_i_0_0: LUT2
2928 
  generic map(
2929 
    INIT => X"8"
2930 
  )
2931 
  port map (
2932 
    I0 => BDRIVE_1_IV_0_1,
2933 
    I1 => BDRIVE_1_IV_M9_I_0,
2934 
    O => BDRIVE_1_IV_M9_I_0_0);
2935 
  II_un1_r_prstate_12_m7_i_a6_0: LUT4_L
2936 
  generic map(
2937 
    INIT => X"0400"
2938 
  )
2939 
  port map (
2940 
    I0 => UN1_AHBSI_INT_68,
2941 
    I1 => change_3_f0,
2942 
    I2 => HMBSEL_4_1_INT_14,
2943 
    I3 => HSEL_5_INT_67,
2944 
    LO => PRSTATE_12_M7_I_A6_0);
2945 
  II_v_bwn_1_sqmuxa_2_d_0: LUT4
2946 
  generic map(
2947 
    INIT => X"FBFF"
2948 
  )
2949 
  port map (
2950 
    I0 => n_ahbsi_hwrite,
2951 
    I1 => HMBSEL_4_1_INT_14,
2952 
    I2 => CHANGE_1_SQMUXA_N_3_INT_63,
2953 
    I3 => SSRHREADY_2_SQMUXA_0_0_INT_62,
2954 
    O => BWN_1_SQMUXA_2_D_0);
2955 
  II_un1_v_ssrstate23_u_0_bmHAKL4HAKR: LUT3
2956 
  generic map(
2957 
    INIT => X"B0"
2958 
  )
2959 
  port map (
2960 
    I0 => UN1_AHBSI_INT_68,
2961 
    I1 => HSEL_5_INT_67,
2962 
    I2 => SSRSTATE_2_INT_22,
2963 
    O => SSRSTATE23_U_0_BM(4));
2964 
  II_un1_v_ssrstate23_u_0_amHAKL4HAKR: LUT3
2965 
  generic map(
2966 
    INIT => X"02"
2967 
  )
2968 
  port map (
2969 
    I0 => SSRSTATE23_1,
2970 
    I1 => WS_0_INT_16,
2971 
    I2 => WS_3_INT_19,
2972 
    O => SSRSTATE23_U_0_AM(4));
2973 
  II_v_writen_0_sqmuxa_d: LUT4
2974 
  generic map(
2975 
    INIT => X"40FF"
2976 
  )
2977 
  port map (
2978 
    I0 => UN1_AHBSI_INT_68,
2979 
    I1 => HMBSEL_4_1_INT_14,
2980 
    I2 => HSEL_5_INT_67,
2981 
    I3 => SSRSTATE_2_INT_22,
2982 
    O => WRITEN_0_SQMUXA_D);
2983 
  II_ctrl_v_ws_1_2_0_dHAKL1HAKR: LUT3
2984 
  generic map(
2985 
    INIT => X"E2"
2986 
  )
2987 
  port map (
2988 
    I0 => N_362,
2989 
    I1 => N_365,
2990 
    I2 => ROMRWS(1),
2991 
    O => WS_1_2_0_D(1));
2992 
  II_ctrl_v_ws_1_2_0_dHAKL2HAKR: LUT3
2993 
  generic map(
2994 
    INIT => X"E2"
2995 
  )
2996 
  port map (
2997 
    I0 => N_363,
2998 
    I1 => N_365,
2999 
    I2 => ROMRWS(2),
3000 
    O => WS_1_2_0_D(2));
3001 
  II_r_prstatesr_0: LUT3
3002 
  generic map(
3003 
    INIT => X"0B"
3004 
  )
3005 
  port map (
3006 
    I0 => un7_bus16en,
3007 
    I1 => PRSTATE_0_INT_27,
3008 
    I2 => PRSTATE_1_SQMUXA,
3009 
    O => PRSTATESR_0);
3010 
  II_un1_v_haddr_0_sqmuxa_a0_0: LUT3
3011 
  generic map(
3012 
    INIT => X"07"
3013 
  )
3014 
  port map (
3015 
    I0 => un7_bus16en,
3016 
    I1 => PRSTATE_0_INT_27,
3017 
    I2 => PRSTATE_5_INT_32,
3018 
    O => HADDR_0_SQMUXA_A0_0);
3019 
  II_ctrl_v_bdrive_1_iv_0_a1: LUT3
3020 
  generic map(
3021 
    INIT => X"40"
3022 
  )
3023 
  port map (
3024 
    I0 => D16MUXC_0_4_INT_73,
3025 
    I1 => SETBDRIVE,
3026 
    I2 => BDRIVE_1_SQMUXA,
3027 
    O => BDRIVE_1_IV_0_A1);
3028 
  II_v_prstate_1_0_a3HAKL4HAKR: LUT3
3029 
  generic map(
3030 
    INIT => X"80"
3031 
  )
3032 
  port map (
3033 
    I0 => rst,
3034 
    I1 => un7_bus16en,
3035 
    I2 => d16mux_0_sqmuxa,
3036 
    O => N_341);
3037 
  II_v_bdrive_0_sqmuxa_2_0: LUT4
3038 
  generic map(
3039 
    INIT => X"FF10"
3040 
  )
3041 
  port map (
3042 
    I0 => N_668,
3043 
    I1 => D16MUXC_0_4_INT_73,
3044 
    I2 => PRSTATE_1_INT_28,
3045 
    I3 => BDRIVE_0_SQMUXA_2_0_0,
3046 
    O => BDRIVE_0_SQMUXA_2_C);
3047 
  II_ctrl_v_bdrive_1_iv_m9_i_0: LUT3
3048 
  generic map(
3049 
    INIT => X"13"
3050 
  )
3051 
  port map (
3052 
    I0 => BDRIVE_1_IV_0_A4_0,
3053 
    I1 => PRSTATE_2_REP1_INT_59,
3054 
    I2 => BDRIVE_1_SQMUXA,
3055 
    O => BDRIVE_1_IV_M9_I_0);
3056 
  II_v_ws_0_sqmuxa_0_0_0: LUT4
3057 
  generic map(
3058 
    INIT => X"3133"
3059 
  )
3060 
  port map (
3061 
    I0 => HSEL_5_INT_67,
3062 
    I1 => D16MUXC_0_4_INT_73,
3063 
    I2 => SSRSTATE_0_INT_20,
3064 
    I3 => WS_0_SQMUXA_C_INT_49,
3065 
    O => WS_0_SQMUXA_0_0_0);
3066 
  II_v_prhready_0_sqmuxa: LUT3
3067 
  generic map(
3068 
    INIT => X"A8"
3069 
  )
3070 
  port map (
3071 
    I0 => un7_bus16en,
3072 
    I1 => PRSTATE_0_INT_27,
3073 
    I2 => d16mux_0_sqmuxa,
3074 
    O => PRHREADY_0_SQMUXA);
3075 
  II_v_ws_0_sqmuxa_1: LUT2
3076 
  generic map(
3077 
    INIT => X"4"
3078 
  )
3079 
  port map (
3080 
    I0 => N_656_INT_66,
3081 
    I1 => rst,
3082 
    O => WS_0_SQMUXA_1_INT_57);
3083 
  II_v_ws_0_sqmuxa_0: LUT4
3084 
  generic map(
3085 
    INIT => X"040F"
3086 
  )
3087 
  port map (
3088 
    I0 => UN1_AHBSI_INT_68,
3089 
    I1 => HSEL_5_INT_67,
3090 
    I2 => SSRSTATE_0_INT_20,
3091 
    I3 => SSRSTATE_1_INT_21,
3092 
    O => SSRSTATE_5_I);
3093 
  II_v_prstate_1_i_m4_0HAKL2HAKR: LUT3
3094 
  generic map(
3095 
    INIT => X"CA"
3096 
  )
3097 
  port map (
3098 
    I0 => HWRITE_1,
3099 
    I1 => un7_bus16en,
3100 
    I2 => PRSTATE_0_INT_27,
3101 
    O => N_336);
3102 
  II_v_bdrive_1_sqmuxa_2: LUT3
3103 
  generic map(
3104 
    INIT => X"40"
3105 
  )
3106 
  port map (
3107 
    I0 => UN1_AHBSI_INT_68,
3108 
    I1 => HSEL_5_INT_67,
3109 
    I2 => SSRSTATE_1_INT_21,
3110 
    O => BDRIVE_1_SQMUXA_2);
3111 
  II_ctrl_v_bdrive_1_iv_0_a0: LUT4
3112 
  generic map(
3113 
    INIT => X"4000"
3114 
  )
3115 
  port map (
3116 
    I0 => UN1_AHBSI_INT_68,
3117 
    I1 => BDRIVE_1_IV_0_A4_0,
3118 
    I2 => HSEL_5_INT_67,
3119 
    I3 => SSRSTATE_1_INT_21,
3120 
    O => BDRIVE_1_IV_0_A0);
3121 
  II_ctrl_v_bdrive_1_iv_m9_i_a4_0_2_1: LUT4
3122 
  generic map(
3123 
    INIT => X"80A0"
3124 
  )
3125 
  port map (
3126 
    I0 => N_668,
3127 
    I1 => SSRSTATE10,
3128 
    I2 => D16MUXC_0_4_INT_73,
3129 
    I3 => SSRSTATE_3_INT_23,
3130 
    O => BDRIVE_1_IV_M9_I_A4_0_2_1);
3131 
  II_v_ws_0_sqmuxa_0_c: LUT2
3132 
  generic map(
3133 
    INIT => X"E"
3134 
  )
3135 
  port map (
3136 
    I0 => SSRSTATE_0_INT_20,
3137 
    I1 => SSRSTATE_1_INT_21,
3138 
    O => WS_0_SQMUXA_0_C_INT_50);
3139 
  II_un1_r_prstate_12_m7_i_a6: LUT2
3140 
  generic map(
3141 
    INIT => X"8"
3142 
  )
3143 
  port map (
3144 
    I0 => change_3_f0,
3145 
    I1 => CHANGE_INT_69,
3146 
    O => PRSTATE_12_M7_I_A6);
3147 
  II_v_prstate_1_sqmuxa: LUT2
3148 
  generic map(
3149 
    INIT => X"4"
3150 
  )
3151 
  port map (
3152 
    I0 => un7_bus16en,
3153 
    I1 => d16mux_0_sqmuxa,
3154 
    O => PRSTATE_1_SQMUXA);
3155 
  II_ctrl_v_hwdataout_1_0_0HAKL16HAKR: LUT4_L
3156 
  generic map(
3157 
    INIT => X"ACCC"
3158 
  )
3159 
  port map (
3160 
    I0 => n_ahbsi_hwdata(0),
3161 
    I1 => n_ahbsi_hwdata(16),
3162 
    I2 => N_SRO_ADDRESS_1_INT_37,
3163 
    I3 => BUS16EN_INT_72,
3164 
    LO => N_382);
3165 
  II_ctrl_v_hwdataout_1_0_0HAKL17HAKR: LUT4_L
3166 
  generic map(
3167 
    INIT => X"ACCC"
3168 
  )
3169 
  port map (
3170 
    I0 => n_ahbsi_hwdata(1),
3171 
    I1 => n_ahbsi_hwdata(17),
3172 
    I2 => N_SRO_ADDRESS_1_INT_37,
3173 
    I3 => BUS16EN_INT_72,
3174 
    LO => N_383);
3175 
  II_ctrl_v_hwdataout_1_0_0HAKL18HAKR: LUT4_L
3176 
  generic map(
3177 
    INIT => X"ACCC"
3178 
  )
3179 
  port map (
3180 
    I0 => n_ahbsi_hwdata(2),
3181 
    I1 => n_ahbsi_hwdata(18),
3182 
    I2 => N_SRO_ADDRESS_1_INT_37,
3183 
    I3 => BUS16EN_INT_72,
3184 
    LO => N_384);
3185 
  II_ctrl_v_hwdataout_1_0_0HAKL19HAKR: LUT4_L
3186 
  generic map(
3187 
    INIT => X"ACCC"
3188 
  )
3189 
  port map (
3190 
    I0 => n_ahbsi_hwdata(3),
3191 
    I1 => n_ahbsi_hwdata(19),
3192 
    I2 => N_SRO_ADDRESS_1_INT_37,
3193 
    I3 => BUS16EN_INT_72,
3194 
    LO => N_385);
3195 
  II_ctrl_v_hwdataout_1_0_0HAKL20HAKR: LUT4_L
3196 
  generic map(
3197 
    INIT => X"ACCC"
3198 
  )
3199 
  port map (
3200 
    I0 => n_ahbsi_hwdata(4),
3201 
    I1 => n_ahbsi_hwdata(20),
3202 
    I2 => N_SRO_ADDRESS_1_INT_37,
3203 
    I3 => BUS16EN_INT_72,
3204 
    LO => N_386);
3205 
  II_ctrl_v_hwdataout_1_0_0HAKL21HAKR: LUT4_L
3206 
  generic map(
3207 
    INIT => X"ACCC"
3208 
  )
3209 
  port map (
3210 
    I0 => n_ahbsi_hwdata(5),
3211 
    I1 => n_ahbsi_hwdata(21),
3212 
    I2 => N_SRO_ADDRESS_1_INT_37,
3213 
    I3 => BUS16EN_INT_72,
3214 
    LO => N_387);
3215 
  II_ctrl_v_hwdataout_1_0_0HAKL22HAKR: LUT4_L
3216 
  generic map(
3217 
    INIT => X"ACCC"
3218 
  )
3219 
  port map (
3220 
    I0 => n_ahbsi_hwdata(6),
3221 
    I1 => n_ahbsi_hwdata(22),
3222 
    I2 => N_SRO_ADDRESS_1_INT_37,
3223 
    I3 => BUS16EN_INT_72,
3224 
    LO => N_388);
3225 
  II_ctrl_v_hwdataout_1_0_0HAKL23HAKR: LUT4_L
3226 
  generic map(
3227 
    INIT => X"ACCC"
3228 
  )
3229 
  port map (
3230 
    I0 => n_ahbsi_hwdata(7),
3231 
    I1 => n_ahbsi_hwdata(23),
3232 
    I2 => N_SRO_ADDRESS_1_INT_37,
3233 
    I3 => BUS16EN_INT_72,
3234 
    LO => N_389);
3235 
  II_ctrl_v_hwdataout_1_0_0HAKL24HAKR: LUT4_L
3236 
  generic map(
3237 
    INIT => X"ACCC"
3238 
  )
3239 
  port map (
3240 
    I0 => n_ahbsi_hwdata(8),
3241 
    I1 => n_ahbsi_hwdata(24),
3242 
    I2 => N_SRO_ADDRESS_1_INT_37,
3243 
    I3 => BUS16EN_INT_72,
3244 
    LO => N_390);
3245 
  II_ctrl_v_hwdataout_1_0_0HAKL25HAKR: LUT4_L
3246 
  generic map(
3247 
    INIT => X"ACCC"
3248 
  )
3249 
  port map (
3250 
    I0 => n_ahbsi_hwdata(9),
3251 
    I1 => n_ahbsi_hwdata(25),
3252 
    I2 => N_SRO_ADDRESS_1_INT_37,
3253 
    I3 => BUS16EN_INT_72,
3254 
    LO => N_391);
3255 
  II_ctrl_v_hwdataout_1_0_0HAKL26HAKR: LUT4_L
3256 
  generic map(
3257 
    INIT => X"ACCC"
3258 
  )
3259 
  port map (
3260 
    I0 => n_ahbsi_hwdata(10),
3261 
    I1 => n_ahbsi_hwdata(26),
3262 
    I2 => N_SRO_ADDRESS_1_INT_37,
3263 
    I3 => BUS16EN_INT_72,
3264 
    LO => N_392);
3265 
  II_ctrl_v_hwdataout_1_0_0HAKL27HAKR: LUT4_L
3266 
  generic map(
3267 
    INIT => X"ACCC"
3268 
  )
3269 
  port map (
3270 
    I0 => n_ahbsi_hwdata(11),
3271 
    I1 => n_ahbsi_hwdata(27),
3272 
    I2 => N_SRO_ADDRESS_1_INT_37,
3273 
    I3 => BUS16EN_INT_72,
3274 
    LO => N_393);
3275 
  II_ctrl_v_hwdataout_1_0_0HAKL28HAKR: LUT4_L
3276 
  generic map(
3277 
    INIT => X"ACCC"
3278 
  )
3279 
  port map (
3280 
    I0 => n_ahbsi_hwdata(12),
3281 
    I1 => n_ahbsi_hwdata(28),
3282 
    I2 => N_SRO_ADDRESS_1_INT_37,
3283 
    I3 => BUS16EN_INT_72,
3284 
    LO => N_394);
3285 
  II_ctrl_v_hwdataout_1_0_0HAKL29HAKR: LUT4_L
3286 
  generic map(
3287 
    INIT => X"ACCC"
3288 
  )
3289 
  port map (
3290 
    I0 => n_ahbsi_hwdata(13),
3291 
    I1 => n_ahbsi_hwdata(29),
3292 
    I2 => N_SRO_ADDRESS_1_INT_37,
3293 
    I3 => BUS16EN_INT_72,
3294 
    LO => N_395);
3295 
  II_ctrl_v_hwdataout_1_0_0HAKL30HAKR: LUT4_L
3296 
  generic map(
3297 
    INIT => X"ACCC"
3298 
  )
3299 
  port map (
3300 
    I0 => n_ahbsi_hwdata(14),
3301 
    I1 => n_ahbsi_hwdata(30),
3302 
    I2 => N_SRO_ADDRESS_1_INT_37,
3303 
    I3 => BUS16EN_INT_72,
3304 
    LO => N_396);
3305 
  II_ctrl_v_hwdataout_1_0_0HAKL31HAKR: LUT4_L
3306 
  generic map(
3307 
    INIT => X"ACCC"
3308 
  )
3309 
  port map (
3310 
    I0 => n_ahbsi_hwdata(15),
3311 
    I1 => n_ahbsi_hwdata(31),
3312 
    I2 => N_SRO_ADDRESS_1_INT_37,
3313 
    I3 => BUS16EN_INT_72,
3314 
    LO => N_397);
3315 
  II_ctrl_v_bwn_1_0_a3_0_1HAKL0HAKR: LUT4_L
3316 
  generic map(
3317 
    INIT => X"0207"
3318 
  )
3319 
  port map (
3320 
    I0 => N_662_INT_60,
3321 
    I1 => n_ahbsi_hsize(0),
3322 
    I2 => hsize_1(1),
3323 
    I3 => SIZE_0_INT_25,
3324 
    LO => N_319_1);
3325 
  II_ctrl_v_bwn_1_0_a3HAKL0HAKR: LUT2
3326 
  generic map(
3327 
    INIT => X"4"
3328 
  )
3329 
  port map (
3330 
    I0 => hsize_1(1),
3331 
    I1 => haddr_0,
3332 
    O => N_317);
3333 
  II_v_writen_0_sqmuxa_0_0: LUT4
3334 
  generic map(
3335 
    INIT => X"4F00"
3336 
  )
3337 
  port map (
3338 
    I0 => n_ahbsi_htrans(0),
3339 
    I1 => n_ahbsi_htrans(1),
3340 
    I2 => SSRSTATE_2_INT_22,
3341 
    I3 => SSRSTATE_2_I_INT_55,
3342 
    O => WRITEN_0_SQMUXA_0_0);
3343 
  II_v_ssrhready_2_sqmuxa_0_0: LUT3
3344 
  generic map(
3345 
    INIT => X"40"
3346 
  )
3347 
  port map (
3348 
    I0 => n_ahbsi_htrans(0),
3349 
    I1 => n_ahbsi_htrans(1),
3350 
    I2 => SSRSTATE_2_INT_22,
3351 
    O => SSRHREADY_2_SQMUXA_0_0_INT_62);
3352 
  II_v_bdrive_0_sqmuxa_2_0_0: LUT4_L
3353 
  generic map(
3354 
    INIT => X"01FF"
3355 
  )
3356 
  port map (
3357 
    I0 => N_668,
3358 
    I1 => PRSTATE_1_INT_28,
3359 
    I2 => PRSTATE_2_REP1_INT_59,
3360 
    I3 => SETBDRIVE,
3361 
    LO => BDRIVE_0_SQMUXA_2_0_0);
3362 
  II_r_d16muxc_0_1: LUT4
3363 
  generic map(
3364 
    INIT => X"000E"
3365 
  )
3366 
  port map (
3367 
    I0 => N_SRO_ADDRESS_1_INT_37,
3368 
    I1 => UN17_BUS16EN,
3369 
    I2 => PRSTATE_0_INT_27,
3370 
    I3 => PRSTATE_5_INT_32,
3371 
    O => D16MUXC_0_1);
3372 
  II_ctrl_v_bdrive_1_iv_0_1: LUT4
3373 
  generic map(
3374 
    INIT => X"BBBF"
3375 
  )
3376 
  port map (
3377 
    I0 => D16MUXC_0_4_INT_73,
3378 
    I1 => SETBDRIVE,
3379 
    I2 => SSRSTATE_0_INT_20,
3380 
    I3 => SSRSTATE_1_INT_21,
3381 
    O => BDRIVE_1_IV_0_1);
3382 
  II_v_ssrstate_11HAKL0HAKR: LUT2
3383 
  generic map(
3384 
    INIT => X"4"
3385 
  )
3386 
  port map (
3387 
    I0 => D16MUXC_0_4_INT_73,
3388 
    I1 => SSRSTATE_0_INT_20,
3389 
    O => SSRSTATE_11(0));
3390 
  II_v_bdrive_1_sqmuxa: LUT4
3391 
  generic map(
3392 
    INIT => X"CC4C"
3393 
  )
3394 
  port map (
3395 
    I0 => SSRSTATE23_1,
3396 
    I1 => SSRSTATE_3_INT_23,
3397 
    I2 => WS_0_INT_16,
3398 
    I3 => WS_3_INT_19,
3399 
    O => BDRIVE_1_SQMUXA);
3400 
  II_v_ssrhready_2_sqmuxa_m2: LUT4
3401 
  generic map(
3402 
    INIT => X"2A7F"
3403 
  )
3404 
  port map (
3405 
    I0 => n_ahbsi_hready,
3406 
    I1 => n_ahbsi_hsel(0),
3407 
    I2 => n_ahbsi_htrans(1),
3408 
    I3 => HSEL_INT_58,
3409 
    O => CHANGE_1_SQMUXA_N_3_INT_63);
3410 
  II_ctrl_hwrite_1_0: LUT3
3411 
  generic map(
3412 
    INIT => X"D8"
3413 
  )
3414 
  port map (
3415 
    I0 => N_662_INT_60,
3416 
    I1 => n_ahbsi_hwrite,
3417 
    I2 => HWRITE,
3418 
    O => HWRITE_1);
3419 
  II_haddr_0HAKL3HAKR: LUT3
3420 
  generic map(
3421 
    INIT => X"D8"
3422 
  )
3423 
  port map (
3424 
    I0 => N_662_INT_60,
3425 
    I1 => n_ahbsi_haddr(3),
3426 
    I2 => HADDR(3),
3427 
    O => NN_1);
3428 
  II_haddr_0HAKL4HAKR: LUT3
3429 
  generic map(
3430 
    INIT => X"D8"
3431 
  )
3432 
  port map (
3433 
    I0 => N_662_INT_60,
3434 
    I1 => n_ahbsi_haddr(4),
3435 
    I2 => HADDR(4),
3436 
    O => NN_2);
3437 
  II_haddr_0HAKL5HAKR: LUT3
3438 
  generic map(
3439 
    INIT => X"D8"
3440 
  )
3441 
  port map (
3442 
    I0 => N_662_INT_60,
3443 
    I1 => n_ahbsi_haddr(5),
3444 
    I2 => HADDR(5),
3445 
    O => NN_3);
3446 
  II_haddr_0HAKL6HAKR: LUT3
3447 
  generic map(
3448 
    INIT => X"D8"
3449 
  )
3450 
  port map (
3451 
    I0 => N_662_INT_60,
3452 
    I1 => n_ahbsi_haddr(6),
3453 
    I2 => HADDR(6),
3454 
    O => NN_4);
3455 
  II_haddr_0HAKL7HAKR: LUT3
3456 
  generic map(
3457 
    INIT => X"D8"
3458 
  )
3459 
  port map (
3460 
    I0 => N_662_INT_60,
3461 
    I1 => n_ahbsi_haddr(7),
3462 
    I2 => HADDR(7),
3463 
    O => NN_5);
3464 
  II_haddr_0HAKL8HAKR: LUT3
3465 
  generic map(
3466 
    INIT => X"D8"
3467 
  )
3468 
  port map (
3469 
    I0 => N_662_INT_60,
3470 
    I1 => n_ahbsi_haddr(8),
3471 
    I2 => HADDR(8),
3472 
    O => NN_6);
3473 
  II_haddr_0HAKL9HAKR: LUT3
3474 
  generic map(
3475 
    INIT => X"D8"
3476 
  )
3477 
  port map (
3478 
    I0 => N_662_INT_60,
3479 
    I1 => n_ahbsi_haddr(9),
3480 
    I2 => HADDR(9),
3481 
    O => NN_7);
3482 
  II_haddr_0HAKL10HAKR: LUT3
3483 
  generic map(
3484 
    INIT => X"D8"
3485 
  )
3486 
  port map (
3487 
    I0 => N_662_INT_60,
3488 
    I1 => n_ahbsi_haddr(10),
3489 
    I2 => HADDR(10),
3490 
    O => NN_8);
3491 
  II_haddr_0HAKL11HAKR: LUT3
3492 
  generic map(
3493 
    INIT => X"D8"
3494 
  )
3495 
  port map (
3496 
    I0 => N_662_INT_60,
3497 
    I1 => n_ahbsi_haddr(11),
3498 
    I2 => HADDR(11),
3499 
    O => NN_9);
3500 
  II_ctrl_v_hsel_5_0: LUT4
3501 
  generic map(
3502 
    INIT => X"D580"
3503 
  )
3504 
  port map (
3505 
    I0 => n_ahbsi_hready,
3506 
    I1 => n_ahbsi_hsel(0),
3507 
    I2 => n_ahbsi_htrans(1),
3508 
    I3 => HSEL_INT_58,
3509 
    O => HSEL_5_INT_67);
3510 
  II_ctrl_v_ws_1_1_0HAKL2HAKR: LUT4
3511 
  generic map(
3512 
    INIT => X"F780"
3513 
  )
3514 
  port map (
3515 
    I0 => N_SRO_ROMSN_0_INT_12,
3516 
    I1 => rst,
3517 
    I2 => IOWS(2),
3518 
    I3 => ROMWWS(2),
3519 
    O => N_363);
3520 
  II_ctrl_v_ws_1_1_0HAKL1HAKR: LUT4
3521 
  generic map(
3522 
    INIT => X"F780"
3523 
  )
3524 
  port map (
3525 
    I0 => N_SRO_ROMSN_0_INT_12,
3526 
    I1 => rst,
3527 
    I2 => IOWS(1),
3528 
    I3 => ROMWWS(1),
3529 
    O => N_362);
3530 
  II_v_ws_3_sqmuxa_1_a0_2: LUT4
3531 
  generic map(
3532 
    INIT => X"8000"
3533 
  )
3534 
  port map (
3535 
    I0 => n_ahbsi_hsel(0),
3536 
    I1 => n_ahbsi_htrans(0),
3537 
    I2 => n_ahbsi_htrans(1),
3538 
    I3 => SSRSTATE_1_INT_21,
3539 
    O => WS_3_SQMUXA_1_A0_2);
3540 
  II_r_d16muxc_2: LUT3
3541 
  generic map(
3542 
    INIT => X"02"
3543 
  )
3544 
  port map (
3545 
    I0 => BUS16EN_INT_72,
3546 
    I1 => WS_0_INT_16,
3547 
    I2 => WS_3_INT_19,
3548 
    O => D16MUXC_2);
3549 
  II_r_d16muxc_1: LUT4
3550 
  generic map(
3551 
    INIT => X"0020"
3552 
  )
3553 
  port map (
3554 
    I0 => PRSTATE_3_INT_30,
3555 
    I1 => SIZE_0_INT_25,
3556 
    I2 => SIZE_1_INT_26,
3557 
    I3 => WS_1_INT_17,
3558 
    O => D16MUXC_1);
3559 
  II_un1_v_ssrstate17_2_0_m6_i_a3_a0_1: LUT2
3560 
  generic map(
3561 
    INIT => X"4"
3562 
  )
3563 
  port map (
3564 
    I0 => HMBSEL_1_INT_34,
3565 
    I1 => HSEL_INT_58,
3566 
    O => SSRSTATE17_2_0_M6_I_A3_A0_1);
3567 
  II_un1_v_ssrstate17_2_0_m6_i_a3_a2: LUT4
3568 
  generic map(
3569 
    INIT => X"4000"
3570 
  )
3571 
  port map (
3572 
    I0 => n_ahbsi_hmbsel(1),
3573 
    I1 => n_ahbsi_hready,
3574 
    I2 => n_ahbsi_hsel(0),
3575 
    I3 => n_ahbsi_htrans(1),
3576 
    O => ssrstate17_2_0_m6_i_a3_a2);
3577 
  II_v_ws_1_sqmuxa: LUT3
3578 
  generic map(
3579 
    INIT => X"40"
3580 
  )
3581 
  port map (
3582 
    I0 => N_SRO_ROMSN_0_INT_12,
3583 
    I1 => rst,
3584 
    I2 => PRSTATE_4_INT_31,
3585 
    O => WS_1_SQMUXA_INT_52);
3586 
  II_ctrl_v_ssrstate10: LUT4
3587 
  generic map(
3588 
    INIT => X"0002"
3589 
  )
3590 
  port map (
3591 
    I0 => WS_0_INT_16,
3592 
    I1 => WS_1_INT_17,
3593 
    I2 => WS_2_INT_18,
3594 
    I3 => WS_3_INT_19,
3595 
    O => SSRSTATE10);
3596 
  II_r_d16muxc_0_4: LUT4
3597 
  generic map(
3598 
    INIT => X"0001"
3599 
  )
3600 
  port map (
3601 
    I0 => WS_0_INT_16,
3602 
    I1 => WS_1_INT_17,
3603 
    I2 => WS_2_INT_18,
3604 
    I3 => WS_3_INT_19,
3605 
    O => D16MUXC_0_4_INT_73);
3606 
  II_un1_r_ssrstate_3: LUT3
3607 
  generic map(
3608 
    INIT => X"8A"
3609 
  )
3610 
  port map (
3611 
    I0 => d_m2_0_a2_0,
3612 
    I1 => SETBDRIVE,
3613 
    I2 => SSRSTATE_3_INT_23,
3614 
    O => SSRSTATE_3);
3615 
  II_v_ws_0_sqmuxa_c: LUT3
3616 
  generic map(
3617 
    INIT => X"EF"
3618 
  )
3619 
  port map (
3620 
    I0 => n_ahbsi_htrans(0),
3621 
    I1 => n_ahbsi_htrans(1),
3622 
    I2 => SSRSTATE_1_INT_21,
3623 
    O => WS_0_SQMUXA_C_INT_49);
3624 
  II_un1_r_prstate_12_0: LUT3
3625 
  generic map(
3626 
    INIT => X"01"
3627 
  )
3628 
  port map (
3629 
    I0 => PRSTATE_0_INT_27,
3630 
    I1 => PRSTATE_1_INT_28,
3631 
    I2 => PRSTATE_2_REP1_INT_59,
3632 
    O => PRSTATE_12_0);
3633 
  II_regsdHAKL8HAKR: LUT3
3634 
  generic map(
3635 
    INIT => X"10"
3636 
  )
3637 
  port map (
3638 
    I0 => n_apbi_paddr(2),
3639 
    I1 => n_apbi_paddr(3),
3640 
    I2 => ROMWIDTH(0),
3641 
    O => n_apbo_prdata_8);
3642 
  II_regsdHAKL9HAKR: LUT3
3643 
  generic map(
3644 
    INIT => X"10"
3645 
  )
3646 
  port map (
3647 
    I0 => n_apbi_paddr(2),
3648 
    I1 => n_apbi_paddr(3),
3649 
    I2 => ROMWIDTH(1),
3650 
    O => n_apbo_prdata_9);
3651 
  II_regsdHAKL11HAKR: LUT3
3652 
  generic map(
3653 
    INIT => X"10"
3654 
  )
3655 
  port map (
3656 
    I0 => n_apbi_paddr(2),
3657 
    I1 => n_apbi_paddr(3),
3658 
    I2 => ROMWRITE,
3659 
    O => n_apbo_prdata_11);
3660 
  II_regsdHAKL1HAKR: LUT3
3661 
  generic map(
3662 
    INIT => X"10"
3663 
  )
3664 
  port map (
3665 
    I0 => n_apbi_paddr(2),
3666 
    I1 => n_apbi_paddr(3),
3667 
    I2 => ROMRWS(1),
3668 
    O => n_apbo_prdata_1);
3669 
  II_regsdHAKL2HAKR: LUT3
3670 
  generic map(
3671 
    INIT => X"10"
3672 
  )
3673 
  port map (
3674 
    I0 => n_apbi_paddr(2),
3675 
    I1 => n_apbi_paddr(3),
3676 
    I2 => ROMRWS(2),
3677 
    O => n_apbo_prdata_2);
3678 
  II_regsdHAKL3HAKR: LUT3
3679 
  generic map(
3680 
    INIT => X"10"
3681 
  )
3682 
  port map (
3683 
    I0 => n_apbi_paddr(2),
3684 
    I1 => n_apbi_paddr(3),
3685 
    I2 => ROMRWS_3_INT_10,
3686 
    O => n_apbo_prdata_3);
3687 
  II_regsdHAKL5HAKR: LUT3
3688 
  generic map(
3689 
    INIT => X"10"
3690 
  )
3691 
  port map (
3692 
    I0 => n_apbi_paddr(2),
3693 
    I1 => n_apbi_paddr(3),
3694 
    I2 => ROMWWS(1),
3695 
    O => n_apbo_prdata_5);
3696 
  II_regsdHAKL6HAKR: LUT3
3697 
  generic map(
3698 
    INIT => X"10"
3699 
  )
3700 
  port map (
3701 
    I0 => n_apbi_paddr(2),
3702 
    I1 => n_apbi_paddr(3),
3703 
    I2 => ROMWWS(2),
3704 
    O => n_apbo_prdata_6);
3705 
  II_regsdHAKL7HAKR: LUT3
3706 
  generic map(
3707 
    INIT => X"10"
3708 
  )
3709 
  port map (
3710 
    I0 => n_apbi_paddr(2),
3711 
    I1 => n_apbi_paddr(3),
3712 
    I2 => ROMWWS_3_INT_8,
3713 
    O => n_apbo_prdata_7);
3714 
  II_regsdHAKL19HAKR: LUT3
3715 
  generic map(
3716 
    INIT => X"10"
3717 
  )
3718 
  port map (
3719 
    I0 => n_apbi_paddr(2),
3720 
    I1 => n_apbi_paddr(3),
3721 
    I2 => IOEN,
3722 
    O => n_apbo_prdata_19);
3723 
  II_regsdHAKL21HAKR: LUT3
3724 
  generic map(
3725 
    INIT => X"10"
3726 
  )
3727 
  port map (
3728 
    I0 => n_apbi_paddr(2),
3729 
    I1 => n_apbi_paddr(3),
3730 
    I2 => IOWS(1),
3731 
    O => n_apbo_prdata_21);
3732 
  II_regsdHAKL22HAKR: LUT3
3733 
  generic map(
3734 
    INIT => X"10"
3735 
  )
3736 
  port map (
3737 
    I0 => n_apbi_paddr(2),
3738 
    I1 => n_apbi_paddr(3),
3739 
    I2 => IOWS(2),
3740 
    O => n_apbo_prdata_22);
3741 
  II_regsdHAKL23HAKR: LUT3
3742 
  generic map(
3743 
    INIT => X"10"
3744 
  )
3745 
  port map (
3746 
    I0 => n_apbi_paddr(2),
3747 
    I1 => n_apbi_paddr(3),
3748 
    I2 => IOWS_3_INT_6,
3749 
    O => n_apbo_prdata_23);
3750 
  II_regsdHAKL20HAKR: LUT3
3751 
  generic map(
3752 
    INIT => X"10"
3753 
  )
3754 
  port map (
3755 
    I0 => n_apbi_paddr(2),
3756 
    I1 => n_apbi_paddr(3),
3757 
    I2 => IOWS_0_INT_5,
3758 
    O => n_apbo_prdata_20);
3759 
  II_regsdHAKL4HAKR: LUT3
3760 
  generic map(
3761 
    INIT => X"10"
3762 
  )
3763 
  port map (
3764 
    I0 => n_apbi_paddr(2),
3765 
    I1 => n_apbi_paddr(3),
3766 
    I2 => ROMWWS_0_INT_7,
3767 
    O => n_apbo_prdata_4);
3768 
  II_regsdHAKL0HAKR: LUT3
3769 
  generic map(
3770 
    INIT => X"10"
3771 
  )
3772 
  port map (
3773 
    I0 => n_apbi_paddr(2),
3774 
    I1 => n_apbi_paddr(3),
3775 
    I2 => ROMRWS_0_INT_9,
3776 
    O => n_apbo_prdata_0);
3777 
  II_v_hmbsel_0_sqmuxa: LUT2
3778 
  generic map(
3779 
    INIT => X"8"
3780 
  )
3781 
  port map (
3782 
    I0 => n_ahbsi_hready,
3783 
    I1 => hsel_4,
3784 
    O => HMBSEL_0_SQMUXA);
3785 
  II_v_data16_0_sqmuxa: LUT2
3786 
  generic map(
3787 
    INIT => X"8"
3788 
  )
3789 
  port map (
3790 
    I0 => BUS16EN_INT_72,
3791 
    I1 => PRSTATE_4_INT_31,
3792 
    O => DATA16_0_SQMUXA);
3793 
  II_hrdata_0HAKL31HAKR: LUT3
3794 
  generic map(
3795 
    INIT => X"D8"
3796 
  )
3797 
  port map (
3798 
    I0 => D16MUX(0),
3799 
    I1 => DATA16(15),
3800 
    I2 => HRDATA(31),
3801 
    O => n_ahbso_hrdata(31));
3802 
  II_hrdata_0HAKL30HAKR: LUT3
3803 
  generic map(
3804 
    INIT => X"D8"
3805 
  )
3806 
  port map (
3807 
    I0 => D16MUX(0),
3808 
    I1 => DATA16(14),
3809 
    I2 => HRDATA(30),
3810 
    O => n_ahbso_hrdata(30));
3811 
  II_hrdata_0HAKL29HAKR: LUT3
3812 
  generic map(
3813 
    INIT => X"D8"
3814 
  )
3815 
  port map (
3816 
    I0 => D16MUX(0),
3817 
    I1 => DATA16(13),
3818 
    I2 => HRDATA(29),
3819 
    O => n_ahbso_hrdata(29));
3820 
  II_hrdata_0HAKL28HAKR: LUT3
3821 
  generic map(
3822 
    INIT => X"D8"
3823 
  )
3824 
  port map (
3825 
    I0 => D16MUX(0),
3826 
    I1 => DATA16(12),
3827 
    I2 => HRDATA(28),
3828 
    O => n_ahbso_hrdata(28));
3829 
  II_hrdata_0HAKL27HAKR: LUT3
3830 
  generic map(
3831 
    INIT => X"D8"
3832 
  )
3833 
  port map (
3834 
    I0 => D16MUX(0),
3835 
    I1 => DATA16(11),
3836 
    I2 => HRDATA(27),
3837 
    O => n_ahbso_hrdata(27));
3838 
  II_hrdata_0HAKL26HAKR: LUT3
3839 
  generic map(
3840 
    INIT => X"D8"
3841 
  )
3842 
  port map (
3843 
    I0 => D16MUX(0),
3844 
    I1 => DATA16(10),
3845 
    I2 => HRDATA(26),
3846 
    O => n_ahbso_hrdata(26));
3847 
  II_hrdata_0HAKL25HAKR: LUT3
3848 
  generic map(
3849 
    INIT => X"D8"
3850 
  )
3851 
  port map (
3852 
    I0 => D16MUX(0),
3853 
    I1 => DATA16(9),
3854 
    I2 => HRDATA(25),
3855 
    O => n_ahbso_hrdata(25));
3856 
  II_hrdata_0HAKL24HAKR: LUT3
3857 
  generic map(
3858 
    INIT => X"D8"
3859 
  )
3860 
  port map (
3861 
    I0 => D16MUX(0),
3862 
    I1 => DATA16(8),
3863 
    I2 => HRDATA(24),
3864 
    O => n_ahbso_hrdata(24));
3865 
  II_hrdata_0HAKL23HAKR: LUT3
3866 
  generic map(
3867 
    INIT => X"D8"
3868 
  )
3869 
  port map (
3870 
    I0 => D16MUX(0),
3871 
    I1 => DATA16(7),
3872 
    I2 => HRDATA(23),
3873 
    O => n_ahbso_hrdata(23));
3874 
  II_hrdata_0HAKL22HAKR: LUT3
3875 
  generic map(
3876 
    INIT => X"D8"
3877 
  )
3878 
  port map (
3879 
    I0 => D16MUX(0),
3880 
    I1 => DATA16(6),
3881 
    I2 => HRDATA(22),
3882 
    O => n_ahbso_hrdata(22));
3883 
  II_hrdata_0HAKL21HAKR: LUT3
3884 
  generic map(
3885 
    INIT => X"D8"
3886 
  )
3887 
  port map (
3888 
    I0 => D16MUX(0),
3889 
    I1 => DATA16(5),
3890 
    I2 => HRDATA(21),
3891 
    O => n_ahbso_hrdata(21));
3892 
  II_hrdata_0HAKL20HAKR: LUT3
3893 
  generic map(
3894 
    INIT => X"D8"
3895 
  )
3896 
  port map (
3897 
    I0 => D16MUX(0),
3898 
    I1 => DATA16(4),
3899 
    I2 => HRDATA(20),
3900 
    O => n_ahbso_hrdata(20));
3901 
  II_hrdata_0HAKL19HAKR: LUT3
3902 
  generic map(
3903 
    INIT => X"D8"
3904 
  )
3905 
  port map (
3906 
    I0 => D16MUX(0),
3907 
    I1 => DATA16(3),
3908 
    I2 => HRDATA(19),
3909 
    O => n_ahbso_hrdata(19));
3910 
  II_hrdata_0HAKL18HAKR: LUT3
3911 
  generic map(
3912 
    INIT => X"D8"
3913 
  )
3914 
  port map (
3915 
    I0 => D16MUX(0),
3916 
    I1 => DATA16(2),
3917 
    I2 => HRDATA(18),
3918 
    O => n_ahbso_hrdata(18));
3919 
  II_hrdata_0HAKL17HAKR: LUT3
3920 
  generic map(
3921 
    INIT => X"D8"
3922 
  )
3923 
  port map (
3924 
    I0 => D16MUX(0),
3925 
    I1 => DATA16(1),
3926 
    I2 => HRDATA(17),
3927 
    O => n_ahbso_hrdata(17));
3928 
  II_hrdata_0HAKL16HAKR: LUT3
3929 
  generic map(
3930 
    INIT => X"D8"
3931 
  )
3932 
  port map (
3933 
    I0 => D16MUX(0),
3934 
    I1 => DATA16(0),
3935 
    I2 => HRDATA(16),
3936 
    O => n_ahbso_hrdata(16));
3937 
  II_hrdata_0HAKL15HAKR: LUT3
3938 
  generic map(
3939 
    INIT => X"E4"
3940 
  )
3941 
  port map (
3942 
    I0 => D16MUX(1),
3943 
    I1 => HRDATA(15),
3944 
    I2 => HRDATA(31),
3945 
    O => n_ahbso_hrdata(15));
3946 
  II_hrdata_0HAKL14HAKR: LUT3
3947 
  generic map(
3948 
    INIT => X"E4"
3949 
  )
3950 
  port map (
3951 
    I0 => D16MUX(1),
3952 
    I1 => HRDATA(14),
3953 
    I2 => HRDATA(30),
3954 
    O => n_ahbso_hrdata(14));
3955 
  II_hrdata_0HAKL13HAKR: LUT3
3956 
  generic map(
3957 
    INIT => X"E4"
3958 
  )
3959 
  port map (
3960 
    I0 => D16MUX(1),
3961 
    I1 => HRDATA(13),
3962 
    I2 => HRDATA(29),
3963 
    O => n_ahbso_hrdata(13));
3964 
  II_hrdata_0HAKL12HAKR: LUT3
3965 
  generic map(
3966 
    INIT => X"E4"
3967 
  )
3968 
  port map (
3969 
    I0 => D16MUX(1),
3970 
    I1 => HRDATA(12),
3971 
    I2 => HRDATA(28),
3972 
    O => n_ahbso_hrdata(12));
3973 
  II_hrdata_0HAKL11HAKR: LUT3
3974 
  generic map(
3975 
    INIT => X"E4"
3976 
  )
3977 
  port map (
3978 
    I0 => D16MUX(1),
3979 
    I1 => HRDATA(11),
3980 
    I2 => HRDATA(27),
3981 
    O => n_ahbso_hrdata(11));
3982 
  II_hrdata_0HAKL10HAKR: LUT3
3983 
  generic map(
3984 
    INIT => X"E4"
3985 
  )
3986 
  port map (
3987 
    I0 => D16MUX(1),
3988 
    I1 => HRDATA(10),
3989 
    I2 => HRDATA(26),
3990 
    O => n_ahbso_hrdata(10));
3991 
  II_hrdata_0HAKL9HAKR: LUT3
3992 
  generic map(
3993 
    INIT => X"E4"
3994 
  )
3995 
  port map (
3996 
    I0 => D16MUX(1),
3997 
    I1 => HRDATA(9),
3998 
    I2 => HRDATA(25),
3999 
    O => n_ahbso_hrdata(9));
4000 
  II_hrdata_0HAKL8HAKR: LUT3
4001 
  generic map(
4002 
    INIT => X"E4"
4003 
  )
4004 
  port map (
4005 
    I0 => D16MUX(1),
4006 
    I1 => HRDATA(8),
4007 
    I2 => HRDATA(24),
4008 
    O => n_ahbso_hrdata(8));
4009 
  II_hrdata_0HAKL7HAKR: LUT3
4010 
  generic map(
4011 
    INIT => X"E4"
4012 
  )
4013 
  port map (
4014 
    I0 => D16MUX(1),
4015 
    I1 => HRDATA(7),
4016 
    I2 => HRDATA(23),
4017 
    O => n_ahbso_hrdata(7));
4018 
  II_hrdata_0HAKL6HAKR: LUT3
4019 
  generic map(
4020 
    INIT => X"E4"
4021 
  )
4022 
  port map (
4023 
    I0 => D16MUX(1),
4024 
    I1 => HRDATA(6),
4025 
    I2 => HRDATA(22),
4026 
    O => n_ahbso_hrdata(6));
4027 
  II_hrdata_0HAKL5HAKR: LUT3
4028 
  generic map(
4029 
    INIT => X"E4"
4030 
  )
4031 
  port map (
4032 
    I0 => D16MUX(1),
4033 
    I1 => HRDATA(5),
4034 
    I2 => HRDATA(21),
4035 
    O => n_ahbso_hrdata(5));
4036 
  II_hrdata_0HAKL4HAKR: LUT3
4037 
  generic map(
4038 
    INIT => X"E4"
4039 
  )
4040 
  port map (
4041 
    I0 => D16MUX(1),
4042 
    I1 => HRDATA(4),
4043 
    I2 => HRDATA(20),
4044 
    O => n_ahbso_hrdata(4));
4045 
  II_hrdata_0HAKL3HAKR: LUT3
4046 
  generic map(
4047 
    INIT => X"E4"
4048 
  )
4049 
  port map (
4050 
    I0 => D16MUX(1),
4051 
    I1 => HRDATA(3),
4052 
    I2 => HRDATA(19),
4053 
    O => n_ahbso_hrdata(3));
4054 
  II_hrdata_0HAKL2HAKR: LUT3
4055 
  generic map(
4056 
    INIT => X"E4"
4057 
  )
4058 
  port map (
4059 
    I0 => D16MUX(1),
4060 
    I1 => HRDATA(2),
4061 
    I2 => HRDATA(18),
4062 
    O => n_ahbso_hrdata(2));
4063 
  II_hrdata_0HAKL1HAKR: LUT3
4064 
  generic map(
4065 
    INIT => X"E4"
4066 
  )
4067 
  port map (
4068 
    I0 => D16MUX(1),
4069 
    I1 => HRDATA(1),
4070 
    I2 => HRDATA(17),
4071 
    O => n_ahbso_hrdata(1));
4072 
  II_hrdata_0HAKL0HAKR: LUT3
4073 
  generic map(
4074 
    INIT => X"E4"
4075 
  )
4076 
  port map (
4077 
    I0 => D16MUX(1),
4078 
    I1 => HRDATA(0),
4079 
    I2 => HRDATA(16),
4080 
    O => n_ahbso_hrdata(0));
4081 
  II_ctrl_v_bdrive_1_iv_0_a0_0: LUT2
4082 
  generic map(
4083 
    INIT => X"4"
4084 
  )
4085 
  port map (
4086 
    I0 => PRSTATE_1_INT_28,
4087 
    I1 => SETBDRIVE,
4088 
    O => BDRIVE_1_IV_0_A4_0);
4089 
  II_ctrl_hwrite6: LUT2
4090 
  generic map(
4091 
    INIT => X"4"
4092 
  )
4093 
  port map (
4094 
    I0 => CHANGE_INT_69,
4095 
    I1 => PRHREADY_INT_48,
4096 
    O => N_662_INT_60);
4097 
  II_ctrl_regsd24: LUT2
4098 
  generic map(
4099 
    INIT => X"1"
4100 
  )
4101 
  port map (
4102 
    I0 => n_apbi_paddr(2),
4103 
    I1 => n_apbi_paddr(3),
4104 
    O => N_APBO_PRDATA_28_INT_11);
4105 
  II_ctrl_bus16en: LUT2
4106 
  generic map(
4107 
    INIT => X"2"
4108 
  )
4109 
  port map (
4110 
    I0 => ROMWIDTH(0),
4111 
    I1 => ROMWIDTH(1),
4112 
    O => BUS16EN_INT_72);
4113 
  II_ctrl_v_ssrstate23_1: LUT2
4114 
  generic map(
4115 
    INIT => X"1"
4116 
  )
4117 
  port map (
4118 
    I0 => WS_1_INT_17,
4119 
    I1 => WS_2_INT_18,
4120 
    O => SSRSTATE23_1);
4121 
  II_ctrl_un1_ahbsi: LUT2
4122 
  generic map(
4123 
    INIT => X"1"
4124 
  )
4125 
  port map (
4126 
    I0 => n_ahbsi_htrans(0),
4127 
    I1 => n_ahbsi_htrans(1),
4128 
    O => UN1_AHBSI_INT_68);
4129 
  II_un1_r_ssrstate_2: LUT2
4130 
  generic map(
4131 
    INIT => X"1"
4132 
  )
4133 
  port map (
4134 
    I0 => SSRSTATE_0_INT_20,
4135 
    I1 => SSRSTATE_3_INT_23,
4136 
    O => SSRSTATE_2_I_INT_55);
4137 
  II_ctrl_un17_bus16en: LUT2
4138 
  generic map(
4139 
    INIT => X"2"
4140 
  )
4141 
  port map (
4142 
    I0 => SIZE_0_INT_25,
4143 
    I1 => SIZE_1_INT_26,
4144 
    O => UN17_BUS16EN);
4145 
  II_un1_r_ssrstate_1: LUT2
4146 
  generic map(
4147 
    INIT => X"1"
4148 
  )
4149 
  port map (
4150 
    I0 => SSRSTATE_2_INT_22,
4151 
    I1 => SSRSTATE_4_INT_24,
4152 
    O => N_668);
4153 
  II_r_haddrHAKL1HAKR: FDSE port map (
4154 
      Q => N_SRO_ADDRESS_1_INT_37,
4155 
      D => n_ahbsi_haddr(1),
4156 
      C => clk,
4157 
      S => PRHREADY_0_SQMUXA,
4158 
      CE => HMBSEL_0_SQMUXA);
4159 
  II_r_prstateHAKL5HAKR: FDS port map (
4160 
      Q => PRSTATE_5_INT_32,
4161 
      D => PRSTATES_I,
4162 
      C => clk,
4163 
      S => RST_I);
4164 
  II_r_prstateHAKL4HAKR: FDS port map (
4165 
      Q => PRSTATE_4_INT_31,
4166 
      D => N_342,
4167 
      C => clk,
4168 
      S => N_341);
4169 
  II_r_prstateHAKL3HAKR: FDR port map (
4170 
      Q => PRSTATE_3_INT_30,
4171 
      D => PRSTATEC,
4172 
      C => clk,
4173 
      R => RST_I);
4174 
  II_r_prstateHAKL2HAKR: FDR port map (
4175 
      Q => PRSTATE_2_INT_29,
4176 
      D => PRSTATEC_0,
4177 
      C => clk,
4178 
      R => RST_I);
4179 
  II_r_prstateHAKL1HAKR: FDR port map (
4180 
      Q => PRSTATE_1_INT_28,
4181 
      D => N_337_I,
4182 
      C => clk,
4183 
      R => RST_I);
4184 
  II_r_prstateHAKL0HAKR: FDR port map (
4185 
      Q => PRSTATE_0_INT_27,
4186 
      D => PRSTATEC_1,
4187 
      C => clk,
4188 
      R => RST_I);
4189 
  II_r_ssrstateHAKL1HAKR: FDR port map (
4190 
      Q => SSRSTATE_1_INT_21,
4191 
      D => ssrstatec,
4192 
      C => clk,
4193 
      R => RST_I);
4194 
  II_r_ssrstateHAKL0HAKR: FDR port map (
4195 
      Q => SSRSTATE_0_INT_20,
4196 
      D => SSRSTATEC_0,
4197 
      C => clk,
4198 
      R => RST_I);
4199 
  II_rbdriveHAKL28HAKR: FDR port map (
4200 
      Q => n_sro_vbdrive(28),
4201 
      D => RBDRIVEC,
4202 
      C => clk,
4203 
      R => BDRIVE_1_IV_0_A1);
4204 
  II_rbdriveHAKL29HAKR: FDR port map (
4205 
      Q => n_sro_vbdrive(29),
4206 
      D => RBDRIVEC,
4207 
      C => clk,
4208 
      R => BDRIVE_1_IV_0_A1);
4209 
  II_rbdriveHAKL30HAKR: FDR port map (
4210 
      Q => n_sro_vbdrive(30),
4211 
      D => RBDRIVEC,
4212 
      C => clk,
4213 
      R => BDRIVE_1_IV_0_A1);
4214 
  II_rbdriveHAKL31HAKR: FDR port map (
4215 
      Q => n_sro_vbdrive(31),
4216 
      D => RBDRIVEC,
4217 
      C => clk,
4218 
      R => BDRIVE_1_IV_0_A1);
4219 
  II_rbdriveHAKL13HAKR: FDR port map (
4220 
      Q => n_sro_vbdrive(13),
4221 
      D => RBDRIVEC,
4222 
      C => clk,
4223 
      R => BDRIVE_1_IV_0_A1);
4224 
  II_rbdriveHAKL14HAKR: FDR port map (
4225 
      Q => n_sro_vbdrive(14),
4226 
      D => RBDRIVEC,
4227 
      C => clk,
4228 
      R => BDRIVE_1_IV_0_A1);
4229 
  II_rbdriveHAKL15HAKR: FDR port map (
4230 
      Q => n_sro_vbdrive(15),
4231 
      D => RBDRIVEC,
4232 
      C => clk,
4233 
      R => BDRIVE_1_IV_0_A1);
4234 
  II_rbdriveHAKL16HAKR: FDR port map (
4235 
      Q => n_sro_vbdrive(16),
4236 
      D => RBDRIVEC,
4237 
      C => clk,
4238 
      R => BDRIVE_1_IV_0_A1);
4239 
  II_rbdriveHAKL17HAKR: FDR port map (
4240 
      Q => n_sro_vbdrive(17),
4241 
      D => RBDRIVEC,
4242 
      C => clk,
4243 
      R => BDRIVE_1_IV_0_A1);
4244 
  II_rbdriveHAKL18HAKR: FDR port map (
4245 
      Q => n_sro_vbdrive(18),
4246 
      D => RBDRIVEC,
4247 
      C => clk,
4248 
      R => BDRIVE_1_IV_0_A1);
4249 
  II_rbdriveHAKL19HAKR: FDR port map (
4250 
      Q => n_sro_vbdrive(19),
4251 
      D => RBDRIVEC,
4252 
      C => clk,
4253 
      R => BDRIVE_1_IV_0_A1);
4254 
  II_rbdriveHAKL20HAKR: FDR port map (
4255 
      Q => n_sro_vbdrive(20),
4256 
      D => RBDRIVEC,
4257 
      C => clk,
4258 
      R => BDRIVE_1_IV_0_A1);
4259 
  II_rbdriveHAKL21HAKR: FDR port map (
4260 
      Q => n_sro_vbdrive(21),
4261 
      D => RBDRIVEC,
4262 
      C => clk,
4263 
      R => BDRIVE_1_IV_0_A1);
4264 
  II_rbdriveHAKL22HAKR: FDR port map (
4265 
      Q => n_sro_vbdrive(22),
4266 
      D => RBDRIVEC,
4267 
      C => clk,
4268 
      R => BDRIVE_1_IV_0_A1);
4269 
  II_rbdriveHAKL23HAKR: FDR port map (
4270 
      Q => n_sro_vbdrive(23),
4271 
      D => RBDRIVEC,
4272 
      C => clk,
4273 
      R => BDRIVE_1_IV_0_A1);
4274 
  II_rbdriveHAKL24HAKR: FDR port map (
4275 
      Q => n_sro_vbdrive(24),
4276 
      D => RBDRIVEC,
4277 
      C => clk,
4278 
      R => BDRIVE_1_IV_0_A1);
4279 
  II_rbdriveHAKL25HAKR: FDR port map (
4280 
      Q => n_sro_vbdrive(25),
4281 
      D => RBDRIVEC,
4282 
      C => clk,
4283 
      R => BDRIVE_1_IV_0_A1);
4284 
  II_rbdriveHAKL26HAKR: FDR port map (
4285 
      Q => n_sro_vbdrive(26),
4286 
      D => RBDRIVEC,
4287 
      C => clk,
4288 
      R => BDRIVE_1_IV_0_A1);
4289 
  II_rbdriveHAKL27HAKR: FDR port map (
4290 
      Q => n_sro_vbdrive(27),
4291 
      D => RBDRIVEC,
4292 
      C => clk,
4293 
      R => BDRIVE_1_IV_0_A1);
4294 
  II_rbdriveHAKL0HAKR: FDR port map (
4295 
      Q => n_sro_vbdrive(0),
4296 
      D => RBDRIVEC_18,
4297 
      C => clk,
4298 
      R => BDRIVE_1_IV_0_A1);
4299 
  II_rbdriveHAKL1HAKR: FDR port map (
4300 
      Q => n_sro_vbdrive(1),
4301 
      D => RBDRIVEC,
4302 
      C => clk,
4303 
      R => BDRIVE_1_IV_0_A1);
4304 
  II_rbdriveHAKL2HAKR: FDR port map (
4305 
      Q => n_sro_vbdrive(2),
4306 
      D => RBDRIVEC,
4307 
      C => clk,
4308 
      R => BDRIVE_1_IV_0_A1);
4309 
  II_rbdriveHAKL3HAKR: FDR port map (
4310 
      Q => n_sro_vbdrive(3),
4311 
      D => RBDRIVEC,
4312 
      C => clk,
4313 
      R => BDRIVE_1_IV_0_A1);
4314 
  II_rbdriveHAKL4HAKR: FDR port map (
4315 
      Q => n_sro_vbdrive(4),
4316 
      D => RBDRIVEC,
4317 
      C => clk,
4318 
      R => BDRIVE_1_IV_0_A1);
4319 
  II_rbdriveHAKL5HAKR: FDR port map (
4320 
      Q => n_sro_vbdrive(5),
4321 
      D => RBDRIVEC,
4322 
      C => clk,
4323 
      R => BDRIVE_1_IV_0_A1);
4324 
  II_rbdriveHAKL6HAKR: FDR port map (
4325 
      Q => n_sro_vbdrive(6),
4326 
      D => RBDRIVEC,
4327 
      C => clk,
4328 
      R => BDRIVE_1_IV_0_A1);
4329 
  II_rbdriveHAKL7HAKR: FDR port map (
4330 
      Q => n_sro_vbdrive(7),
4331 
      D => RBDRIVEC,
4332 
      C => clk,
4333 
      R => BDRIVE_1_IV_0_A1);
4334 
  II_rbdriveHAKL8HAKR: FDR port map (
4335 
      Q => n_sro_vbdrive(8),
4336 
      D => RBDRIVEC,
4337 
      C => clk,
4338 
      R => BDRIVE_1_IV_0_A1);
4339 
  II_rbdriveHAKL9HAKR: FDR port map (
4340 
      Q => n_sro_vbdrive(9),
4341 
      D => RBDRIVEC,
4342 
      C => clk,
4343 
      R => BDRIVE_1_IV_0_A1);
4344 
  II_rbdriveHAKL10HAKR: FDR port map (
4345 
      Q => n_sro_vbdrive(10),
4346 
      D => RBDRIVEC,
4347 
      C => clk,
4348 
      R => BDRIVE_1_IV_0_A1);
4349 
  II_rbdriveHAKL11HAKR: FDR port map (
4350 
      Q => n_sro_vbdrive(11),
4351 
      D => RBDRIVEC,
4352 
      C => clk,
4353 
      R => BDRIVE_1_IV_0_A1);
4354 
  II_rbdriveHAKL12HAKR: FDR port map (
4355 
      Q => n_sro_vbdrive(12),
4356 
      D => RBDRIVEC,
4357 
      C => clk,
4358 
      R => BDRIVE_1_IV_0_A1);
4359 
  II_r_d16muxHAKL0HAKR: FDR port map (
4360 
      Q => D16MUX(0),
4361 
      D => D16MUXC,
4362 
      C => clk,
4363 
      R => WS_2_INT_18);
4364 
  II_r_d16muxHAKL1HAKR: FDR port map (
4365 
      Q => D16MUX(1),
4366 
      D => D16MUXC_0,
4367 
      C => clk,
4368 
      R => PRSTATE_2_INT_29);
4369 
  II_r_acount_sHAKL9HAKR: XORCY port map (
4370 
      LI => ACOUNT_QXU(9),
4371 
      CI => ACOUNT_CRY(8),
4372 
      O => ACOUNT_S(9));
4373 
  II_r_acount_sHAKL8HAKR: XORCY port map (
4374 
      LI => ACOUNT_QXU(8),
4375 
      CI => ACOUNT_CRY(7),
4376 
      O => ACOUNT_S(8));
4377 
  II_r_acount_cryHAKL8HAKR: MUXCY_L port map (
4378 
      DI => NN_10,
4379 
      CI => ACOUNT_CRY(7),
4380 
      S => ACOUNT_QXU(8),
4381 
      LO => ACOUNT_CRY(8));
4382 
  II_r_acount_sHAKL7HAKR: XORCY port map (
4383 
      LI => ACOUNT_QXU(7),
4384 
      CI => ACOUNT_CRY(6),
4385 
      O => ACOUNT_S(7));
4386 
  II_r_acount_cryHAKL7HAKR: MUXCY_L port map (
4387 
      DI => NN_10,
4388 
      CI => ACOUNT_CRY(6),
4389 
      S => ACOUNT_QXU(7),
4390 
      LO => ACOUNT_CRY(7));
4391 
  II_r_acount_sHAKL6HAKR: XORCY port map (
4392 
      LI => ACOUNT_QXU(6),
4393 
      CI => ACOUNT_CRY(5),
4394 
      O => ACOUNT_S(6));
4395 
  II_r_acount_cryHAKL6HAKR: MUXCY_L port map (
4396 
      DI => NN_10,
4397 
      CI => ACOUNT_CRY(5),
4398 
      S => ACOUNT_QXU(6),
4399 
      LO => ACOUNT_CRY(6));
4400 
  II_r_acount_sHAKL5HAKR: XORCY port map (
4401 
      LI => ACOUNT_QXU(5),
4402 
      CI => ACOUNT_CRY(4),
4403 
      O => ACOUNT_S(5));
4404 
  II_r_acount_cryHAKL5HAKR: MUXCY_L port map (
4405 
      DI => NN_10,
4406 
      CI => ACOUNT_CRY(4),
4407 
      S => ACOUNT_QXU(5),
4408 
      LO => ACOUNT_CRY(5));
4409 
  II_r_acount_sHAKL4HAKR: XORCY port map (
4410 
      LI => ACOUNT_QXU(4),
4411 
      CI => ACOUNT_CRY(3),
4412 
      O => ACOUNT_S(4));
4413 
  II_r_acount_cryHAKL4HAKR: MUXCY_L port map (
4414 
      DI => NN_10,
4415 
      CI => ACOUNT_CRY(3),
4416 
      S => ACOUNT_QXU(4),
4417 
      LO => ACOUNT_CRY(4));
4418 
  II_r_acount_sHAKL3HAKR: XORCY port map (
4419 
      LI => ACOUNT_QXU(3),
4420 
      CI => ACOUNT_CRY(2),
4421 
      O => ACOUNT_S(3));
4422 
  II_r_acount_cryHAKL3HAKR: MUXCY_L port map (
4423 
      DI => NN_10,
4424 
      CI => ACOUNT_CRY(2),
4425 
      S => ACOUNT_QXU(3),
4426 
      LO => ACOUNT_CRY(3));
4427 
  II_r_acount_sHAKL2HAKR: XORCY port map (
4428 
      LI => ACOUNT_QXU(2),
4429 
      CI => ACOUNT_CRY(1),
4430 
      O => ACOUNT_S(2));
4431 
  II_r_acount_cryHAKL2HAKR: MUXCY_L port map (
4432 
      DI => NN_10,
4433 
      CI => ACOUNT_CRY(1),
4434 
      S => ACOUNT_QXU(2),
4435 
      LO => ACOUNT_CRY(2));
4436 
  II_r_acount_sHAKL1HAKR: XORCY port map (
4437 
      LI => ACOUNT_QXU(1),
4438 
      CI => N_SRO_ADDRESS_2_INT_38,
4439 
      O => ACOUNT_S(1));
4440 
  II_r_acount_cryHAKL1HAKR: MUXCY_L port map (
4441 
      DI => NN_10,
4442 
      CI => N_SRO_ADDRESS_2_INT_38,
4443 
      S => ACOUNT_QXU(1),
4444 
      LO => ACOUNT_CRY(1));
4445 
  II_r_hsel: FDRE port map (
4446 
      Q => HSEL_INT_58,
4447 
      D => hsel_4,
4448 
      C => clk,
4449 
      R => RST_I,
4450 
      CE => n_ahbsi_hready);
4451 
  II_r_mcfg1_ioen: FDRE port map (
4452 
      Q => IOEN,
4453 
      D => IOEN_1,
4454 
      C => clk,
4455 
      R => RST_I,
4456 
      CE => BEXCEN_1_SQMUXA_I);
4457 
  II_r_mcfg1_romwrite: FDRE port map (
4458 
      Q => ROMWRITE,
4459 
      D => ROMWRITE_1,
4460 
      C => clk,
4461 
      R => RST_I,
4462 
      CE => BEXCEN_1_SQMUXA_I);
4463 
  II_r_mcfg1_iowsHAKL3HAKR: FDRE port map (
4464 
      Q => IOWS_3_INT_6,
4465 
      D => IOWS_1(3),
4466 
      C => clk,
4467 
      R => RST_I,
4468 
      CE => BEXCEN_1_SQMUXA_I);
4469 
  II_r_mcfg1_iowsHAKL2HAKR: FDRE port map (
4470 
      Q => IOWS(2),
4471 
      D => IOWS_1(2),
4472 
      C => clk,
4473 
      R => RST_I,
4474 
      CE => BEXCEN_1_SQMUXA_I);
4475 
  II_r_mcfg1_iowsHAKL1HAKR: FDRE port map (
4476 
      Q => IOWS(1),
4477 
      D => IOWS_1(1),
4478 
      C => clk,
4479 
      R => RST_I,
4480 
      CE => BEXCEN_1_SQMUXA_I);
4481 
  II_r_mcfg1_iowsHAKL0HAKR: FDRE port map (
4482 
      Q => IOWS_0_INT_5,
4483 
      D => IOWS_1(0),
4484 
      C => clk,
4485 
      R => RST_I,
4486 
      CE => BEXCEN_1_SQMUXA_I);
4487 
  II_r_mcfg1_romrwsHAKL3HAKR: FDSE port map (
4488 
      Q => ROMRWS_3_INT_10,
4489 
      D => N_627_I,
4490 
      C => clk,
4491 
      S => RST_I,
4492 
      CE => BEXCEN_1_SQMUXA_I);
4493 
  II_r_mcfg1_romrwsHAKL2HAKR: FDSE port map (
4494 
      Q => ROMRWS(2),
4495 
      D => N_628_I,
4496 
      C => clk,
4497 
      S => RST_I,
4498 
      CE => BEXCEN_1_SQMUXA_I);
4499 
  II_r_mcfg1_romrwsHAKL1HAKR: FDSE port map (
4500 
      Q => ROMRWS(1),
4501 
      D => N_629_I,
4502 
      C => clk,
4503 
      S => RST_I,
4504 
      CE => BEXCEN_1_SQMUXA_I);
4505 
  II_r_mcfg1_romrwsHAKL0HAKR: FDSE port map (
4506 
      Q => ROMRWS_0_INT_9,
4507 
      D => N_630_I,
4508 
      C => clk,
4509 
      S => RST_I,
4510 
      CE => BEXCEN_1_SQMUXA_I);
4511 
  II_r_mcfg1_romwwsHAKL3HAKR: FDSE port map (
4512 
      Q => ROMWWS_3_INT_8,
4513 
      D => N_623_I,
4514 
      C => clk,
4515 
      S => RST_I,
4516 
      CE => BEXCEN_1_SQMUXA_I);
4517 
  II_r_mcfg1_romwwsHAKL2HAKR: FDSE port map (
4518 
      Q => ROMWWS(2),
4519 
      D => N_624_I,
4520 
      C => clk,
4521 
      S => RST_I,
4522 
      CE => BEXCEN_1_SQMUXA_I);
4523 
  II_r_mcfg1_romwwsHAKL1HAKR: FDSE port map (
4524 
      Q => ROMWWS(1),
4525 
      D => N_625_I,
4526 
      C => clk,
4527 
      S => RST_I,
4528 
      CE => BEXCEN_1_SQMUXA_I);
4529 
  II_r_mcfg1_romwwsHAKL0HAKR: FDSE port map (
4530 
      Q => ROMWWS_0_INT_7,
4531 
      D => N_626_I,
4532 
      C => clk,
4533 
      S => RST_I,
4534 
      CE => BEXCEN_1_SQMUXA_I);
4535 
  II_r_writen: FDSE port map (
4536 
      Q => n_sro_writen,
4537 
      D => N_635_I,
4538 
      C => clk,
4539 
      S => RST_I,
4540 
      CE => WRITEN_2_SQMUXA);
4541 
  II_r_loadcount: FDS port map (
4542 
      Q => loadcount,
4543 
      D => loadcount_7,
4544 
      C => clk,
4545 
      S => RST_I);
4546 
  II_r_setbdrive: FDRE port map (
4547 
      Q => SETBDRIVE,
4548 
      D => SSRSTATE_1_INT_21,
4549 
      C => clk,
4550 
      R => RST_I,
4551 
      CE => SSRSTATE_3);
4552 
  II_r_ssrhready: FDS port map (
4553 
      Q => SSRHREADY_INT_51,
4554 
      D => ssrhready_8,
4555 
      C => clk,
4556 
      S => RST_I);
4557 
  II_r_prhready: FDS port map (
4558 
      Q => PRHREADY_INT_48,
4559 
      D => PRHREADY_6,
4560 
      C => clk,
4561 
      S => RST_I);
4562 
  II_r_romsn: FDSE port map (
4563 
      Q => N_SRO_ROMSN_0_INT_12,
4564 
      D => ROMSN_1,
4565 
      C => clk,
4566 
      S => RST_I,
4567 
      CE => N_599_I);
4568 
  II_r_hready: FDS port map (
4569 
      Q => n_ahbso_hready,
4570 
      D => hready_2,
4571 
      C => clk,
4572 
      S => RST_I);
4573 
  II_GND: GND port map (
4574 
      G => NN_10);
4575 
  II_VCC: VCC port map (
4576 
      P => NN_11);
4577 
  iows_0 <= IOWS_0_INT_5;
4578 
  iows_3 <= IOWS_3_INT_6;
4579 
  romwws_0 <= ROMWWS_0_INT_7;
4580 
  romwws_3 <= ROMWWS_3_INT_8;
4581 
  romrws_0 <= ROMRWS_0_INT_9;
4582 
  romrws_3 <= ROMRWS_3_INT_10;
4583 
  n_apbo_prdata_28 <= N_APBO_PRDATA_28_INT_11;
4584 
  n_sro_romsn(0) <= N_SRO_ROMSN_0_INT_12;
4585 
  prstate_fast(2) <= PRSTATE_FAST_2_INT_13;
4586 
  hmbsel_4(1) <= HMBSEL_4_1_INT_14;
4587 
  n_sro_bdrive(3) <= N_SRO_BDRIVE_3_INT_15;
4588 
  ws(0) <= WS_0_INT_16;
4589 
  ws(1) <= WS_1_INT_17;
4590 
  ws(2) <= WS_2_INT_18;
4591 
  ws(3) <= WS_3_INT_19;
4592 
  ssrstate(0) <= SSRSTATE_0_INT_20;
4593 
  ssrstate(1) <= SSRSTATE_1_INT_21;
4594 
  ssrstate(2) <= SSRSTATE_2_INT_22;
4595 
  ssrstate(3) <= SSRSTATE_3_INT_23;
4596 
  ssrstate(4) <= SSRSTATE_4_INT_24;
4597 
  size(0) <= SIZE_0_INT_25;
4598 
  size(1) <= SIZE_1_INT_26;
4599 
  prstate(0) <= PRSTATE_0_INT_27;
4600 
  prstate(1) <= PRSTATE_1_INT_28;
4601 
  prstate(2) <= PRSTATE_2_INT_29;
4602 
  prstate(3) <= PRSTATE_3_INT_30;
4603 
  prstate(4) <= PRSTATE_4_INT_31;
4604 
  prstate(5) <= PRSTATE_5_INT_32;
4605 
  hmbsel(0) <= HMBSEL_0_INT_33;
4606 
  hmbsel(1) <= HMBSEL_1_INT_34;
4607 
  hmbsel(2) <= HMBSEL_2_INT_35;
4608 
  n_sro_address(0) <= N_SRO_ADDRESS_0_INT_36;
4609 
  n_sro_address(1) <= N_SRO_ADDRESS_1_INT_37;
4610 
  n_sro_address(2) <= N_SRO_ADDRESS_2_INT_38;
4611 
  n_sro_address(3) <= N_SRO_ADDRESS_3_INT_39;
4612 
  n_sro_address(4) <= N_SRO_ADDRESS_4_INT_40;
4613 
  n_sro_address(5) <= N_SRO_ADDRESS_5_INT_41;
4614 
  n_sro_address(6) <= N_SRO_ADDRESS_6_INT_42;
4615 
  n_sro_address(7) <= N_SRO_ADDRESS_7_INT_43;
4616 
  n_sro_address(8) <= N_SRO_ADDRESS_8_INT_44;
4617 
  n_sro_address(9) <= N_SRO_ADDRESS_9_INT_45;
4618 
  n_sro_address(10) <= N_SRO_ADDRESS_10_INT_46;
4619 
  n_sro_address(11) <= N_SRO_ADDRESS_11_INT_47;
4620 
  prhready <= PRHREADY_INT_48;
4621 
  ws_0_sqmuxa_c <= WS_0_SQMUXA_C_INT_49;
4622 
  ws_0_sqmuxa_0_c <= WS_0_SQMUXA_0_C_INT_50;
4623 
  ssrhready <= SSRHREADY_INT_51;
4624 
  ws_1_sqmuxa <= WS_1_SQMUXA_INT_52;
4625 
  ws_3_sqmuxa_1 <= WS_3_SQMUXA_1_INT_53;
4626 
  ws_2_sqmuxa_3_0_2 <= WS_2_SQMUXA_3_0_2_INT_54;
4627 
  ssrstate_2_i <= SSRSTATE_2_I_INT_55;
4628 
  ws_2_sqmuxa_3_d <= WS_2_SQMUXA_3_D_INT_56;
4629 
  ws_0_sqmuxa_1 <= WS_0_SQMUXA_1_INT_57;
4630 
  hsel <= HSEL_INT_58;
4631 
  prstate_2_rep1 <= PRSTATE_2_REP1_INT_59;
4632 
  N_662 <= N_662_INT_60;
4633 
  ssrstate_6_sqmuxa <= SSRSTATE_6_SQMUXA_INT_61;
4634 
  ssrhready_2_sqmuxa_0_0 <= SSRHREADY_2_SQMUXA_0_0_INT_62;
4635 
  change_1_sqmuxa_N_3 <= CHANGE_1_SQMUXA_N_3_INT_63;
4636 
  ssrstate6_xx_mm_m3 <= SSRSTATE6_XX_MM_M3_INT_64;
4637 
  ssrstate6_1_d_0_L1 <= SSRSTATE6_1_D_0_L1_INT_65;
4638 
  N_656 <= N_656_INT_66;
4639 
  hsel_5 <= HSEL_5_INT_67;
4640 
  un1_ahbsi <= UN1_AHBSI_INT_68;
4641 
  change <= CHANGE_INT_69;
4642 
  n_sro_iosn <= N_SRO_IOSN_INT_70;
4643 
  N_371 <= N_371_INT_71;
4644 
  bus16en <= BUS16EN_INT_72;
4645 
  d16muxc_0_4 <= D16MUXC_0_4_INT_73;
4646 
end beh;
4647 
 
4648 
--
4649 
 
4650 
library ieee;
4651 
use ieee.std_logic_1164.all;
4652 
library unisim;
4653 
use unisim.vcomponents.all;
4654 
 
4655 
architecture beh of ssrctrl_unisim is
4656 
  signal WRP_R_HMBSEL : std_logic_vector (2 downto 0);
4657 
  signal WRP_R_WS : std_logic_vector (3 downto 0);
4658 
  signal WRP_R_SIZE : std_logic_vector (1 downto 0);
4659 
  signal WRP_R_PRSTATE : std_logic_vector (5 downto 0);
4660 
  signal WRP_R_SSRSTATE : std_logic_vector (4 downto 0);
4661 
  signal WRP_R_MCFG1_ROMRWS : std_logic_vector (3 downto 0);
4662 
  signal WRP_R_MCFG1_ROMWWS : std_logic_vector (3 downto 0);
4663 
  signal WRP_R_MCFG1_IOWS : std_logic_vector (3 downto 0);
4664 
  signal WRP_CTRL_V_SSRSTATE_1 : std_logic_vector (4 to 4);
4665 
  signal WRP_CTRL_V_SSRSTATE_1_M1 : std_logic_vector (4 downto 3);
4666 
  signal WRP_CTRL_V_WS_1 : std_logic_vector (3 downto 0);
4667 
  signal WRP_CTRL_V_HMBSEL_4 : std_logic_vector (1 to 1);
4668 
  signal WRP_NONAME_CNST : std_logic_vector (0 to 0);
4669 
  signal WRP_CTRL_HSIZE_1 : std_logic_vector (1 to 1);
4670 
  signal WRP_HADDR : std_logic_vector (1 to 1);
4671 
  signal WRP_UN1_V_HSEL_1 : std_logic_vector (0 to 0);
4672 
  signal WRP_CTRL_V_BWN_1_0_O3 : std_logic_vector (0 to 0);
4673 
  signal WRP_V_PRSTATE_1_I_O4_S : std_logic_vector (2 to 2);
4674 
  signal WRP_R_PRSTATE_FAST : std_logic_vector (2 to 2);
4675 
  signal N_SRO_ADDRESS_0_INT_172 : std_logic ;
4676 
  signal N_SRO_ADDRESS_1_INT_173 : std_logic ;
4677 
  signal N_SRO_IOSN_INT_259 : std_logic ;
4678 
  signal N_SRO_ROMSN_0_INT_260 : std_logic ;
4679 
  signal WRP_R_PRHREADY : std_logic ;
4680 
  signal WRP_R_CHANGE : std_logic ;
4681 
  signal WRP_CTRL_V_HSEL_5 : std_logic ;
4682 
  signal WRP_R_HSEL : std_logic ;
4683 
  signal WRP_CTRL_V_LOADCOUNT_7 : std_logic ;
4684 
  signal WRP_R_LOADCOUNT : std_logic ;
4685 
  signal WRP_CTRL_V_SSRHREADY_8 : std_logic ;
4686 
  signal WRP_R_SSRHREADY : std_logic ;
4687 
  signal WRP_CTRL_V_HREADY_2 : std_logic ;
4688 
  signal N_574_I : std_logic ;
4689 
  signal WRP_CTRL_BUS16EN : std_logic ;
4690 
  signal WRP_CTRL_V_HSEL_4 : std_logic ;
4691 
  signal WRP_CTRL_UN7_BUS16EN : std_logic ;
4692 
  signal WRP_V_D16MUX_0_SQMUXA : std_logic ;
4693 
  signal N_593 : std_logic ;
4694 
  signal N_597 : std_logic ;
4695 
  signal N_596 : std_logic ;
4696 
  signal WRP_V_SSRSTATE_2_SQMUXA_1 : std_logic ;
4697 
  signal WRP_V_SSRSTATE_6_SQMUXA : std_logic ;
4698 
  signal WRP_V_SSRSTATE_1_SQMUXA_1 : std_logic ;
4699 
  signal WRP_UN1_R_SSRSTATE_2_I : std_logic ;
4700 
  signal WRP_V_WS_0_SQMUXA_1 : std_logic ;
4701 
  signal WRP_V_BWN_0_SQMUXA_1 : std_logic ;
4702 
  signal WRP_V_WS_1_SQMUXA : std_logic ;
4703 
  signal N_646 : std_logic ;
4704 
  signal WRP_V_WS_3_SQMUXA_1 : std_logic ;
4705 
  signal N_662 : std_logic ;
4706 
  signal WRP_V_LOADCOUNT_1_SQMUXA : std_logic ;
4707 
  signal N_319_1 : std_logic ;
4708 
  signal WRP_CTRL_UN1_AHBSI : std_logic ;
4709 
  signal N_622 : std_logic ;
4710 
  signal WRP_UN1_V_SSRSTATE_2_SQMUXA_I : std_logic ;
4711 
  signal N_365 : std_logic ;
4712 
  signal N_371 : std_logic ;
4713 
  signal N_656 : std_logic ;
4714 
  signal WRP_UN1_V_CHANGE_1_SQMUXA_0 : std_logic ;
4715 
  signal G0_25 : std_logic ;
4716 
  signal WRP_CTRL_V_CHANGE_3_F0 : std_logic ;
4717 
  signal WRP_UN1_V_BWN_1_SQMUXA_2_D : std_logic ;
4718 
  signal WRP_CTRL_UN1_V_SSRSTATE17_1_XX_MM_N_4 : std_logic ;
4719 
  signal SSRSTATE17_2_0_M6_I_A3_A2 : std_logic ;
4720 
  signal SSRSTATE6_XX_MM_M3 : std_logic ;
4721 
  signal WRP_V_CHANGE_1_SQMUXA_N_3 : std_logic ;
4722 
  signal WRP_CTRL_V_CHANGE_3_F1_D_0_0 : std_logic ;
4723 
  signal WRP_V_WS_2_SQMUXA_3_D : std_logic ;
4724 
  signal WRP_V_WS_0_SQMUXA_C : std_logic ;
4725 
  signal WRP_V_WS_0_SQMUXA_0_C : std_logic ;
4726 
  signal G0_30 : std_logic ;
4727 
  signal D_M2_0_A2_0 : std_logic ;
4728 
  signal N_618_I : std_logic ;
4729 
  signal WRP_R_SSRSTATEC : std_logic ;
4730 
  signal WRP_R_D16MUXC_0_4 : std_logic ;
4731 
  signal WRP_V_WS_4_SQMUXA_0 : std_logic ;
4732 
  signal D_M1_E_0_0 : std_logic ;
4733 
  signal WRP_V_WS_2_SQMUXA_0 : std_logic ;
4734 
  signal WRP_V_SSRSTATE_1_SQMUXA_1_XX_MM_A1_0 : std_logic ;
4735 
  signal WRP_UN1_V_SSRSTATE17_2_0_M6_I_1 : std_logic ;
4736 
  signal WRP_V_SSRHREADY_2_SQMUXA_0_0 : std_logic ;
4737 
  signal WRP_V_WS_2_SQMUXA_3_0_2 : std_logic ;
4738 
  signal WRP_V_WS_2_SQMUXA_3_0_4 : std_logic ;
4739 
  signal WRP_UN1_V_BWN_1_SQMUXA_2_D_0_2 : std_logic ;
4740 
  signal WRP_UN1_V_SSRSTATE_1_SQMUXA_1_0_M3_0_1 : std_logic ;
4741 
  signal SSRSTATE6_1_D_0_L1 : std_logic ;
4742 
  signal HSEL_1_0_L3 : std_logic ;
4743 
  signal SSRHREADY_8_F0_L5 : std_logic ;
4744 
  signal SSRHREADY_8_F0_L8 : std_logic ;
4745 
  signal G0_I : std_logic ;
4746 
  signal N_5 : std_logic ;
4747 
  signal G0_23 : std_logic ;
4748 
  signal N_14 : std_logic ;
4749 
  signal N_19 : std_logic ;
4750 
  signal G0_34 : std_logic ;
4751 
  signal G0_29 : std_logic ;
4752 
  signal G0_28 : std_logic ;
4753 
  signal G0_31 : std_logic ;
4754 
  signal G2_1_0 : std_logic ;
4755 
  signal G0_44 : std_logic ;
4756 
  signal G0_I_M2_1 : std_logic ;
4757 
  signal G0_14 : std_logic ;
4758 
  signal G0_7_0 : std_logic ;
4759 
  signal G0_1_0 : std_logic ;
4760 
  signal G3 : std_logic ;
4761 
  signal N_4 : std_logic ;
4762 
  signal N_17 : std_logic ;
4763 
  signal G0_5_0 : std_logic ;
4764 
  signal G0_11 : std_logic ;
4765 
  signal G0_I_A3_0 : std_logic ;
4766 
  signal G0_51 : std_logic ;
4767 
  signal G0_8_1 : std_logic ;
4768 
  signal G0_56 : std_logic ;
4769 
  signal G0_I_M2_2 : std_logic ;
4770 
  signal N_9 : std_logic ;
4771 
  signal G0_8 : std_logic ;
4772 
  signal G0_I_M2_L1 : std_logic ;
4773 
  signal G0_54_L1 : std_logic ;
4774 
  signal G0_57_1 : std_logic ;
4775 
  signal G0_34_L1_0 : std_logic ;
4776 
  signal G0_34_L6 : std_logic ;
4777 
  signal G0_34_L10 : std_logic ;
4778 
  signal G0_55_L1 : std_logic ;
4779 
  signal G0_55_L5 : std_logic ;
4780 
  signal G0_55_L7 : std_logic ;
4781 
  signal G0_19_L1 : std_logic ;
4782 
  signal G0_52_X0 : std_logic ;
4783 
  signal G0_52_X1 : std_logic ;
4784 
  signal G0_50_X : std_logic ;
4785 
  signal WS_2_SQMUXA_3_0_X : std_logic ;
4786 
  signal D_M1_E_L1 : std_logic ;
4787 
  signal G0_57_1_L5 : std_logic ;
4788 
  signal G0_57_1_L7 : std_logic ;
4789 
  signal G0_55_L5_L1 : std_logic ;
4790 
  signal G0_55_L7_L1 : std_logic ;
4791 
  signal G0_36_L1 : std_logic ;
4792 
  signal G0_48_L1 : std_logic ;
4793 
  signal G0_34_L10_L1 : std_logic ;
4794 
  signal G0_34_L10_L3 : std_logic ;
4795 
  signal G0_57_1_L7_L4 : std_logic ;
4796 
  signal G0_57_1_L7_L6 : std_logic ;
4797 
  signal G0_57_1_L7_L8 : std_logic ;
4798 
  signal WRP_R_PRSTATE_2_REP1 : std_logic ;
4799 
  signal D_M1_E_L1_0 : std_logic ;
4800 
  signal D_M1_E_L3 : std_logic ;
4801 
  signal G0_I_M2_0_L1 : std_logic ;
4802 
  signal G0_I_M2_0_L3 : std_logic ;
4803 
  signal G0_I_M2_0_L5 : std_logic ;
4804 
  signal G3_1 : std_logic ;
4805 
  signal G0_0_L1 : std_logic ;
4806 
  signal G0_0_L3 : std_logic ;
4807 
  signal G0_0_L5 : std_logic ;
4808 
  signal G0_0_L7 : std_logic ;
4809 
  signal G0_0_L9 : std_logic ;
4810 
  signal G0_57_1_L7_L6_RN_0 : std_logic ;
4811 
  signal G0_57_1_L7_L6_SN : std_logic ;
4812 
  signal G0_55_L7_L1_RN_0 : std_logic ;
4813 
  signal G0_55_L7_L1_SN : std_logic ;
4814 
  signal G0_52X : std_logic ;
4815 
  signal G0_52X_0 : std_logic ;
4816 
  signal G2_0_1 : std_logic ;
4817 
  signal G0_46_L1 : std_logic ;
4818 
  signal G0_46_L3 : std_logic ;
4819 
  signal G0_46_L5 : std_logic ;
4820 
  signal G0_46_L7 : std_logic ;
4821 
  signal NN_1 : std_logic ;
4822 
  signal N_SRO_OEN_INT_245_INT_246_INT_247_INT_248_INT_249_INT_250_INT_251_INT_252_INT_268 : std_logic ;
4823 
  signal N_SRO_BDRIVE_3_INT_269_INT_270_INT_271_INT_272 : std_logic ;
4824 
  signal NN_2 : std_logic ;
4825 
  component ssrctrl_unisim_netlist
4826 
    port(
4827 
      n_sro_vbdrive : out std_logic_vector(31 downto 0);
4828 
      n_ahbso_hrdata : out std_logic_vector(31 downto 0);
4829 
      iows_0 : out std_logic;
4830 
      iows_3 : out std_logic;
4831 
      romwws_0 : out std_logic;
4832 
      romwws_3 : out std_logic;
4833 
      romrws_0 : out std_logic;
4834 
      romrws_3 : out std_logic;
4835 
      NoName_cnst : in std_logic_vector(0 downto 0);
4836 
      n_sri_bwidth : in std_logic_vector(1 downto 0);
4837 
      n_apbi_pwdata_19 : in std_logic;
4838 
      n_apbi_pwdata_11 : in std_logic;
4839 
      n_apbi_pwdata_9 : in std_logic;
4840 
      n_apbi_pwdata_8 : in std_logic;
4841 
      n_apbi_pwdata_23 : in std_logic;
4842 
      n_apbi_pwdata_22 : in std_logic;
4843 
      n_apbi_pwdata_21 : in std_logic;
4844 
      n_apbi_pwdata_20 : in std_logic;
4845 
      n_apbi_pwdata_3 : in std_logic;
4846 
      n_apbi_pwdata_2 : in std_logic;
4847 
      n_apbi_pwdata_1 : in std_logic;
4848 
      n_apbi_pwdata_0 : in std_logic;
4849 
      n_apbi_pwdata_7 : in std_logic;
4850 
      n_apbi_pwdata_6 : in std_logic;
4851 
      n_apbi_pwdata_5 : in std_logic;
4852 
      n_apbi_pwdata_4 : in std_logic;
4853 
      n_apbi_psel : in std_logic_vector(0 downto 0);
4854 
      n_apbi_paddr : in std_logic_vector(5 downto 2);
4855 
      n_apbo_prdata_0 : out std_logic;
4856 
      n_apbo_prdata_4 : out std_logic;
4857 
      n_apbo_prdata_20 : out std_logic;
4858 
      n_apbo_prdata_23 : out std_logic;
4859 
      n_apbo_prdata_22 : out std_logic;
4860 
      n_apbo_prdata_21 : out std_logic;
4861 
      n_apbo_prdata_19 : out std_logic;
4862 
      n_apbo_prdata_7 : out std_logic;
4863 
      n_apbo_prdata_6 : out std_logic;
4864 
      n_apbo_prdata_5 : out std_logic;
4865 
      n_apbo_prdata_3 : out std_logic;
4866 
      n_apbo_prdata_2 : out std_logic;
4867 
      n_apbo_prdata_1 : out std_logic;
4868 
      n_apbo_prdata_11 : out std_logic;
4869 
      n_apbo_prdata_9 : out std_logic;
4870 
      n_apbo_prdata_8 : out std_logic;
4871 
      n_apbo_prdata_28 : out std_logic;
4872 
      n_sro_romsn : out std_logic_vector(0 downto 0);
4873 
      n_ahbsi_hsel : in std_logic_vector(0 downto 0);
4874 
      prstate_fast : out std_logic_vector(2 downto 2);
4875 
      n_ahbsi_htrans : in std_logic_vector(1 downto 0);
4876 
      ssrstate_1_m1 : inout std_logic_vector(4 downto 3);
4877 
      hsel_1 : in std_logic_vector(0 downto 0);
4878 
      hmbsel_4 : out std_logic_vector(1 downto 1);
4879 
      n_sro_bdrive : out std_logic_vector(3 downto 3);
4880 
      ws_1_0 : in std_logic;
4881 
      ws_1_3 : in std_logic;
4882 
      ws : out std_logic_vector(3 downto 0);
4883 
      ssrstate_1_2 : in std_logic;
4884 
      n_ahbsi_haddr : in std_logic_vector(31 downto 0);
4885 
      n_ahbsi_hmbsel : in std_logic_vector(2 downto 0);
4886 
      n_sri_data : in std_logic_vector(31 downto 0);
4887 
      ssrstate : out std_logic_vector(4 downto 0);
4888 
      n_ahbsi_hwdata : in std_logic_vector(31 downto 0);
4889 
      n_ahbsi_hsize : in std_logic_vector(1 downto 0);
4890 
      size : out std_logic_vector(1 downto 0);
4891 
      n_sro_data : out std_logic_vector(31 downto 0);
4892 
      n_sro_ramsn : out std_logic_vector(0 downto 0);
4893 
      n_sro_wrn : out std_logic_vector(3 downto 0);
4894 
      haddr_0 : in std_logic;
4895 
      bwn_1_0_o3_0 : in std_logic;
4896 
      hsize_1 : in std_logic_vector(1 downto 1);
4897 
      prstate_1_i_o4_s : in std_logic_vector(2 downto 2);
4898 
      prstate : out std_logic_vector(5 downto 0);
4899 
      hmbsel : out std_logic_vector(2 downto 0);
4900 
      n_sro_address : out std_logic_vector(31 downto 0);
4901 
      hready_2 : in std_logic;
4902 
      n_ahbso_hready : out std_logic;
4903 
      ssrhready_8 : in std_logic;
4904 
      loadcount : out std_logic;
4905 
      n_sro_writen : out std_logic;
4906 
      ssrstatec : in std_logic;
4907 
      prhready : out std_logic;
4908 
      d_m2_0_a2_0 : in std_logic;
4909 
      ssrstate17_2_0_m6_i_a3_a2 : out std_logic;
4910 
      N_319_1 : out std_logic;
4911 
      ws_0_sqmuxa_c : out std_logic;
4912 
      N_365 : in std_logic;
4913 
      ws_0_sqmuxa_0_c : out std_logic;
4914 
      ws_2_sqmuxa_3_0_4 : out std_logic;
4915 
      change_1_sqmuxa_0 : in std_logic;
4916 
      d16mux_0_sqmuxa : in std_logic;
4917 
      ssrstate_2_sqmuxa_1 : in std_logic;
4918 
      un7_bus16en : in std_logic;
4919 
      N_646 : in std_logic;
4920 
      loadcount_1_sqmuxa : in std_logic;
4921 
      ssrstate_1_sqmuxa_1_0_m3_0_1 : out std_logic;
4922 
      n_apbi_penable : in std_logic;
4923 
      n_apbi_pwrite : in std_logic;
4924 
      d_m1_e_0_0 : in std_logic;
4925 
      hsel_1_0_L3 : out std_logic;
4926 
      ssrhready_8_f0_L8 : out std_logic;
4927 
      ssrstate_1_sqmuxa_1 : in std_logic;
4928 
      ssrhready : out std_logic;
4929 
      ssrhready_8_f0_L5 : out std_logic;
4930 
      ssrstate17_1_xx_mm_N_4 : in std_logic;
4931 
      ws_1_sqmuxa : out std_logic;
4932 
      ws_4_sqmuxa_0 : in std_logic;
4933 
      ws_2_sqmuxa_0 : in std_logic;
4934 
      ssrstate17_2_0_m6_i_1 : out std_logic;
4935 
      ws_2_sqmuxa_3_0_x : out std_logic;
4936 
      ws_3_sqmuxa_1 : out std_logic;
4937 
      ws_2_sqmuxa_3_0_2 : out std_logic;
4938 
      ssrstate_2_i : out std_logic;
4939 
      ws_2_sqmuxa_3_d : out std_logic;
4940 
      ws_0_sqmuxa_1 : out std_logic;
4941 
      g0_30 : in std_logic;
4942 
      hsel_4 : in std_logic;
4943 
      n_ahbsi_hready : in std_logic;
4944 
      hsel : out std_logic;
4945 
      g0_25 : in std_logic;
4946 
      bwn_0_sqmuxa_1 : in std_logic;
4947 
      prstate_2_rep1 : out std_logic;
4948 
      N_662 : out std_logic;
4949 
      ssrstate_6_sqmuxa : out std_logic;
4950 
      g0_52_x1 : in std_logic;
4951 
      g0_52_x0 : in std_logic;
4952 
      ssrhready_2_sqmuxa_0_0 : out std_logic;
4953 
      change_1_sqmuxa_N_3 : out std_logic;
4954 
      ssrstate6_xx_mm_m3 : out std_logic;
4955 
      ssrstate6_1_d_0_L1 : out std_logic;
4956 
      N_656 : out std_logic;
4957 
      hsel_5 : out std_logic;
4958 
      change_3_f0 : in std_logic;
4959 
      un1_ahbsi : out std_logic;
4960 
      change : out std_logic;
4961 
      n_ahbsi_hwrite : in std_logic;
4962 
      N_574_i : in std_logic;
4963 
      n_sro_iosn : out std_logic;
4964 
      N_618_i : in std_logic;
4965 
      clk : in std_logic;
4966 
      n_sro_oen : out std_logic;
4967 
      rst : in std_logic;
4968 
      bwn_1_sqmuxa_2_d : in std_logic;
4969 
      bwn_1_sqmuxa_2_d_0_2 : in std_logic;
4970 
      ssrstate_2_sqmuxa_i : in std_logic;
4971 
      g0_23 : in std_logic;
4972 
      N_371 : out std_logic;
4973 
      loadcount_7 : in std_logic;
4974 
      bus16en : out std_logic;
4975 
      d16muxc_0_4 : out std_logic;
4976 
      change_3_f1_d_0_0 : in std_logic;
4977 
      g0_1_0 : in std_logic;
4978 
      g0_44 : in std_logic  );
4979 
  end component;
4980 
begin
4981 
  II_g0_46: LUT4_L
4982 
  generic map(
4983 
    INIT => X"B000"
4984 
  )
4985 
  port map (
4986 
    I0 => N_4,
4987 
    I1 => N_17,
4988 
    I2 => G0_46_L7,
4989 
    I3 => G3,
4990 
    LO => WRP_CTRL_V_HREADY_2);
4991 
  II_g0_45: LUT4_L
4992 
  generic map(
4993 
    INIT => X"0B00"
4994 
  )
4995 
  port map (
4996 
    I0 => N_4,
4997 
    I1 => N_17,
4998 
    I2 => SSRHREADY_8_F0_L8,
4999 
    I3 => G3,
5000 
    LO => WRP_CTRL_V_SSRHREADY_8);
5001 
  II_g0_35: LUT4_L
5002 
  generic map(
5003 
    INIT => X"00B1"
5004 
  )
5005 
  port map (
5006 
    I0 => N_622,
5007 
    I1 => G0_34,
5008 
    I2 => G0_29,
5009 
    I3 => WRP_V_SSRSTATE_2_SQMUXA_1,
5010 
    LO => WRP_R_SSRSTATEC);
5011 
  II_g0_57: LUT4_L
5012 
  generic map(
5013 
    INIT => X"FA44"
5014 
  )
5015 
  port map (
5016 
    I0 => N_371,
5017 
    I1 => G0_56,
5018 
    I2 => G0_I_M2_2,
5019 
    I3 => G0_57_1,
5020 
    LO => WRP_CTRL_V_WS_1(0));
5021 
  II_g0_i_m2_0: LUT4_L
5022 
  generic map(
5023 
    INIT => X"B1E4"
5024 
  )
5025 
  port map (
5026 
    I0 => N_5,
5027 
    I1 => G0_I_M2_0_L3,
5028 
    I2 => G0_I_M2_0_L5,
5029 
    I3 => WRP_R_WS(3),
5030 
    LO => WRP_CTRL_V_WS_1(3));
5031 
  II_g0_i_m2: LUT4_L
5032 
  generic map(
5033 
    INIT => X"D8CC"
5034 
  )
5035 
  port map (
5036 
    I0 => N_622,
5037 
    I1 => G0_I_M2_L1,
5038 
    I2 => WRP_CTRL_V_SSRSTATE_1_M1(4),
5039 
    I3 => WRP_UN1_V_SSRSTATE_2_SQMUXA_I,
5040 
    LO => WRP_CTRL_V_SSRSTATE_1(4));
5041 
  II_g0_5: LUT4_L
5042 
  generic map(
5043 
    INIT => X"37FF"
5044 
  )
5045 
  port map (
5046 
    I0 => WRP_CTRL_HSIZE_1(1),
5047 
    I1 => WRP_CTRL_V_BWN_1_0_O3(0),
5048 
    I2 => WRP_HADDR(1),
5049 
    I3 => WRP_UN1_V_BWN_1_SQMUXA_2_D,
5050 
    LO => N_618_I);
5051 
  II_g0_46_L1: LUT3
5052 
  generic map(
5053 
    INIT => X"13"
5054 
  )
5055 
  port map (
5056 
    I0 => WRP_R_D16MUXC_0_4,
5057 
    I1 => WRP_R_SSRHREADY,
5058 
    I2 => WRP_R_SSRSTATE(3),
5059 
    O => G0_46_L1);
5060 
  II_g0_46_L3: LUT3
5061 
  generic map(
5062 
    INIT => X"0B"
5063 
  )
5064 
  port map (
5065 
    I0 => WRP_CTRL_UN1_AHBSI,
5066 
    I1 => WRP_CTRL_V_HSEL_5,
5067 
    I2 => WRP_R_CHANGE,
5068 
    O => G0_46_L3);
5069 
  II_g0_46_L5: LUT3
5070 
  generic map(
5071 
    INIT => X"5D"
5072 
  )
5073 
  port map (
5074 
    I0 => G0_44,
5075 
    I1 => G0_46_L1,
5076 
    I2 => WRP_V_SSRSTATE_1_SQMUXA_1,
5077 
    O => G0_46_L5);
5078 
  II_g0_46_L7: LUT4_L
5079 
  generic map(
5080 
    INIT => X"1033"
5081 
  )
5082 
  port map (
5083 
    I0 => G0_46_L3,
5084 
    I1 => G0_46_L5,
5085 
    I2 => WRP_CTRL_V_CHANGE_3_F1_D_0_0,
5086 
    I3 => WRP_V_PRSTATE_1_I_O4_S(2),
5087 
    LO => G0_46_L7);
5088 
  II_g2_0: LUT4
5089 
  generic map(
5090 
    INIT => X"E0EA"
5091 
  )
5092 
  port map (
5093 
    I0 => SSRHREADY_8_F0_L5,
5094 
    I1 => G2_0_1,
5095 
    I2 => WRP_CTRL_V_HMBSEL_4(1),
5096 
    I3 => WRP_R_SSRSTATE(2),
5097 
    O => N_4);
5098 
  II_g2_0_1: LUT3
5099 
  generic map(
5100 
    INIT => X"20"
5101 
  )
5102 
  port map (
5103 
    I0 => G0_48_L1,
5104 
    I1 => WRP_CTRL_UN1_AHBSI,
5105 
    I2 => WRP_CTRL_V_HSEL_5,
5106 
    O => G2_0_1);
5107 
  II_g0_52_x1x: LUT4
5108 
  generic map(
5109 
    INIT => X"35F5"
5110 
  )
5111 
  port map (
5112 
    I0 => D_M1_E_0_0,
5113 
    I1 => n_ahbsi_hmbsel(1),
5114 
    I2 => n_ahbsi_hready,
5115 
    I3 => n_ahbsi_hsel(0),
5116 
    O => G0_52X_0);
5117 
  II_g0_52_x0x: LUT2
5118 
  generic map(
5119 
    INIT => X"D"
5120 
  )
5121 
  port map (
5122 
    I0 => D_M1_E_0_0,
5123 
    I1 => n_ahbsi_hready,
5124 
    O => G0_52X);
5125 
  II_g0_55_L7_L1: LUT3
5126 
  generic map(
5127 
    INIT => X"E2"
5128 
  )
5129 
  port map (
5130 
    I0 => G0_55_L7_L1_RN_0,
5131 
    I1 => G0_55_L7_L1_SN,
5132 
    I2 => n_ahbsi_htrans(1),
5133 
    O => G0_55_L7_L1);
5134 
  II_g0_55_L7_L1_sn: LUT4
5135 
  generic map(
5136 
    INIT => X"8D88"
5137 
  )
5138 
  port map (
5139 
    I0 => n_ahbsi_hready,
5140 
    I1 => n_ahbsi_hsel(0),
5141 
    I2 => n_ahbsi_htrans(0),
5142 
    I3 => WRP_R_HSEL,
5143 
    O => G0_55_L7_L1_SN);
5144 
  II_g0_55_L7_L1_rn: LUT2
5145 
  generic map(
5146 
    INIT => X"4"
5147 
  )
5148 
  port map (
5149 
    I0 => n_ahbsi_hready,
5150 
    I1 => WRP_R_HSEL,
5151 
    O => G0_55_L7_L1_RN_0);
5152 
  II_g0_57_1_L7_L6: LUT3
5153 
  generic map(
5154 
    INIT => X"E2"
5155 
  )
5156 
  port map (
5157 
    I0 => G0_57_1_L7_L6_RN_0,
5158 
    I1 => G0_57_1_L7_L6_SN,
5159 
    I2 => n_ahbsi_htrans(1),
5160 
    O => G0_57_1_L7_L6);
5161 
  II_g0_57_1_L7_L6_sn: LUT4
5162 
  generic map(
5163 
    INIT => X"8D88"
5164 
  )
5165 
  port map (
5166 
    I0 => n_ahbsi_hready,
5167 
    I1 => n_ahbsi_hsel(0),
5168 
    I2 => n_ahbsi_htrans(0),
5169 
    I3 => WRP_R_HSEL,
5170 
    O => G0_57_1_L7_L6_SN);
5171 
  II_g0_57_1_L7_L6_rn: LUT2
5172 
  generic map(
5173 
    INIT => X"4"
5174 
  )
5175 
  port map (
5176 
    I0 => n_ahbsi_hready,
5177 
    I1 => WRP_R_HSEL,
5178 
    O => G0_57_1_L7_L6_RN_0);
5179 
  II_g0_0_L1: LUT2
5180 
  generic map(
5181 
    INIT => X"7"
5182 
  )
5183 
  port map (
5184 
    I0 => rst,
5185 
    I1 => WRP_R_PRSTATE_2_REP1,
5186 
    O => G0_0_L1);
5187 
  II_g0_0_L3: LUT2
5188 
  generic map(
5189 
    INIT => X"4"
5190 
  )
5191 
  port map (
5192 
    I0 => WRP_V_CHANGE_1_SQMUXA_N_3,
5193 
    I1 => WRP_V_SSRHREADY_2_SQMUXA_0_0,
5194 
    O => G0_0_L3);
5195 
  II_g0_0_L5: LUT4
5196 
  generic map(
5197 
    INIT => X"55DF"
5198 
  )
5199 
  port map (
5200 
    I0 => G0_0_L1,
5201 
    I1 => WRP_CTRL_UN1_AHBSI,
5202 
    I2 => WRP_CTRL_V_HSEL_5,
5203 
    I3 => WRP_R_D16MUXC_0_4,
5204 
    O => G0_0_L5);
5205 
  II_g0_0_L7: LUT2
5206 
  generic map(
5207 
    INIT => X"2"
5208 
  )
5209 
  port map (
5210 
    I0 => n_ahbsi_htrans(0),
5211 
    I1 => WRP_CTRL_UN1_V_SSRSTATE17_1_XX_MM_N_4,
5212 
    O => G0_0_L7);
5213 
  II_g0_0_L9: LUT4
5214 
  generic map(
5215 
    INIT => X"7F33"
5216 
  )
5217 
  port map (
5218 
    I0 => G0_0_L3,
5219 
    I1 => n_ahbsi_hwrite,
5220 
    I2 => WRP_CTRL_V_HMBSEL_4(1),
5221 
    I3 => SSRSTATE6_XX_MM_M3,
5222 
    O => G0_0_L9);
5223 
  II_g0_0: LUT4
5224 
  generic map(
5225 
    INIT => X"FFEF"
5226 
  )
5227 
  port map (
5228 
    I0 => G0_0_L5,
5229 
    I1 => G0_0_L7,
5230 
    I2 => G0_0_L9,
5231 
    I3 => WRP_V_LOADCOUNT_1_SQMUXA,
5232 
    O => WRP_UN1_V_BWN_1_SQMUXA_2_D);
5233 
  II_g3: LUT4
5234 
  generic map(
5235 
    INIT => X"DFCC"
5236 
  )
5237 
  port map (
5238 
    I0 => G3_1,
5239 
    I1 => n_ahbsi_hwrite,
5240 
    I2 => WRP_CTRL_V_HMBSEL_4(1),
5241 
    I3 => SSRSTATE6_XX_MM_M3,
5242 
    O => G3);
5243 
  II_g3_1: LUT2
5244 
  generic map(
5245 
    INIT => X"4"
5246 
  )
5247 
  port map (
5248 
    I0 => WRP_V_CHANGE_1_SQMUXA_N_3,
5249 
    I1 => WRP_V_SSRHREADY_2_SQMUXA_0_0,
5250 
    O => G3_1);
5251 
  II_g0_i_m2_0_L1: LUT3
5252 
  generic map(
5253 
    INIT => X"01"
5254 
  )
5255 
  port map (
5256 
    I0 => WRP_R_WS(0),
5257 
    I1 => WRP_R_WS(1),
5258 
    I2 => WRP_R_WS(2),
5259 
    O => G0_I_M2_0_L1);
5260 
  II_g0_i_m2_0_L3: LUT4
5261 
  generic map(
5262 
    INIT => X"0A2A"
5263 
  )
5264 
  port map (
5265 
    I0 => G0_I_M2_0_L1,
5266 
    I1 => G0_30,
5267 
    I2 => WRP_V_WS_0_SQMUXA_1,
5268 
    I3 => WRP_V_WS_3_SQMUXA_1,
5269 
    O => G0_I_M2_0_L3);
5270 
  II_g0_i_m2_0_L5: LUT4
5271 
  generic map(
5272 
    INIT => X"1555"
5273 
  )
5274 
  port map (
5275 
    I0 => D_M1_E_L1_0,
5276 
    I1 => D_M1_E_L3,
5277 
    I2 => WRP_V_WS_2_SQMUXA_3_0_2,
5278 
    I3 => WRP_V_WS_2_SQMUXA_3_D,
5279 
    O => G0_I_M2_0_L5);
5280 
  II_d_m1_e_L1_0: LUT3
5281 
  generic map(
5282 
    INIT => X"4E"
5283 
  )
5284 
  port map (
5285 
    I0 => N_365,
5286 
    I1 => D_M1_E_L1,
5287 
    I2 => WRP_R_MCFG1_ROMRWS(3),
5288 
    O => D_M1_E_L1_0);
5289 
  II_d_m1_e_L3: LUT4_L
5290 
  generic map(
5291 
    INIT => X"0F2F"
5292 
  )
5293 
  port map (
5294 
    I0 => WRP_UN1_R_SSRSTATE_2_I,
5295 
    I1 => G0_30,
5296 
    I2 => WRP_V_WS_0_SQMUXA_1,
5297 
    I3 => WRP_V_WS_3_SQMUXA_1,
5298 
    LO => D_M1_E_L3);
5299 
  II_g0_57_1_L7_L4: LUT4
5300 
  generic map(
5301 
    INIT => X"4555"
5302 
  )
5303 
  port map (
5304 
    I0 => SSRSTATE6_1_D_0_L1,
5305 
    I1 => n_ahbsi_htrans(0),
5306 
    I2 => n_ahbsi_htrans(1),
5307 
    I3 => WRP_R_SSRSTATE(1),
5308 
    O => G0_57_1_L7_L4);
5309 
  II_g0_57_1_L7_L8: LUT4_L
5310 
  generic map(
5311 
    INIT => X"4C40"
5312 
  )
5313 
  port map (
5314 
    I0 => G0_57_1_L7_L4,
5315 
    I1 => G0_57_1_L7_L6,
5316 
    I2 => WRP_CTRL_V_HMBSEL_4(1),
5317 
    I3 => WRP_R_SSRSTATE(2),
5318 
    LO => G0_57_1_L7_L8);
5319 
  II_g0_57_1_L7: LUT4_L
5320 
  generic map(
5321 
    INIT => X"4F5F"
5322 
  )
5323 
  port map (
5324 
    I0 => N_656,
5325 
    I1 => G0_57_1_L7_L8,
5326 
    I2 => rst,
5327 
    I3 => SSRSTATE6_XX_MM_M3,
5328 
    LO => G0_57_1_L7);
5329 
  II_g0_34_L10_L1: LUT4
5330 
  generic map(
5331 
    INIT => X"0400"
5332 
  )
5333 
  port map (
5334 
    I0 => n_ahbsi_htrans(0),
5335 
    I1 => n_ahbsi_htrans(1),
5336 
    I2 => n_ahbsi_hwrite,
5337 
    I3 => WRP_R_SSRSTATE(1),
5338 
    O => G0_34_L10_L1);
5339 
  II_g0_34_L10_L3: LUT2
5340 
  generic map(
5341 
    INIT => X"7"
5342 
  )
5343 
  port map (
5344 
    I0 => G0_34_L10_L1,
5345 
    I1 => WRP_CTRL_V_HSEL_5,
5346 
    O => G0_34_L10_L3);
5347 
  II_g0_34_L10: LUT4
5348 
  generic map(
5349 
    INIT => X"00B0"
5350 
  )
5351 
  port map (
5352 
    I0 => G0_34_L10_L3,
5353 
    I1 => WRP_CTRL_V_HMBSEL_4(1),
5354 
    I2 => WRP_UN1_V_CHANGE_1_SQMUXA_0,
5355 
    I3 => WRP_V_SSRSTATE_6_SQMUXA,
5356 
    O => G0_34_L10);
5357 
  II_g0_48_L1: LUT3
5358 
  generic map(
5359 
    INIT => X"40"
5360 
  )
5361 
  port map (
5362 
    I0 => n_ahbsi_htrans(0),
5363 
    I1 => n_ahbsi_htrans(1),
5364 
    I2 => n_ahbsi_hwrite,
5365 
    O => G0_48_L1);
5366 
  II_g0_48: LUT4
5367 
  generic map(
5368 
    INIT => X"2000"
5369 
  )
5370 
  port map (
5371 
    I0 => G0_48_L1,
5372 
    I1 => WRP_CTRL_UN1_AHBSI,
5373 
    I2 => WRP_CTRL_V_HMBSEL_4(1),
5374 
    I3 => WRP_CTRL_V_HSEL_5,
5375 
    O => WRP_V_LOADCOUNT_1_SQMUXA);
5376 
  II_g0_36_L1: LUT3
5377 
  generic map(
5378 
    INIT => X"2F"
5379 
  )
5380 
  port map (
5381 
    I0 => WRP_R_CHANGE,
5382 
    I1 => WRP_R_HSEL,
5383 
    I2 => WRP_R_PRSTATE(5),
5384 
    O => G0_36_L1);
5385 
  II_g0_36: LUT4
5386 
  generic map(
5387 
    INIT => X"2220"
5388 
  )
5389 
  port map (
5390 
    I0 => G0_I_M2_1,
5391 
    I1 => G0_36_L1,
5392 
    I2 => WRP_CTRL_V_HSEL_5,
5393 
    I3 => WRP_R_CHANGE,
5394 
    O => WRP_V_PRSTATE_1_I_O4_S(2));
5395 
  II_g0_55_L7: LUT4_L
5396 
  generic map(
5397 
    INIT => X"4CFC"
5398 
  )
5399 
  port map (
5400 
    I0 => G0_55_L1,
5401 
    I1 => G0_55_L5,
5402 
    I2 => G0_55_L7_L1,
5403 
    I3 => WRP_CTRL_V_HMBSEL_4(1),
5404 
    LO => G0_55_L7);
5405 
  II_g0_55_L5_L1: LUT4
5406 
  generic map(
5407 
    INIT => X"35FF"
5408 
  )
5409 
  port map (
5410 
    I0 => D_M1_E_0_0,
5411 
    I1 => n_ahbsi_hmbsel(1),
5412 
    I2 => n_ahbsi_hready,
5413 
    I3 => n_ahbsi_htrans(0),
5414 
    O => G0_55_L5_L1);
5415 
  II_g0_55_L5: LUT4
5416 
  generic map(
5417 
    INIT => X"51FF"
5418 
  )
5419 
  port map (
5420 
    I0 => G0_55_L5_L1,
5421 
    I1 => n_ahbsi_hready,
5422 
    I2 => WRP_CTRL_V_HSEL_4,
5423 
    I3 => WRP_R_SSRSTATE(2),
5424 
    O => G0_55_L5);
5425 
  II_g0_57_1_L5: LUT3
5426 
  generic map(
5427 
    INIT => X"70"
5428 
  )
5429 
  port map (
5430 
    I0 => G0_30,
5431 
    I1 => WRP_V_WS_0_SQMUXA_1,
5432 
    I2 => WRP_V_WS_2_SQMUXA_3_D,
5433 
    O => G0_57_1_L5);
5434 
  II_g0_57_1: LUT4_L
5435 
  generic map(
5436 
    INIT => X"1D55"
5437 
  )
5438 
  port map (
5439 
    I0 => N_365,
5440 
    I1 => G0_57_1_L5,
5441 
    I2 => G0_57_1_L7,
5442 
    I3 => WRP_V_WS_2_SQMUXA_3_0_4,
5443 
    LO => G0_57_1);
5444 
  II_d_m1_e_L1: LUT4
5445 
  generic map(
5446 
    INIT => X"087F"
5447 
  )
5448 
  port map (
5449 
    I0 => N_SRO_ROMSN_0_INT_260,
5450 
    I1 => rst,
5451 
    I2 => WRP_R_MCFG1_IOWS(3),
5452 
    I3 => WRP_R_MCFG1_ROMWWS(3),
5453 
    O => D_M1_E_L1);
5454 
  II_g0_i_o4: LUT4_L
5455 
  generic map(
5456 
    INIT => X"FDF5"
5457 
  )
5458 
  port map (
5459 
    I0 => N_365,
5460 
    I1 => WS_2_SQMUXA_3_0_X,
5461 
    I2 => WRP_V_WS_1_SQMUXA,
5462 
    I3 => WRP_V_WS_2_SQMUXA_3_0_4,
5463 
    LO => N_5);
5464 
  II_g3_2: LUT4
5465 
  generic map(
5466 
    INIT => X"7FFF"
5467 
  )
5468 
  port map (
5469 
    I0 => G0_50_X,
5470 
    I1 => n_ahbsi_hmbsel(1),
5471 
    I2 => n_ahbsi_hsel(0),
5472 
    I3 => n_ahbsi_htrans(1),
5473 
    O => N_19);
5474 
  II_g0_50_x: LUT3_L
5475 
  generic map(
5476 
    INIT => X"80"
5477 
  )
5478 
  port map (
5479 
    I0 => n_ahbsi_hready,
5480 
    I1 => WRP_R_PRSTATE(5),
5481 
    I2 => WRP_R_SSRSTATE(4),
5482 
    LO => G0_50_X);
5483 
  II_g0_52: MUXF5 port map (
5484 
      I0 => G0_52X,
5485 
      I1 => G0_52X_0,
5486 
      S => n_ahbsi_htrans(1),
5487 
      O => WRP_CTRL_UN1_V_SSRSTATE17_1_XX_MM_N_4);
5488 
  II_g0_52_x1: LUT4
5489 
  generic map(
5490 
    INIT => X"35F5"
5491 
  )
5492 
  port map (
5493 
    I0 => D_M1_E_0_0,
5494 
    I1 => n_ahbsi_hmbsel(1),
5495 
    I2 => n_ahbsi_hready,
5496 
    I3 => n_ahbsi_hsel(0),
5497 
    O => G0_52_X1);
5498 
  II_g0_52_x0: LUT2
5499 
  generic map(
5500 
    INIT => X"D"
5501 
  )
5502 
  port map (
5503 
    I0 => D_M1_E_0_0,
5504 
    I1 => n_ahbsi_hready,
5505 
    O => G0_52_X0);
5506 
  II_g1_1: LUT4
5507 
  generic map(
5508 
    INIT => X"0105"
5509 
  )
5510 
  port map (
5511 
    I0 => SSRSTATE17_2_0_M6_I_A3_A2,
5512 
    I1 => n_ahbsi_htrans(1),
5513 
    I2 => WRP_UN1_V_SSRSTATE17_2_0_M6_I_1,
5514 
    I3 => WRP_UN1_V_SSRSTATE_1_SQMUXA_1_0_M3_0_1,
5515 
    O => N_14);
5516 
  II_g0_19_L1: LUT4_L
5517 
  generic map(
5518 
    INIT => X"0001"
5519 
  )
5520 
  port map (
5521 
    I0 => G0_28,
5522 
    I1 => WRP_CTRL_UN1_AHBSI,
5523 
    I2 => WRP_CTRL_V_HMBSEL_4(1),
5524 
    I3 => WRP_V_CHANGE_1_SQMUXA_N_3,
5525 
    LO => G0_19_L1);
5526 
  II_g0_19: LUT4
5527 
  generic map(
5528 
    INIT => X"0010"
5529 
  )
5530 
  port map (
5531 
    I0 => G0_19_L1,
5532 
    I1 => WRP_R_SSRSTATE(1),
5533 
    I2 => WRP_UN1_V_CHANGE_1_SQMUXA_0,
5534 
    I3 => WRP_V_SSRSTATE_6_SQMUXA,
5535 
    O => N_622);
5536 
  II_g0_55_L1: LUT4
5537 
  generic map(
5538 
    INIT => X"0400"
5539 
  )
5540 
  port map (
5541 
    I0 => n_ahbsi_htrans(0),
5542 
    I1 => n_ahbsi_htrans(1),
5543 
    I2 => n_ahbsi_hwrite,
5544 
    I3 => WRP_R_SSRSTATE(1),
5545 
    O => G0_55_L1);
5546 
  II_g0_55: LUT4
5547 
  generic map(
5548 
    INIT => X"0F0D"
5549 
  )
5550 
  port map (
5551 
    I0 => G0_55_L7,
5552 
    I1 => WRP_R_LOADCOUNT,
5553 
    I2 => WRP_R_SSRSTATE(3),
5554 
    I3 => WRP_V_SSRSTATE_1_SQMUXA_1,
5555 
    O => WRP_CTRL_V_LOADCOUNT_7);
5556 
  II_g0_34_L1_0: LUT2
5557 
  generic map(
5558 
    INIT => X"4"
5559 
  )
5560 
  port map (
5561 
    I0 => WRP_R_D16MUXC_0_4,
5562 
    I1 => WRP_V_WS_0_SQMUXA_0_C,
5563 
    O => G0_34_L1_0);
5564 
  II_g0_34_L6: LUT4
5565 
  generic map(
5566 
    INIT => X"A2AA"
5567 
  )
5568 
  port map (
5569 
    I0 => G0_34_L1_0,
5570 
    I1 => WRP_CTRL_V_HSEL_5,
5571 
    I2 => WRP_R_SSRSTATE(0),
5572 
    I3 => WRP_V_WS_0_SQMUXA_C,
5573 
    O => G0_34_L6);
5574 
  II_g0_34: LUT4_L
5575 
  generic map(
5576 
    INIT => X"51F3"
5577 
  )
5578 
  port map (
5579 
    I0 => G0_34_L6,
5580 
    I1 => G0_34_L10,
5581 
    I2 => WRP_NONAME_CNST(0),
5582 
    I3 => WRP_R_SSRSTATE(1),
5583 
    LO => G0_34);
5584 
  II_g0_54_L1: LUT4_L
5585 
  generic map(
5586 
    INIT => X"0400"
5587 
  )
5588 
  port map (
5589 
    I0 => n_ahbsi_htrans(0),
5590 
    I1 => n_ahbsi_htrans(1),
5591 
    I2 => WRP_CTRL_UN1_AHBSI,
5592 
    I3 => WRP_CTRL_V_HSEL_5,
5593 
    LO => G0_54_L1);
5594 
  II_g0_54: LUT4
5595 
  generic map(
5596 
    INIT => X"2000"
5597 
  )
5598 
  port map (
5599 
    I0 => G0_54_L1,
5600 
    I1 => n_ahbsi_hwrite,
5601 
    I2 => WRP_CTRL_V_HMBSEL_4(1),
5602 
    I3 => WRP_R_SSRSTATE(1),
5603 
    O => WRP_CTRL_V_SSRSTATE_1_M1(3));
5604 
  II_g0_i_m2_L1: LUT3
5605 
  generic map(
5606 
    INIT => X"75"
5607 
  )
5608 
  port map (
5609 
    I0 => rst,
5610 
    I1 => WRP_R_SSRSTATE(3),
5611 
    I2 => WRP_V_SSRSTATE_1_SQMUXA_1,
5612 
    O => G0_I_M2_L1);
5613 
  II_g0_56: LUT4
5614 
  generic map(
5615 
    INIT => X"CC5A"
5616 
  )
5617 
  port map (
5618 
    I0 => N_9,
5619 
    I1 => WRP_R_MCFG1_ROMRWS(0),
5620 
    I2 => WRP_R_WS(0),
5621 
    I3 => WRP_V_WS_1_SQMUXA,
5622 
    O => G0_56);
5623 
  II_g1_3: LUT3_L
5624 
  generic map(
5625 
    INIT => X"37"
5626 
  )
5627 
  port map (
5628 
    I0 => G0_30,
5629 
    I1 => WRP_V_WS_0_SQMUXA_1,
5630 
    I2 => WRP_V_WS_3_SQMUXA_1,
5631 
    LO => N_9);
5632 
  II_g0_30: LUT4
5633 
  generic map(
5634 
    INIT => X"AEAA"
5635 
  )
5636 
  port map (
5637 
    I0 => N_14,
5638 
    I1 => N_19,
5639 
    I2 => G0_8,
5640 
    I3 => WRP_R_SSRSTATE(4),
5641 
    O => G0_30);
5642 
  II_g0_16: LUT4
5643 
  generic map(
5644 
    INIT => X"337F"
5645 
  )
5646 
  port map (
5647 
    I0 => N_SRO_ROMSN_0_INT_260,
5648 
    I1 => rst,
5649 
    I2 => WRP_V_WS_2_SQMUXA_0,
5650 
    I3 => WRP_V_WS_4_SQMUXA_0,
5651 
    O => N_365);
5652 
  II_g0_8: LUT4
5653 
  generic map(
5654 
    INIT => X"4000"
5655 
  )
5656 
  port map (
5657 
    I0 => n_ahbsi_hready,
5658 
    I1 => WRP_R_HMBSEL(1),
5659 
    I2 => WRP_R_HSEL,
5660 
    I3 => WRP_R_PRSTATE(5),
5661 
    O => G0_8);
5662 
  II_g0_i_m2_2: LUT4
5663 
  generic map(
5664 
    INIT => X"F780"
5665 
  )
5666 
  port map (
5667 
    I0 => N_SRO_ROMSN_0_INT_260,
5668 
    I1 => rst,
5669 
    I2 => WRP_R_MCFG1_IOWS(0),
5670 
    I3 => WRP_R_MCFG1_ROMWWS(0),
5671 
    O => G0_I_M2_2);
5672 
  II_g0_7: LUT3
5673 
  generic map(
5674 
    INIT => X"54"
5675 
  )
5676 
  port map (
5677 
    I0 => N_SRO_IOSN_INT_259,
5678 
    I1 => WRP_R_PRSTATE(4),
5679 
    I2 => WRP_R_PRSTATE_2_REP1,
5680 
    O => WRP_V_WS_2_SQMUXA_0);
5681 
  II_g0_6: LUT2
5682 
  generic map(
5683 
    INIT => X"4"
5684 
  )
5685 
  port map (
5686 
    I0 => N_SRO_ROMSN_0_INT_260,
5687 
    I1 => WRP_R_PRSTATE_FAST(2),
5688 
    O => WRP_V_WS_4_SQMUXA_0);
5689 
  II_g0_53: LUT4
5690 
  generic map(
5691 
    INIT => X"1050"
5692 
  )
5693 
  port map (
5694 
    I0 => G0_51,
5695 
    I1 => WRP_CTRL_V_HSEL_4,
5696 
    I2 => WRP_R_SSRSTATE(4),
5697 
    I3 => WRP_V_SSRSTATE_1_SQMUXA_1_XX_MM_A1_0,
5698 
    O => WRP_V_SSRSTATE_1_SQMUXA_1);
5699 
  II_g0_51: LUT4
5700 
  generic map(
5701 
    INIT => X"2000"
5702 
  )
5703 
  port map (
5704 
    I0 => G0_8_1,
5705 
    I1 => n_ahbsi_hready,
5706 
    I2 => WRP_R_HMBSEL(1),
5707 
    I3 => WRP_R_HSEL,
5708 
    O => G0_51);
5709 
  II_g0_50: LUT4
5710 
  generic map(
5711 
    INIT => X"8000"
5712 
  )
5713 
  port map (
5714 
    I0 => n_ahbsi_hmbsel(1),
5715 
    I1 => n_ahbsi_hready,
5716 
    I2 => WRP_R_PRSTATE(5),
5717 
    I3 => WRP_R_SSRSTATE(4),
5718 
    O => WRP_V_SSRSTATE_1_SQMUXA_1_XX_MM_A1_0);
5719 
  II_g0_8_1: LUT2
5720 
  generic map(
5721 
    INIT => X"8"
5722 
  )
5723 
  port map (
5724 
    I0 => WRP_R_PRSTATE(5),
5725 
    I1 => WRP_R_SSRSTATE(4),
5726 
    O => G0_8_1);
5727 
  II_g0_4: LUT2
5728 
  generic map(
5729 
    INIT => X"8"
5730 
  )
5731 
  port map (
5732 
    I0 => WRP_R_HMBSEL(1),
5733 
    I1 => WRP_R_HSEL,
5734 
    O => D_M1_E_0_0);
5735 
  II_g0_3: LUT2
5736 
  generic map(
5737 
    INIT => X"8"
5738 
  )
5739 
  port map (
5740 
    I0 => n_ahbsi_hsel(0),
5741 
    I1 => n_ahbsi_htrans(1),
5742 
    O => WRP_CTRL_V_HSEL_4);
5743 
  II_g0_i_0: LUT4
5744 
  generic map(
5745 
    INIT => X"AA80"
5746 
  )
5747 
  port map (
5748 
    I0 => G0_I_A3_0,
5749 
    I1 => rst,
5750 
    I2 => WRP_R_PRSTATE(2),
5751 
    I3 => WRP_V_BWN_0_SQMUXA_1,
5752 
    O => WRP_CTRL_V_BWN_1_0_O3(0));
5753 
  II_g0_2: LUT4
5754 
  generic map(
5755 
    INIT => X"C4CC"
5756 
  )
5757 
  port map (
5758 
    I0 => WRP_CTRL_V_HMBSEL_4(1),
5759 
    I1 => SSRSTATE6_XX_MM_M3,
5760 
    I2 => WRP_V_CHANGE_1_SQMUXA_N_3,
5761 
    I3 => WRP_V_SSRHREADY_2_SQMUXA_0_0,
5762 
    O => N_646);
5763 
  II_g0_i_a3_0: LUT4_L
5764 
  generic map(
5765 
    INIT => X"5D7F"
5766 
  )
5767 
  port map (
5768 
    I0 => N_319_1,
5769 
    I1 => N_662,
5770 
    I2 => n_ahbsi_haddr(0),
5771 
    I3 => N_SRO_ADDRESS_0_INT_172,
5772 
    LO => G0_I_A3_0);
5773 
  II_g0: LUT3
5774 
  generic map(
5775 
    INIT => X"D8"
5776 
  )
5777 
  port map (
5778 
    I0 => N_662,
5779 
    I1 => n_ahbsi_haddr(1),
5780 
    I2 => N_SRO_ADDRESS_1_INT_173,
5781 
    O => WRP_HADDR(1));
5782 
  II_g0_i: LUT4
5783 
  generic map(
5784 
    INIT => X"F3A2"
5785 
  )
5786 
  port map (
5787 
    I0 => G0_11,
5788 
    I1 => n_ahbsi_htrans(0),
5789 
    I2 => WRP_CTRL_UN1_V_SSRSTATE17_1_XX_MM_N_4,
5790 
    I3 => WRP_R_D16MUXC_0_4,
5791 
    O => G0_I);
5792 
  II_g0_47: LUT4
5793 
  generic map(
5794 
    INIT => X"202A"
5795 
  )
5796 
  port map (
5797 
    I0 => rst,
5798 
    I1 => WRP_R_D16MUXC_0_4,
5799 
    I2 => WRP_R_PRSTATE(1),
5800 
    I3 => WRP_R_PRSTATE_2_REP1,
5801 
    O => WRP_V_BWN_0_SQMUXA_1);
5802 
  II_g0_38: LUT3
5803 
  generic map(
5804 
    INIT => X"D8"
5805 
  )
5806 
  port map (
5807 
    I0 => N_662,
5808 
    I1 => n_ahbsi_hsize(1),
5809 
    I2 => WRP_R_SIZE(1),
5810 
    O => WRP_CTRL_HSIZE_1(1));
5811 
  II_g0_11: LUT2_L
5812 
  generic map(
5813 
    INIT => X"4"
5814 
  )
5815 
  port map (
5816 
    I0 => WRP_CTRL_UN1_AHBSI,
5817 
    I1 => WRP_CTRL_V_HSEL_5,
5818 
    LO => G0_11);
5819 
  II_g0_44: LUT4
5820 
  generic map(
5821 
    INIT => X"BBBA"
5822 
  )
5823 
  port map (
5824 
    I0 => G0_5_0,
5825 
    I1 => WRP_CTRL_UN7_BUS16EN,
5826 
    I2 => WRP_R_PRSTATE(0),
5827 
    I3 => WRP_V_D16MUX_0_SQMUXA,
5828 
    O => G0_44);
5829 
  II_g0_43: LUT4
5830 
  generic map(
5831 
    INIT => X"0400"
5832 
  )
5833 
  port map (
5834 
    I0 => N_SRO_ADDRESS_1_INT_173,
5835 
    I1 => WRP_CTRL_BUS16EN,
5836 
    I2 => WRP_R_SIZE(0),
5837 
    I3 => WRP_R_SIZE(1),
5838 
    O => WRP_CTRL_UN7_BUS16EN);
5839 
  II_g0_41: LUT2
5840 
  generic map(
5841 
    INIT => X"E"
5842 
  )
5843 
  port map (
5844 
    I0 => N_17,
5845 
    I1 => WRP_R_CHANGE,
5846 
    O => G0_1_0);
5847 
  II_g0_5_0: LUT2
5848 
  generic map(
5849 
    INIT => X"E"
5850 
  )
5851 
  port map (
5852 
    I0 => WRP_R_PRHREADY,
5853 
    I1 => WRP_R_PRSTATE(5),
5854 
    O => G0_5_0);
5855 
  II_g0_40: LUT2
5856 
  generic map(
5857 
    INIT => X"4"
5858 
  )
5859 
  port map (
5860 
    I0 => WRP_CTRL_UN1_AHBSI,
5861 
    I1 => WRP_CTRL_V_HSEL_5,
5862 
    O => N_17);
5863 
  II_g0_39: LUT2
5864 
  generic map(
5865 
    INIT => X"8"
5866 
  )
5867 
  port map (
5868 
    I0 => WRP_R_D16MUXC_0_4,
5869 
    I1 => WRP_R_PRSTATE(3),
5870 
    O => WRP_V_D16MUX_0_SQMUXA);
5871 
  II_g0_18: LUT3
5872 
  generic map(
5873 
    INIT => X"A2"
5874 
  )
5875 
  port map (
5876 
    I0 => G0_7_0,
5877 
    I1 => WRP_CTRL_V_HMBSEL_4(1),
5878 
    I2 => WRP_R_CHANGE,
5879 
    O => WRP_CTRL_V_CHANGE_3_F1_D_0_0);
5880 
  II_g0_17: LUT4
5881 
  generic map(
5882 
    INIT => X"A808"
5883 
  )
5884 
  port map (
5885 
    I0 => G0_I_M2_1,
5886 
    I1 => WRP_CTRL_V_HSEL_5,
5887 
    I2 => WRP_R_CHANGE,
5888 
    I3 => WRP_R_HSEL,
5889 
    O => WRP_UN1_V_HSEL_1(0));
5890 
  II_g0_7_0: LUT4
5891 
  generic map(
5892 
    INIT => X"00FE"
5893 
  )
5894 
  port map (
5895 
    I0 => WRP_R_CHANGE,
5896 
    I1 => WRP_R_SSRSTATE(1),
5897 
    I2 => WRP_R_SSRSTATE(2),
5898 
    I3 => WRP_R_SSRSTATE(4),
5899 
    O => G0_7_0);
5900 
  II_g0_15: LUT4
5901 
  generic map(
5902 
    INIT => X"00FE"
5903 
  )
5904 
  port map (
5905 
    I0 => WRP_R_CHANGE,
5906 
    I1 => WRP_R_SSRSTATE(1),
5907 
    I2 => WRP_R_SSRSTATE(2),
5908 
    I3 => WRP_R_SSRSTATE(4),
5909 
    O => WRP_CTRL_V_CHANGE_3_F0);
5910 
  II_g0_i_m2_1: LUT4
5911 
  generic map(
5912 
    INIT => X"3353"
5913 
  )
5914 
  port map (
5915 
    I0 => HSEL_1_0_L3,
5916 
    I1 => G0_14,
5917 
    I2 => n_ahbsi_hready,
5918 
    I3 => WRP_R_CHANGE,
5919 
    O => G0_I_M2_1);
5920 
  II_g0_14: LUT2
5921 
  generic map(
5922 
    INIT => X"1"
5923 
  )
5924 
  port map (
5925 
    I0 => WRP_R_HMBSEL(0),
5926 
    I1 => WRP_R_HMBSEL(2),
5927 
    O => G0_14);
5928 
  II_g0_33: LUT4
5929 
  generic map(
5930 
    INIT => X"085D"
5931 
  )
5932 
  port map (
5933 
    I0 => G0_31,
5934 
    I1 => G2_1_0,
5935 
    I2 => WRP_R_SSRSTATE(1),
5936 
    I3 => WRP_V_CHANGE_1_SQMUXA_N_3,
5937 
    O => WRP_UN1_V_CHANGE_1_SQMUXA_0);
5938 
  II_g0_32: LUT4
5939 
  generic map(
5940 
    INIT => X"0001"
5941 
  )
5942 
  port map (
5943 
    I0 => G0_28,
5944 
    I1 => WRP_CTRL_UN1_AHBSI,
5945 
    I2 => WRP_CTRL_V_HMBSEL_4(1),
5946 
    I3 => WRP_V_CHANGE_1_SQMUXA_N_3,
5947 
    O => WRP_NONAME_CNST(0));
5948 
  II_g0_31: LUT4
5949 
  generic map(
5950 
    INIT => X"FFAB"
5951 
  )
5952 
  port map (
5953 
    I0 => G0_28,
5954 
    I1 => n_ahbsi_htrans(0),
5955 
    I2 => n_ahbsi_htrans(1),
5956 
    I3 => WRP_R_SSRSTATE(0),
5957 
    O => G0_31);
5958 
  II_g2_1_0: LUT2
5959 
  generic map(
5960 
    INIT => X"1"
5961 
  )
5962 
  port map (
5963 
    I0 => WRP_R_SSRSTATE(0),
5964 
    I1 => WRP_R_SSRSTATE(2),
5965 
    O => G2_1_0);
5966 
  II_g0_29: LUT2
5967 
  generic map(
5968 
    INIT => X"2"
5969 
  )
5970 
  port map (
5971 
    I0 => n_ahbsi_hwrite,
5972 
    I1 => WRP_V_SSRSTATE_1_SQMUXA_1,
5973 
    O => G0_29);
5974 
  II_g0_28: LUT2
5975 
  generic map(
5976 
    INIT => X"1"
5977 
  )
5978 
  port map (
5979 
    I0 => WRP_R_SSRSTATE(1),
5980 
    I1 => WRP_R_SSRSTATE(2),
5981 
    O => G0_28);
5982 
  II_g0_27: LUT2
5983 
  generic map(
5984 
    INIT => X"8"
5985 
  )
5986 
  port map (
5987 
    I0 => rst,
5988 
    I1 => WRP_R_SSRSTATE(3),
5989 
    O => WRP_V_SSRSTATE_2_SQMUXA_1);
5990 
  II_g0_25: LUT2
5991 
  generic map(
5992 
    INIT => X"2"
5993 
  )
5994 
  port map (
5995 
    I0 => N_365,
5996 
    I1 => WRP_V_WS_1_SQMUXA,
5997 
    O => G0_25);
5998 
  II_g0_23: LUT3
5999 
  generic map(
6000 
    INIT => X"37"
6001 
  )
6002 
  port map (
6003 
    I0 => G0_30,
6004 
    I1 => WRP_V_WS_0_SQMUXA_1,
6005 
    I2 => WRP_V_WS_3_SQMUXA_1,
6006 
    O => G0_23);
6007 
  II_g0_12: LUT2
6008 
  generic map(
6009 
    INIT => X"1"
6010 
  )
6011 
  port map (
6012 
    I0 => WRP_R_SSRSTATE(0),
6013 
    I1 => WRP_R_SSRSTATE(2),
6014 
    O => D_M2_0_A2_0);
6015 
  II_g0_10: LUT2
6016 
  generic map(
6017 
    INIT => X"2"
6018 
  )
6019 
  port map (
6020 
    I0 => rst,
6021 
    I1 => WRP_R_SSRSTATE(3),
6022 
    O => WRP_UN1_V_SSRSTATE_2_SQMUXA_I);
6023 
  II_g0_1: LUT4
6024 
  generic map(
6025 
    INIT => X"FFD5"
6026 
  )
6027 
  port map (
6028 
    I0 => G0_I,
6029 
    I1 => rst,
6030 
    I2 => WRP_R_PRSTATE(2),
6031 
    I3 => WRP_V_LOADCOUNT_1_SQMUXA,
6032 
    O => WRP_UN1_V_BWN_1_SQMUXA_2_D_0_2);
6033 
  II_N_574_i: LUT4_L
6034 
  generic map(
6035 
    INIT => X"5545"
6036 
  )
6037 
  port map (
6038 
    I0 => N_593,
6039 
    I1 => N_596,
6040 
    I2 => D_M1_E_0_0,
6041 
    I3 => n_ahbsi_hready,
6042 
    LO => N_574_I);
6043 
  II_N_574_i_a3_0: LUT4_L
6044 
  generic map(
6045 
    INIT => X"4000"
6046 
  )
6047 
  port map (
6048 
    I0 => N_597,
6049 
    I1 => n_ahbsi_hmbsel(1),
6050 
    I2 => n_ahbsi_hready,
6051 
    I3 => WRP_CTRL_V_HSEL_4,
6052 
    LO => N_593);
6053 
  II_N_574_i_o3_0: LUT4
6054 
  generic map(
6055 
    INIT => X"135F"
6056 
  )
6057 
  port map (
6058 
    I0 => n_ahbsi_htrans(1),
6059 
    I1 => WRP_R_PRSTATE(5),
6060 
    I2 => WRP_R_SSRSTATE(1),
6061 
    I3 => WRP_R_SSRSTATE(4),
6062 
    O => N_596);
6063 
  II_N_574_i_o3: LUT3
6064 
  generic map(
6065 
    INIT => X"13"
6066 
  )
6067 
  port map (
6068 
    I0 => WRP_R_PRSTATE(5),
6069 
    I1 => WRP_R_SSRSTATE(1),
6070 
    I2 => WRP_R_SSRSTATE(4),
6071 
    O => N_597);
6072 
  II_wrp: ssrctrl_unisim_netlist port map (
6073 
      n_sro_vbdrive(0) => n_sro_vbdrive(0),
6074 
      n_sro_vbdrive(1) => n_sro_vbdrive(1),
6075 
      n_sro_vbdrive(2) => n_sro_vbdrive(2),
6076 
      n_sro_vbdrive(3) => n_sro_vbdrive(3),
6077 
      n_sro_vbdrive(4) => n_sro_vbdrive(4),
6078 
      n_sro_vbdrive(5) => n_sro_vbdrive(5),
6079 
      n_sro_vbdrive(6) => n_sro_vbdrive(6),
6080 
      n_sro_vbdrive(7) => n_sro_vbdrive(7),
6081 
      n_sro_vbdrive(8) => n_sro_vbdrive(8),
6082 
      n_sro_vbdrive(9) => n_sro_vbdrive(9),
6083 
      n_sro_vbdrive(10) => n_sro_vbdrive(10),
6084 
      n_sro_vbdrive(11) => n_sro_vbdrive(11),
6085 
      n_sro_vbdrive(12) => n_sro_vbdrive(12),
6086 
      n_sro_vbdrive(13) => n_sro_vbdrive(13),
6087 
      n_sro_vbdrive(14) => n_sro_vbdrive(14),
6088 
      n_sro_vbdrive(15) => n_sro_vbdrive(15),
6089 
      n_sro_vbdrive(16) => n_sro_vbdrive(16),
6090 
      n_sro_vbdrive(17) => n_sro_vbdrive(17),
6091 
      n_sro_vbdrive(18) => n_sro_vbdrive(18),
6092 
      n_sro_vbdrive(19) => n_sro_vbdrive(19),
6093 
      n_sro_vbdrive(20) => n_sro_vbdrive(20),
6094 
      n_sro_vbdrive(21) => n_sro_vbdrive(21),
6095 
      n_sro_vbdrive(22) => n_sro_vbdrive(22),
6096 
      n_sro_vbdrive(23) => n_sro_vbdrive(23),
6097 
      n_sro_vbdrive(24) => n_sro_vbdrive(24),
6098 
      n_sro_vbdrive(25) => n_sro_vbdrive(25),
6099 
      n_sro_vbdrive(26) => n_sro_vbdrive(26),
6100 
      n_sro_vbdrive(27) => n_sro_vbdrive(27),
6101 
      n_sro_vbdrive(28) => n_sro_vbdrive(28),
6102 
      n_sro_vbdrive(29) => n_sro_vbdrive(29),
6103 
      n_sro_vbdrive(30) => n_sro_vbdrive(30),
6104 
      n_sro_vbdrive(31) => n_sro_vbdrive(31),
6105 
      n_ahbso_hrdata(0) => n_ahbso_hrdata(0),
6106 
      n_ahbso_hrdata(1) => n_ahbso_hrdata(1),
6107 
      n_ahbso_hrdata(2) => n_ahbso_hrdata(2),
6108 
      n_ahbso_hrdata(3) => n_ahbso_hrdata(3),
6109 
      n_ahbso_hrdata(4) => n_ahbso_hrdata(4),
6110 
      n_ahbso_hrdata(5) => n_ahbso_hrdata(5),
6111 
      n_ahbso_hrdata(6) => n_ahbso_hrdata(6),
6112 
      n_ahbso_hrdata(7) => n_ahbso_hrdata(7),
6113 
      n_ahbso_hrdata(8) => n_ahbso_hrdata(8),
6114 
      n_ahbso_hrdata(9) => n_ahbso_hrdata(9),
6115 
      n_ahbso_hrdata(10) => n_ahbso_hrdata(10),
6116 
      n_ahbso_hrdata(11) => n_ahbso_hrdata(11),
6117 
      n_ahbso_hrdata(12) => n_ahbso_hrdata(12),
6118 
      n_ahbso_hrdata(13) => n_ahbso_hrdata(13),
6119 
      n_ahbso_hrdata(14) => n_ahbso_hrdata(14),
6120 
      n_ahbso_hrdata(15) => n_ahbso_hrdata(15),
6121 
      n_ahbso_hrdata(16) => n_ahbso_hrdata(16),
6122 
      n_ahbso_hrdata(17) => n_ahbso_hrdata(17),
6123 
      n_ahbso_hrdata(18) => n_ahbso_hrdata(18),
6124 
      n_ahbso_hrdata(19) => n_ahbso_hrdata(19),
6125 
      n_ahbso_hrdata(20) => n_ahbso_hrdata(20),
6126 
      n_ahbso_hrdata(21) => n_ahbso_hrdata(21),
6127 
      n_ahbso_hrdata(22) => n_ahbso_hrdata(22),
6128 
      n_ahbso_hrdata(23) => n_ahbso_hrdata(23),
6129 
      n_ahbso_hrdata(24) => n_ahbso_hrdata(24),
6130 
      n_ahbso_hrdata(25) => n_ahbso_hrdata(25),
6131 
      n_ahbso_hrdata(26) => n_ahbso_hrdata(26),
6132 
      n_ahbso_hrdata(27) => n_ahbso_hrdata(27),
6133 
      n_ahbso_hrdata(28) => n_ahbso_hrdata(28),
6134 
      n_ahbso_hrdata(29) => n_ahbso_hrdata(29),
6135 
      n_ahbso_hrdata(30) => n_ahbso_hrdata(30),
6136 
      n_ahbso_hrdata(31) => n_ahbso_hrdata(31),
6137 
      iows_0 => WRP_R_MCFG1_IOWS(0),
6138 
      iows_3 => WRP_R_MCFG1_IOWS(3),
6139 
      romwws_0 => WRP_R_MCFG1_ROMWWS(0),
6140 
      romwws_3 => WRP_R_MCFG1_ROMWWS(3),
6141 
      romrws_0 => WRP_R_MCFG1_ROMRWS(0),
6142 
      romrws_3 => WRP_R_MCFG1_ROMRWS(3),
6143 
      NoName_cnst(0) => WRP_NONAME_CNST(0),
6144 
      n_sri_bwidth(0) => n_sri_bwidth(0),
6145 
      n_sri_bwidth(1) => n_sri_bwidth(1),
6146 
      n_apbi_pwdata_19 => n_apbi_pwdata(19),
6147 
      n_apbi_pwdata_11 => n_apbi_pwdata(11),
6148 
      n_apbi_pwdata_9 => n_apbi_pwdata(9),
6149 
      n_apbi_pwdata_8 => n_apbi_pwdata(8),
6150 
      n_apbi_pwdata_23 => n_apbi_pwdata(23),
6151 
      n_apbi_pwdata_22 => n_apbi_pwdata(22),
6152 
      n_apbi_pwdata_21 => n_apbi_pwdata(21),
6153 
      n_apbi_pwdata_20 => n_apbi_pwdata(20),
6154 
      n_apbi_pwdata_3 => n_apbi_pwdata(3),
6155 
      n_apbi_pwdata_2 => n_apbi_pwdata(2),
6156 
      n_apbi_pwdata_1 => n_apbi_pwdata(1),
6157 
      n_apbi_pwdata_0 => n_apbi_pwdata(0),
6158 
      n_apbi_pwdata_7 => n_apbi_pwdata(7),
6159 
      n_apbi_pwdata_6 => n_apbi_pwdata(6),
6160 
      n_apbi_pwdata_5 => n_apbi_pwdata(5),
6161 
      n_apbi_pwdata_4 => n_apbi_pwdata(4),
6162 
      n_apbi_psel(0) => n_apbi_psel(0),
6163 
      n_apbi_paddr(2) => n_apbi_paddr(2),
6164 
      n_apbi_paddr(3) => n_apbi_paddr(3),
6165 
      n_apbi_paddr(4) => n_apbi_paddr(4),
6166 
      n_apbi_paddr(5) => n_apbi_paddr(5),
6167 
      n_apbo_prdata_0 => n_apbo_prdata(0),
6168 
      n_apbo_prdata_4 => n_apbo_prdata(4),
6169 
      n_apbo_prdata_20 => n_apbo_prdata(20),
6170 
      n_apbo_prdata_23 => n_apbo_prdata(23),
6171 
      n_apbo_prdata_22 => n_apbo_prdata(22),
6172 
      n_apbo_prdata_21 => n_apbo_prdata(21),
6173 
      n_apbo_prdata_19 => n_apbo_prdata(19),
6174 
      n_apbo_prdata_7 => n_apbo_prdata(7),
6175 
      n_apbo_prdata_6 => n_apbo_prdata(6),
6176 
      n_apbo_prdata_5 => n_apbo_prdata(5),
6177 
      n_apbo_prdata_3 => n_apbo_prdata(3),
6178 
      n_apbo_prdata_2 => n_apbo_prdata(2),
6179 
      n_apbo_prdata_1 => n_apbo_prdata(1),
6180 
      n_apbo_prdata_11 => n_apbo_prdata(11),
6181 
      n_apbo_prdata_9 => n_apbo_prdata(9),
6182 
      n_apbo_prdata_8 => n_apbo_prdata(8),
6183 
      n_apbo_prdata_28 => n_apbo_prdata(28),
6184 
      n_sro_romsn(0) => N_SRO_ROMSN_0_INT_260,
6185 
      n_ahbsi_hsel(0) => n_ahbsi_hsel(0),
6186 
      prstate_fast(2) => WRP_R_PRSTATE_FAST(2),
6187 
      n_ahbsi_htrans(0) => n_ahbsi_htrans(0),
6188 
      n_ahbsi_htrans(1) => n_ahbsi_htrans(1),
6189 
      ssrstate_1_m1(3) => WRP_CTRL_V_SSRSTATE_1_M1(3),
6190 
      ssrstate_1_m1(4) => WRP_CTRL_V_SSRSTATE_1_M1(4),
6191 
      hsel_1(0) => WRP_UN1_V_HSEL_1(0),
6192 
      hmbsel_4(1) => WRP_CTRL_V_HMBSEL_4(1),
6193 
      n_sro_bdrive(3) => N_SRO_BDRIVE_3_INT_269_INT_270_INT_271_INT_272,
6194 
      ws_1_0 => WRP_CTRL_V_WS_1(0),
6195 
      ws_1_3 => WRP_CTRL_V_WS_1(3),
6196 
      ws(0) => WRP_R_WS(0),
6197 
      ws(1) => WRP_R_WS(1),
6198 
      ws(2) => WRP_R_WS(2),
6199 
      ws(3) => WRP_R_WS(3),
6200 
      ssrstate_1_2 => WRP_CTRL_V_SSRSTATE_1(4),
6201 
      n_ahbsi_haddr(0) => n_ahbsi_haddr(0),
6202 
      n_ahbsi_haddr(1) => n_ahbsi_haddr(1),
6203 
      n_ahbsi_haddr(2) => n_ahbsi_haddr(2),
6204 
      n_ahbsi_haddr(3) => n_ahbsi_haddr(3),
6205 
      n_ahbsi_haddr(4) => n_ahbsi_haddr(4),
6206 
      n_ahbsi_haddr(5) => n_ahbsi_haddr(5),
6207 
      n_ahbsi_haddr(6) => n_ahbsi_haddr(6),
6208 
      n_ahbsi_haddr(7) => n_ahbsi_haddr(7),
6209 
      n_ahbsi_haddr(8) => n_ahbsi_haddr(8),
6210 
      n_ahbsi_haddr(9) => n_ahbsi_haddr(9),
6211 
      n_ahbsi_haddr(10) => n_ahbsi_haddr(10),
6212 
      n_ahbsi_haddr(11) => n_ahbsi_haddr(11),
6213 
      n_ahbsi_haddr(12) => n_ahbsi_haddr(12),
6214 
      n_ahbsi_haddr(13) => n_ahbsi_haddr(13),
6215 
      n_ahbsi_haddr(14) => n_ahbsi_haddr(14),
6216 
      n_ahbsi_haddr(15) => n_ahbsi_haddr(15),
6217 
      n_ahbsi_haddr(16) => n_ahbsi_haddr(16),
6218 
      n_ahbsi_haddr(17) => n_ahbsi_haddr(17),
6219 
      n_ahbsi_haddr(18) => n_ahbsi_haddr(18),
6220 
      n_ahbsi_haddr(19) => n_ahbsi_haddr(19),
6221 
      n_ahbsi_haddr(20) => n_ahbsi_haddr(20),
6222 
      n_ahbsi_haddr(21) => n_ahbsi_haddr(21),
6223 
      n_ahbsi_haddr(22) => n_ahbsi_haddr(22),
6224 
      n_ahbsi_haddr(23) => n_ahbsi_haddr(23),
6225 
      n_ahbsi_haddr(24) => n_ahbsi_haddr(24),
6226 
      n_ahbsi_haddr(25) => n_ahbsi_haddr(25),
6227 
      n_ahbsi_haddr(26) => n_ahbsi_haddr(26),
6228 
      n_ahbsi_haddr(27) => n_ahbsi_haddr(27),
6229 
      n_ahbsi_haddr(28) => n_ahbsi_haddr(28),
6230 
      n_ahbsi_haddr(29) => n_ahbsi_haddr(29),
6231 
      n_ahbsi_haddr(30) => n_ahbsi_haddr(30),
6232 
      n_ahbsi_haddr(31) => n_ahbsi_haddr(31),
6233 
      n_ahbsi_hmbsel(0) => n_ahbsi_hmbsel(0),
6234 
      n_ahbsi_hmbsel(1) => n_ahbsi_hmbsel(1),
6235 
      n_ahbsi_hmbsel(2) => n_ahbsi_hmbsel(2),
6236 
      n_sri_data(0) => n_sri_data(0),
6237 
      n_sri_data(1) => n_sri_data(1),
6238 
      n_sri_data(2) => n_sri_data(2),
6239 
      n_sri_data(3) => n_sri_data(3),
6240 
      n_sri_data(4) => n_sri_data(4),
6241 
      n_sri_data(5) => n_sri_data(5),
6242 
      n_sri_data(6) => n_sri_data(6),
6243 
      n_sri_data(7) => n_sri_data(7),
6244 
      n_sri_data(8) => n_sri_data(8),
6245 
      n_sri_data(9) => n_sri_data(9),
6246 
      n_sri_data(10) => n_sri_data(10),
6247 
      n_sri_data(11) => n_sri_data(11),
6248 
      n_sri_data(12) => n_sri_data(12),
6249 
      n_sri_data(13) => n_sri_data(13),
6250 
      n_sri_data(14) => n_sri_data(14),
6251 
      n_sri_data(15) => n_sri_data(15),
6252 
      n_sri_data(16) => n_sri_data(16),
6253 
      n_sri_data(17) => n_sri_data(17),
6254 
      n_sri_data(18) => n_sri_data(18),
6255 
      n_sri_data(19) => n_sri_data(19),
6256 
      n_sri_data(20) => n_sri_data(20),
6257 
      n_sri_data(21) => n_sri_data(21),
6258 
      n_sri_data(22) => n_sri_data(22),
6259 
      n_sri_data(23) => n_sri_data(23),
6260 
      n_sri_data(24) => n_sri_data(24),
6261 
      n_sri_data(25) => n_sri_data(25),
6262 
      n_sri_data(26) => n_sri_data(26),
6263 
      n_sri_data(27) => n_sri_data(27),
6264 
      n_sri_data(28) => n_sri_data(28),
6265 
      n_sri_data(29) => n_sri_data(29),
6266 
      n_sri_data(30) => n_sri_data(30),
6267 
      n_sri_data(31) => n_sri_data(31),
6268 
      ssrstate(0) => WRP_R_SSRSTATE(0),
6269 
      ssrstate(1) => WRP_R_SSRSTATE(1),
6270 
      ssrstate(2) => WRP_R_SSRSTATE(2),
6271 
      ssrstate(3) => WRP_R_SSRSTATE(3),
6272 
      ssrstate(4) => WRP_R_SSRSTATE(4),
6273 
      n_ahbsi_hwdata(0) => n_ahbsi_hwdata(0),
6274 
      n_ahbsi_hwdata(1) => n_ahbsi_hwdata(1),
6275 
      n_ahbsi_hwdata(2) => n_ahbsi_hwdata(2),
6276 
      n_ahbsi_hwdata(3) => n_ahbsi_hwdata(3),
6277 
      n_ahbsi_hwdata(4) => n_ahbsi_hwdata(4),
6278 
      n_ahbsi_hwdata(5) => n_ahbsi_hwdata(5),
6279 
      n_ahbsi_hwdata(6) => n_ahbsi_hwdata(6),
6280 
      n_ahbsi_hwdata(7) => n_ahbsi_hwdata(7),
6281 
      n_ahbsi_hwdata(8) => n_ahbsi_hwdata(8),
6282 
      n_ahbsi_hwdata(9) => n_ahbsi_hwdata(9),
6283 
      n_ahbsi_hwdata(10) => n_ahbsi_hwdata(10),
6284 
      n_ahbsi_hwdata(11) => n_ahbsi_hwdata(11),
6285 
      n_ahbsi_hwdata(12) => n_ahbsi_hwdata(12),
6286 
      n_ahbsi_hwdata(13) => n_ahbsi_hwdata(13),
6287 
      n_ahbsi_hwdata(14) => n_ahbsi_hwdata(14),
6288 
      n_ahbsi_hwdata(15) => n_ahbsi_hwdata(15),
6289 
      n_ahbsi_hwdata(16) => n_ahbsi_hwdata(16),
6290 
      n_ahbsi_hwdata(17) => n_ahbsi_hwdata(17),
6291 
      n_ahbsi_hwdata(18) => n_ahbsi_hwdata(18),
6292 
      n_ahbsi_hwdata(19) => n_ahbsi_hwdata(19),
6293 
      n_ahbsi_hwdata(20) => n_ahbsi_hwdata(20),
6294 
      n_ahbsi_hwdata(21) => n_ahbsi_hwdata(21),
6295 
      n_ahbsi_hwdata(22) => n_ahbsi_hwdata(22),
6296 
      n_ahbsi_hwdata(23) => n_ahbsi_hwdata(23),
6297 
      n_ahbsi_hwdata(24) => n_ahbsi_hwdata(24),
6298 
      n_ahbsi_hwdata(25) => n_ahbsi_hwdata(25),
6299 
      n_ahbsi_hwdata(26) => n_ahbsi_hwdata(26),
6300 
      n_ahbsi_hwdata(27) => n_ahbsi_hwdata(27),
6301 
      n_ahbsi_hwdata(28) => n_ahbsi_hwdata(28),
6302 
      n_ahbsi_hwdata(29) => n_ahbsi_hwdata(29),
6303 
      n_ahbsi_hwdata(30) => n_ahbsi_hwdata(30),
6304 
      n_ahbsi_hwdata(31) => n_ahbsi_hwdata(31),
6305 
      n_ahbsi_hsize(0) => n_ahbsi_hsize(0),
6306 
      n_ahbsi_hsize(1) => n_ahbsi_hsize(1),
6307 
      size(0) => WRP_R_SIZE(0),
6308 
      size(1) => WRP_R_SIZE(1),
6309 
      n_sro_data(0) => n_sro_data(0),
6310 
      n_sro_data(1) => n_sro_data(1),
6311 
      n_sro_data(2) => n_sro_data(2),
6312 
      n_sro_data(3) => n_sro_data(3),
6313 
      n_sro_data(4) => n_sro_data(4),
6314 
      n_sro_data(5) => n_sro_data(5),
6315 
      n_sro_data(6) => n_sro_data(6),
6316 
      n_sro_data(7) => n_sro_data(7),
6317 
      n_sro_data(8) => n_sro_data(8),
6318 
      n_sro_data(9) => n_sro_data(9),
6319 
      n_sro_data(10) => n_sro_data(10),
6320 
      n_sro_data(11) => n_sro_data(11),
6321 
      n_sro_data(12) => n_sro_data(12),
6322 
      n_sro_data(13) => n_sro_data(13),
6323 
      n_sro_data(14) => n_sro_data(14),
6324 
      n_sro_data(15) => n_sro_data(15),
6325 
      n_sro_data(16) => n_sro_data(16),
6326 
      n_sro_data(17) => n_sro_data(17),
6327 
      n_sro_data(18) => n_sro_data(18),
6328 
      n_sro_data(19) => n_sro_data(19),
6329 
      n_sro_data(20) => n_sro_data(20),
6330 
      n_sro_data(21) => n_sro_data(21),
6331 
      n_sro_data(22) => n_sro_data(22),
6332 
      n_sro_data(23) => n_sro_data(23),
6333 
      n_sro_data(24) => n_sro_data(24),
6334 
      n_sro_data(25) => n_sro_data(25),
6335 
      n_sro_data(26) => n_sro_data(26),
6336 
      n_sro_data(27) => n_sro_data(27),
6337 
      n_sro_data(28) => n_sro_data(28),
6338 
      n_sro_data(29) => n_sro_data(29),
6339 
      n_sro_data(30) => n_sro_data(30),
6340 
      n_sro_data(31) => n_sro_data(31),
6341 
      n_sro_ramsn(0) => n_sro_ramsn(0),
6342 
      n_sro_wrn(0) => n_sro_wrn(0),
6343 
      n_sro_wrn(1) => n_sro_wrn(1),
6344 
      n_sro_wrn(2) => n_sro_wrn(2),
6345 
      n_sro_wrn(3) => n_sro_wrn(3),
6346 
      haddr_0 => WRP_HADDR(1),
6347 
      bwn_1_0_o3_0 => WRP_CTRL_V_BWN_1_0_O3(0),
6348 
      hsize_1(1) => WRP_CTRL_HSIZE_1(1),
6349 
      prstate_1_i_o4_s(2) => WRP_V_PRSTATE_1_I_O4_S(2),
6350 
      prstate(0) => WRP_R_PRSTATE(0),
6351 
      prstate(1) => WRP_R_PRSTATE(1),
6352 
      prstate(2) => WRP_R_PRSTATE(2),
6353 
      prstate(3) => WRP_R_PRSTATE(3),
6354 
      prstate(4) => WRP_R_PRSTATE(4),
6355 
      prstate(5) => WRP_R_PRSTATE(5),
6356 
      hmbsel(0) => WRP_R_HMBSEL(0),
6357 
      hmbsel(1) => WRP_R_HMBSEL(1),
6358 
      hmbsel(2) => WRP_R_HMBSEL(2),
6359 
      n_sro_address(0) => N_SRO_ADDRESS_0_INT_172,
6360 
      n_sro_address(1) => N_SRO_ADDRESS_1_INT_173,
6361 
      n_sro_address(2) => n_sro_address(2),
6362 
      n_sro_address(3) => n_sro_address(3),
6363 
      n_sro_address(4) => n_sro_address(4),
6364 
      n_sro_address(5) => n_sro_address(5),
6365 
      n_sro_address(6) => n_sro_address(6),
6366 
      n_sro_address(7) => n_sro_address(7),
6367 
      n_sro_address(8) => n_sro_address(8),
6368 
      n_sro_address(9) => n_sro_address(9),
6369 
      n_sro_address(10) => n_sro_address(10),
6370 
      n_sro_address(11) => n_sro_address(11),
6371 
      n_sro_address(12) => n_sro_address(12),
6372 
      n_sro_address(13) => n_sro_address(13),
6373 
      n_sro_address(14) => n_sro_address(14),
6374 
      n_sro_address(15) => n_sro_address(15),
6375 
      n_sro_address(16) => n_sro_address(16),
6376 
      n_sro_address(17) => n_sro_address(17),
6377 
      n_sro_address(18) => n_sro_address(18),
6378 
      n_sro_address(19) => n_sro_address(19),
6379 
      n_sro_address(20) => n_sro_address(20),
6380 
      n_sro_address(21) => n_sro_address(21),
6381 
      n_sro_address(22) => n_sro_address(22),
6382 
      n_sro_address(23) => n_sro_address(23),
6383 
      n_sro_address(24) => n_sro_address(24),
6384 
      n_sro_address(25) => n_sro_address(25),
6385 
      n_sro_address(26) => n_sro_address(26),
6386 
      n_sro_address(27) => n_sro_address(27),
6387 
      n_sro_address(28) => n_sro_address(28),
6388 
      n_sro_address(29) => n_sro_address(29),
6389 
      n_sro_address(30) => n_sro_address(30),
6390 
      n_sro_address(31) => n_sro_address(31),
6391 
      hready_2 => WRP_CTRL_V_HREADY_2,
6392 
      n_ahbso_hready => n_ahbso_hready,
6393 
      ssrhready_8 => WRP_CTRL_V_SSRHREADY_8,
6394 
      loadcount => WRP_R_LOADCOUNT,
6395 
      n_sro_writen => n_sro_writen,
6396 
      ssrstatec => WRP_R_SSRSTATEC,
6397 
      prhready => WRP_R_PRHREADY,
6398 
      d_m2_0_a2_0 => D_M2_0_A2_0,
6399 
      ssrstate17_2_0_m6_i_a3_a2 => SSRSTATE17_2_0_M6_I_A3_A2,
6400 
      N_319_1 => N_319_1,
6401 
      ws_0_sqmuxa_c => WRP_V_WS_0_SQMUXA_C,
6402 
      N_365 => N_365,
6403 
      ws_0_sqmuxa_0_c => WRP_V_WS_0_SQMUXA_0_C,
6404 
      ws_2_sqmuxa_3_0_4 => WRP_V_WS_2_SQMUXA_3_0_4,
6405 
      change_1_sqmuxa_0 => WRP_UN1_V_CHANGE_1_SQMUXA_0,
6406 
      d16mux_0_sqmuxa => WRP_V_D16MUX_0_SQMUXA,
6407 
      ssrstate_2_sqmuxa_1 => WRP_V_SSRSTATE_2_SQMUXA_1,
6408 
      un7_bus16en => WRP_CTRL_UN7_BUS16EN,
6409 
      N_646 => N_646,
6410 
      loadcount_1_sqmuxa => WRP_V_LOADCOUNT_1_SQMUXA,
6411 
      ssrstate_1_sqmuxa_1_0_m3_0_1 => WRP_UN1_V_SSRSTATE_1_SQMUXA_1_0_M3_0_1,
6412 
      n_apbi_penable => n_apbi_penable,
6413 
      n_apbi_pwrite => n_apbi_pwrite,
6414 
      d_m1_e_0_0 => D_M1_E_0_0,
6415 
      hsel_1_0_L3 => HSEL_1_0_L3,
6416 
      ssrhready_8_f0_L8 => SSRHREADY_8_F0_L8,
6417 
      ssrstate_1_sqmuxa_1 => WRP_V_SSRSTATE_1_SQMUXA_1,
6418 
      ssrhready => WRP_R_SSRHREADY,
6419 
      ssrhready_8_f0_L5 => SSRHREADY_8_F0_L5,
6420 
      ssrstate17_1_xx_mm_N_4 => WRP_CTRL_UN1_V_SSRSTATE17_1_XX_MM_N_4,
6421 
      ws_1_sqmuxa => WRP_V_WS_1_SQMUXA,
6422 
      ws_4_sqmuxa_0 => WRP_V_WS_4_SQMUXA_0,
6423 
      ws_2_sqmuxa_0 => WRP_V_WS_2_SQMUXA_0,
6424 
      ssrstate17_2_0_m6_i_1 => WRP_UN1_V_SSRSTATE17_2_0_M6_I_1,
6425 
      ws_2_sqmuxa_3_0_x => WS_2_SQMUXA_3_0_X,
6426 
      ws_3_sqmuxa_1 => WRP_V_WS_3_SQMUXA_1,
6427 
      ws_2_sqmuxa_3_0_2 => WRP_V_WS_2_SQMUXA_3_0_2,
6428 
      ssrstate_2_i => WRP_UN1_R_SSRSTATE_2_I,
6429 
      ws_2_sqmuxa_3_d => WRP_V_WS_2_SQMUXA_3_D,
6430 
      ws_0_sqmuxa_1 => WRP_V_WS_0_SQMUXA_1,
6431 
      g0_30 => G0_30,
6432 
      hsel_4 => WRP_CTRL_V_HSEL_4,
6433 
      n_ahbsi_hready => n_ahbsi_hready,
6434 
      hsel => WRP_R_HSEL,
6435 
      g0_25 => G0_25,
6436 
      bwn_0_sqmuxa_1 => WRP_V_BWN_0_SQMUXA_1,
6437 
      prstate_2_rep1 => WRP_R_PRSTATE_2_REP1,
6438 
      N_662 => N_662,
6439 
      ssrstate_6_sqmuxa => WRP_V_SSRSTATE_6_SQMUXA,
6440 
      g0_52_x1 => G0_52_X1,
6441 
      g0_52_x0 => G0_52_X0,
6442 
      ssrhready_2_sqmuxa_0_0 => WRP_V_SSRHREADY_2_SQMUXA_0_0,
6443 
      change_1_sqmuxa_N_3 => WRP_V_CHANGE_1_SQMUXA_N_3,
6444 
      ssrstate6_xx_mm_m3 => SSRSTATE6_XX_MM_M3,
6445 
      ssrstate6_1_d_0_L1 => SSRSTATE6_1_D_0_L1,
6446 
      N_656 => N_656,
6447 
      hsel_5 => WRP_CTRL_V_HSEL_5,
6448 
      change_3_f0 => WRP_CTRL_V_CHANGE_3_F0,
6449 
      un1_ahbsi => WRP_CTRL_UN1_AHBSI,
6450 
      change => WRP_R_CHANGE,
6451 
      n_ahbsi_hwrite => n_ahbsi_hwrite,
6452 
      N_574_i => N_574_I,
6453 
      n_sro_iosn => N_SRO_IOSN_INT_259,
6454 
      N_618_i => N_618_I,
6455 
      clk => clk,
6456 
      n_sro_oen => N_SRO_OEN_INT_245_INT_246_INT_247_INT_248_INT_249_INT_250_INT_251_INT_252_INT_268,
6457 
      rst => rst,
6458 
      bwn_1_sqmuxa_2_d => WRP_UN1_V_BWN_1_SQMUXA_2_D,
6459 
      bwn_1_sqmuxa_2_d_0_2 => WRP_UN1_V_BWN_1_SQMUXA_2_D_0_2,
6460 
      ssrstate_2_sqmuxa_i => WRP_UN1_V_SSRSTATE_2_SQMUXA_I,
6461 
      g0_23 => G0_23,
6462 
      N_371 => N_371,
6463 
      loadcount_7 => WRP_CTRL_V_LOADCOUNT_7,
6464 
      bus16en => WRP_CTRL_BUS16EN,
6465 
      d16muxc_0_4 => WRP_R_D16MUXC_0_4,
6466 
      change_3_f1_d_0_0 => WRP_CTRL_V_CHANGE_3_F1_D_0_0,
6467 
      g0_1_0 => G0_1_0,
6468 
      g0_44 => G0_44);
6469 
  II_GND: GND port map (
6470 
      G => NN_2);
6471 
  II_VCC: VCC port map (
6472 
      P => NN_1);
6473 
  n_ahbso_hresp(0) <= NN_2;
6474 
  n_ahbso_hresp(1) <= NN_2;
6475 
  n_ahbso_hsplit(0) <= NN_2;
6476 
  n_ahbso_hsplit(1) <= NN_2;
6477 
  n_ahbso_hsplit(2) <= NN_2;
6478 
  n_ahbso_hsplit(3) <= NN_2;
6479 
  n_ahbso_hsplit(4) <= NN_2;
6480 
  n_ahbso_hsplit(5) <= NN_2;
6481 
  n_ahbso_hsplit(6) <= NN_2;
6482 
  n_ahbso_hsplit(7) <= NN_2;
6483 
  n_ahbso_hsplit(8) <= NN_2;
6484 
  n_ahbso_hsplit(9) <= NN_2;
6485 
  n_ahbso_hsplit(10) <= NN_2;
6486 
  n_ahbso_hsplit(11) <= NN_2;
6487 
  n_ahbso_hsplit(12) <= NN_2;
6488 
  n_ahbso_hsplit(13) <= NN_2;
6489 
  n_ahbso_hsplit(14) <= NN_2;
6490 
  n_ahbso_hsplit(15) <= NN_2;
6491 
  n_ahbso_hcache <= NN_1;
6492 
  n_ahbso_hirq(0) <= NN_2;
6493 
  n_ahbso_hirq(1) <= NN_2;
6494 
  n_ahbso_hirq(2) <= NN_2;
6495 
  n_ahbso_hirq(3) <= NN_2;
6496 
  n_ahbso_hirq(4) <= NN_2;
6497 
  n_ahbso_hirq(5) <= NN_2;
6498 
  n_ahbso_hirq(6) <= NN_2;
6499 
  n_ahbso_hirq(7) <= NN_2;
6500 
  n_ahbso_hirq(8) <= NN_2;
6501 
  n_ahbso_hirq(9) <= NN_2;
6502 
  n_ahbso_hirq(10) <= NN_2;
6503 
  n_ahbso_hirq(11) <= NN_2;
6504 
  n_ahbso_hirq(12) <= NN_2;
6505 
  n_ahbso_hirq(13) <= NN_2;
6506 
  n_ahbso_hirq(14) <= NN_2;
6507 
  n_ahbso_hirq(15) <= NN_2;
6508 
  n_ahbso_hirq(16) <= NN_2;
6509 
  n_ahbso_hirq(17) <= NN_2;
6510 
  n_ahbso_hirq(18) <= NN_2;
6511 
  n_ahbso_hirq(19) <= NN_2;
6512 
  n_ahbso_hirq(20) <= NN_2;
6513 
  n_ahbso_hirq(21) <= NN_2;
6514 
  n_ahbso_hirq(22) <= NN_2;
6515 
  n_ahbso_hirq(23) <= NN_2;
6516 
  n_ahbso_hirq(24) <= NN_2;
6517 
  n_ahbso_hirq(25) <= NN_2;
6518 
  n_ahbso_hirq(26) <= NN_2;
6519 
  n_ahbso_hirq(27) <= NN_2;
6520 
  n_ahbso_hirq(28) <= NN_2;
6521 
  n_ahbso_hirq(29) <= NN_2;
6522 
  n_ahbso_hirq(30) <= NN_2;
6523 
  n_ahbso_hirq(31) <= NN_2;
6524 
  n_apbo_prdata(10) <= NN_2;
6525 
  n_apbo_prdata(12) <= NN_2;
6526 
  n_apbo_prdata(13) <= NN_2;
6527 
  n_apbo_prdata(14) <= NN_2;
6528 
  n_apbo_prdata(15) <= NN_2;
6529 
  n_apbo_prdata(16) <= NN_2;
6530 
  n_apbo_prdata(17) <= NN_2;
6531 
  n_apbo_prdata(18) <= NN_2;
6532 
  n_apbo_prdata(24) <= NN_2;
6533 
  n_apbo_prdata(25) <= NN_2;
6534 
  n_apbo_prdata(26) <= NN_2;
6535 
  n_apbo_prdata(27) <= NN_2;
6536 
  n_apbo_prdata(29) <= NN_2;
6537 
  n_apbo_prdata(30) <= NN_2;
6538 
  n_apbo_prdata(31) <= NN_2;
6539 
  n_apbo_pirq(0) <= NN_2;
6540 
  n_apbo_pirq(1) <= NN_2;
6541 
  n_apbo_pirq(2) <= NN_2;
6542 
  n_apbo_pirq(3) <= NN_2;
6543 
  n_apbo_pirq(4) <= NN_2;
6544 
  n_apbo_pirq(5) <= NN_2;
6545 
  n_apbo_pirq(6) <= NN_2;
6546 
  n_apbo_pirq(7) <= NN_2;
6547 
  n_apbo_pirq(8) <= NN_2;
6548 
  n_apbo_pirq(9) <= NN_2;
6549 
  n_apbo_pirq(10) <= NN_2;
6550 
  n_apbo_pirq(11) <= NN_2;
6551 
  n_apbo_pirq(12) <= NN_2;
6552 
  n_apbo_pirq(13) <= NN_2;
6553 
  n_apbo_pirq(14) <= NN_2;
6554 
  n_apbo_pirq(15) <= NN_2;
6555 
  n_apbo_pirq(16) <= NN_2;
6556 
  n_apbo_pirq(17) <= NN_2;
6557 
  n_apbo_pirq(18) <= NN_2;
6558 
  n_apbo_pirq(19) <= NN_2;
6559 
  n_apbo_pirq(20) <= NN_2;
6560 
  n_apbo_pirq(21) <= NN_2;
6561 
  n_apbo_pirq(22) <= NN_2;
6562 
  n_apbo_pirq(23) <= NN_2;
6563 
  n_apbo_pirq(24) <= NN_2;
6564 
  n_apbo_pirq(25) <= NN_2;
6565 
  n_apbo_pirq(26) <= NN_2;
6566 
  n_apbo_pirq(27) <= NN_2;
6567 
  n_apbo_pirq(28) <= NN_2;
6568 
  n_apbo_pirq(29) <= NN_2;
6569 
  n_apbo_pirq(30) <= NN_2;
6570 
  n_apbo_pirq(31) <= NN_2;
6571 
  n_sro_address(0) <= N_SRO_ADDRESS_0_INT_172;
6572 
  n_sro_address(1) <= N_SRO_ADDRESS_1_INT_173;
6573 
  n_sro_sddata(0) <= NN_2;
6574 
  n_sro_sddata(1) <= NN_2;
6575 
  n_sro_sddata(2) <= NN_2;
6576 
  n_sro_sddata(3) <= NN_2;
6577 
  n_sro_sddata(4) <= NN_2;
6578 
  n_sro_sddata(5) <= NN_2;
6579 
  n_sro_sddata(6) <= NN_2;
6580 
  n_sro_sddata(7) <= NN_2;
6581 
  n_sro_sddata(8) <= NN_2;
6582 
  n_sro_sddata(9) <= NN_2;
6583 
  n_sro_sddata(10) <= NN_2;
6584 
  n_sro_sddata(11) <= NN_2;
6585 
  n_sro_sddata(12) <= NN_2;
6586 
  n_sro_sddata(13) <= NN_2;
6587 
  n_sro_sddata(14) <= NN_2;
6588 
  n_sro_sddata(15) <= NN_2;
6589 
  n_sro_sddata(16) <= NN_2;
6590 
  n_sro_sddata(17) <= NN_2;
6591 
  n_sro_sddata(18) <= NN_2;
6592 
  n_sro_sddata(19) <= NN_2;
6593 
  n_sro_sddata(20) <= NN_2;
6594 
  n_sro_sddata(21) <= NN_2;
6595 
  n_sro_sddata(22) <= NN_2;
6596 
  n_sro_sddata(23) <= NN_2;
6597 
  n_sro_sddata(24) <= NN_2;
6598 
  n_sro_sddata(25) <= NN_2;
6599 
  n_sro_sddata(26) <= NN_2;
6600 
  n_sro_sddata(27) <= NN_2;
6601 
  n_sro_sddata(28) <= NN_2;
6602 
  n_sro_sddata(29) <= NN_2;
6603 
  n_sro_sddata(30) <= NN_2;
6604 
  n_sro_sddata(31) <= NN_2;
6605 
  n_sro_sddata(32) <= NN_2;
6606 
  n_sro_sddata(33) <= NN_2;
6607 
  n_sro_sddata(34) <= NN_2;
6608 
  n_sro_sddata(35) <= NN_2;
6609 
  n_sro_sddata(36) <= NN_2;
6610 
  n_sro_sddata(37) <= NN_2;
6611 
  n_sro_sddata(38) <= NN_2;
6612 
  n_sro_sddata(39) <= NN_2;
6613 
  n_sro_sddata(40) <= NN_2;
6614 
  n_sro_sddata(41) <= NN_2;
6615 
  n_sro_sddata(42) <= NN_2;
6616 
  n_sro_sddata(43) <= NN_2;
6617 
  n_sro_sddata(44) <= NN_2;
6618 
  n_sro_sddata(45) <= NN_2;
6619 
  n_sro_sddata(46) <= NN_2;
6620 
  n_sro_sddata(47) <= NN_2;
6621 
  n_sro_sddata(48) <= NN_2;
6622 
  n_sro_sddata(49) <= NN_2;
6623 
  n_sro_sddata(50) <= NN_2;
6624 
  n_sro_sddata(51) <= NN_2;
6625 
  n_sro_sddata(52) <= NN_2;
6626 
  n_sro_sddata(53) <= NN_2;
6627 
  n_sro_sddata(54) <= NN_2;
6628 
  n_sro_sddata(55) <= NN_2;
6629 
  n_sro_sddata(56) <= NN_2;
6630 
  n_sro_sddata(57) <= NN_2;
6631 
  n_sro_sddata(58) <= NN_2;
6632 
  n_sro_sddata(59) <= NN_2;
6633 
  n_sro_sddata(60) <= NN_2;
6634 
  n_sro_sddata(61) <= NN_2;
6635 
  n_sro_sddata(62) <= NN_2;
6636 
  n_sro_sddata(63) <= NN_2;
6637 
  n_sro_ramsn(1) <= NN_1;
6638 
  n_sro_ramsn(2) <= NN_1;
6639 
  n_sro_ramsn(3) <= NN_1;
6640 
  n_sro_ramsn(4) <= NN_1;
6641 
  n_sro_ramsn(5) <= NN_1;
6642 
  n_sro_ramsn(6) <= NN_1;
6643 
  n_sro_ramsn(7) <= NN_1;
6644 
  n_sro_ramoen(0) <= N_SRO_OEN_INT_245_INT_246_INT_247_INT_248_INT_249_INT_250_INT_251_INT_252_INT_268;
6645 
  n_sro_ramoen(1) <= N_SRO_OEN_INT_245_INT_246_INT_247_INT_248_INT_249_INT_250_INT_251_INT_252_INT_268;
6646 
  n_sro_ramoen(2) <= N_SRO_OEN_INT_245_INT_246_INT_247_INT_248_INT_249_INT_250_INT_251_INT_252_INT_268;
6647 
  n_sro_ramoen(3) <= N_SRO_OEN_INT_245_INT_246_INT_247_INT_248_INT_249_INT_250_INT_251_INT_252_INT_268;
6648 
  n_sro_ramoen(4) <= N_SRO_OEN_INT_245_INT_246_INT_247_INT_248_INT_249_INT_250_INT_251_INT_252_INT_268;
6649 
  n_sro_ramoen(5) <= N_SRO_OEN_INT_245_INT_246_INT_247_INT_248_INT_249_INT_250_INT_251_INT_252_INT_268;
6650 
  n_sro_ramoen(6) <= N_SRO_OEN_INT_245_INT_246_INT_247_INT_248_INT_249_INT_250_INT_251_INT_252_INT_268;
6651 
  n_sro_ramoen(7) <= N_SRO_OEN_INT_245_INT_246_INT_247_INT_248_INT_249_INT_250_INT_251_INT_252_INT_268;
6652 
  n_sro_ramn <= NN_2;
6653 
  n_sro_romn <= NN_2;
6654 
  n_sro_mben(0) <= NN_2;
6655 
  n_sro_mben(1) <= NN_2;
6656 
  n_sro_mben(2) <= NN_2;
6657 
  n_sro_mben(3) <= NN_2;
6658 
  n_sro_iosn <= N_SRO_IOSN_INT_259;
6659 
  n_sro_romsn(0) <= N_SRO_ROMSN_0_INT_260;
6660 
  n_sro_romsn(1) <= NN_1;
6661 
  n_sro_romsn(2) <= NN_1;
6662 
  n_sro_romsn(3) <= NN_1;
6663 
  n_sro_romsn(4) <= NN_1;
6664 
  n_sro_romsn(5) <= NN_1;
6665 
  n_sro_romsn(6) <= NN_1;
6666 
  n_sro_romsn(7) <= NN_1;
6667 
  n_sro_oen <= N_SRO_OEN_INT_245_INT_246_INT_247_INT_248_INT_249_INT_250_INT_251_INT_252_INT_268;
6668 
  n_sro_bdrive(0) <= N_SRO_BDRIVE_3_INT_269_INT_270_INT_271_INT_272;
6669 
  n_sro_bdrive(1) <= N_SRO_BDRIVE_3_INT_269_INT_270_INT_271_INT_272;
6670 
  n_sro_bdrive(2) <= N_SRO_BDRIVE_3_INT_269_INT_270_INT_271_INT_272;
6671 
  n_sro_bdrive(3) <= N_SRO_BDRIVE_3_INT_269_INT_270_INT_271_INT_272;
6672 
  n_sro_svbdrive(0) <= NN_2;
6673 
  n_sro_svbdrive(1) <= NN_2;
6674 
  n_sro_svbdrive(2) <= NN_2;
6675 
  n_sro_svbdrive(3) <= NN_2;
6676 
  n_sro_svbdrive(4) <= NN_2;
6677 
  n_sro_svbdrive(5) <= NN_2;
6678 
  n_sro_svbdrive(6) <= NN_2;
6679 
  n_sro_svbdrive(7) <= NN_2;
6680 
  n_sro_svbdrive(8) <= NN_2;
6681 
  n_sro_svbdrive(9) <= NN_2;
6682 
  n_sro_svbdrive(10) <= NN_2;
6683 
  n_sro_svbdrive(11) <= NN_2;
6684 
  n_sro_svbdrive(12) <= NN_2;
6685 
  n_sro_svbdrive(13) <= NN_2;
6686 
  n_sro_svbdrive(14) <= NN_2;
6687 
  n_sro_svbdrive(15) <= NN_2;
6688 
  n_sro_svbdrive(16) <= NN_2;
6689 
  n_sro_svbdrive(17) <= NN_2;
6690 
  n_sro_svbdrive(18) <= NN_2;
6691 
  n_sro_svbdrive(19) <= NN_2;
6692 
  n_sro_svbdrive(20) <= NN_2;
6693 
  n_sro_svbdrive(21) <= NN_2;
6694 
  n_sro_svbdrive(22) <= NN_2;
6695 
  n_sro_svbdrive(23) <= NN_2;
6696 
  n_sro_svbdrive(24) <= NN_2;
6697 
  n_sro_svbdrive(25) <= NN_2;
6698 
  n_sro_svbdrive(26) <= NN_2;
6699 
  n_sro_svbdrive(27) <= NN_2;
6700 
  n_sro_svbdrive(28) <= NN_2;
6701 
  n_sro_svbdrive(29) <= NN_2;
6702 
  n_sro_svbdrive(30) <= NN_2;
6703 
  n_sro_svbdrive(31) <= NN_2;
6704 
  n_sro_svbdrive(32) <= NN_2;
6705 
  n_sro_svbdrive(33) <= NN_2;
6706 
  n_sro_svbdrive(34) <= NN_2;
6707 
  n_sro_svbdrive(35) <= NN_2;
6708 
  n_sro_svbdrive(36) <= NN_2;
6709 
  n_sro_svbdrive(37) <= NN_2;
6710 
  n_sro_svbdrive(38) <= NN_2;
6711 
  n_sro_svbdrive(39) <= NN_2;
6712 
  n_sro_svbdrive(40) <= NN_2;
6713 
  n_sro_svbdrive(41) <= NN_2;
6714 
  n_sro_svbdrive(42) <= NN_2;
6715 
  n_sro_svbdrive(43) <= NN_2;
6716 
  n_sro_svbdrive(44) <= NN_2;
6717 
  n_sro_svbdrive(45) <= NN_2;
6718 
  n_sro_svbdrive(46) <= NN_2;
6719 
  n_sro_svbdrive(47) <= NN_2;
6720 
  n_sro_svbdrive(48) <= NN_2;
6721 
  n_sro_svbdrive(49) <= NN_2;
6722 
  n_sro_svbdrive(50) <= NN_2;
6723 
  n_sro_svbdrive(51) <= NN_2;
6724 
  n_sro_svbdrive(52) <= NN_2;
6725 
  n_sro_svbdrive(53) <= NN_2;
6726 
  n_sro_svbdrive(54) <= NN_2;
6727 
  n_sro_svbdrive(55) <= NN_2;
6728 
  n_sro_svbdrive(56) <= NN_2;
6729 
  n_sro_svbdrive(57) <= NN_2;
6730 
  n_sro_svbdrive(58) <= NN_2;
6731 
  n_sro_svbdrive(59) <= NN_2;
6732 
  n_sro_svbdrive(60) <= NN_2;
6733 
  n_sro_svbdrive(61) <= NN_2;
6734 
  n_sro_svbdrive(62) <= NN_2;
6735 
  n_sro_svbdrive(63) <= NN_2;
6736 
  n_sro_read <= NN_2;
6737 
  n_sro_sa(0) <= NN_2;
6738 
  n_sro_sa(1) <= NN_2;
6739 
  n_sro_sa(2) <= NN_2;
6740 
  n_sro_sa(3) <= NN_2;
6741 
  n_sro_sa(4) <= NN_2;
6742 
  n_sro_sa(5) <= NN_2;
6743 
  n_sro_sa(6) <= NN_2;
6744 
  n_sro_sa(7) <= NN_2;
6745 
  n_sro_sa(8) <= NN_2;
6746 
  n_sro_sa(9) <= NN_2;
6747 
  n_sro_sa(10) <= NN_2;
6748 
  n_sro_sa(11) <= NN_2;
6749 
  n_sro_sa(12) <= NN_2;
6750 
  n_sro_sa(13) <= NN_2;
6751 
  n_sro_sa(14) <= NN_2;
6752 
  n_sro_cb(0) <= NN_2;
6753 
  n_sro_cb(1) <= NN_2;
6754 
  n_sro_cb(2) <= NN_2;
6755 
  n_sro_cb(3) <= NN_2;
6756 
  n_sro_cb(4) <= NN_2;
6757 
  n_sro_cb(5) <= NN_2;
6758 
  n_sro_cb(6) <= NN_2;
6759 
  n_sro_cb(7) <= NN_2;
6760 
  n_sro_scb(0) <= NN_2;
6761 
  n_sro_scb(1) <= NN_2;
6762 
  n_sro_scb(2) <= NN_2;
6763 
  n_sro_scb(3) <= NN_2;
6764 
  n_sro_scb(4) <= NN_2;
6765 
  n_sro_scb(5) <= NN_2;
6766 
  n_sro_scb(6) <= NN_2;
6767 
  n_sro_scb(7) <= NN_2;
6768 
  n_sro_vcdrive(0) <= NN_2;
6769 
  n_sro_vcdrive(1) <= NN_2;
6770 
  n_sro_vcdrive(2) <= NN_2;
6771 
  n_sro_vcdrive(3) <= NN_2;
6772 
  n_sro_vcdrive(4) <= NN_2;
6773 
  n_sro_vcdrive(5) <= NN_2;
6774 
  n_sro_vcdrive(6) <= NN_2;
6775 
  n_sro_vcdrive(7) <= NN_2;
6776 
  n_sro_svcdrive(0) <= NN_2;
6777 
  n_sro_svcdrive(1) <= NN_2;
6778 
  n_sro_svcdrive(2) <= NN_2;
6779 
  n_sro_svcdrive(3) <= NN_2;
6780 
  n_sro_svcdrive(4) <= NN_2;
6781 
  n_sro_svcdrive(5) <= NN_2;
6782 
  n_sro_svcdrive(6) <= NN_2;
6783 
  n_sro_svcdrive(7) <= NN_2;
6784 
  n_sro_ce <= NN_2;
6785 
end beh;
6786 
 

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