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------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003, Gaisler Research
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-----------------------------------------------------------------------------
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-- Entity: cpu_disas
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-- File: cpu_disas.vhd
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-- Author: Jiri Gaisler, Gaisler Research
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-- Description: Module for disassembly
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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-- pragma translate_off
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library grlib;
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use grlib.stdlib.all;
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use grlib.sparc.all;
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use std.textio.all;
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use grlib.sparc_disas.all;
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-- pragma translate_on
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entity cpu_disas is
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port (
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clk : in std_ulogic;
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rstn : in std_ulogic;
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dummy : out std_ulogic;
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inst : in std_logic_vector(31 downto 0);
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pc : in std_logic_vector(31 downto 2);
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result: in std_logic_vector(31 downto 0);
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index : in std_logic_vector(3 downto 0);
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wreg : in std_ulogic;
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annul : in std_ulogic;
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holdn : in std_ulogic;
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pv : in std_ulogic;
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trap : in std_ulogic);
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end;
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architecture behav of cpu_disas is
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begin
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dummy <= '1';
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-- pragma translate_off
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trc : process(clk)
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variable valid : boolean;
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variable op : std_logic_vector(1 downto 0);
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variable op3 : std_logic_vector(5 downto 0);
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variable fpins, fpld : boolean;
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begin
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op := inst(31 downto 30); op3 := inst(24 downto 19);
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fpins := (op = FMT3) and ((op3 = FPOP1) or (op3 = FPOP2));
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fpld := (op = LDST) and ((op3 = LDF) or (op3 = LDDF) or (op3 = LDFSR));
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valid := (((not annul) and pv) = '1') and (not ((fpins or fpld) and (trap = '0')));
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valid := valid and (holdn = '1');
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if rising_edge(clk) and (rstn = '1') then
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print_insn (conv_integer(index), pc(31 downto 2) & "00", inst,
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result, valid, trap = '1', wreg = '1', false);
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end if;
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end process;
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-- pragma translate_on
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end;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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-- pragma translate_off
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library grlib;
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use grlib.stdlib.all;
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use grlib.sparc.all;
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use std.textio.all;
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use grlib.sparc_disas.all;
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-- pragma translate_on
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entity gaisler_cpu_disas is
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port (
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clk : in std_ulogic;
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rstn : in std_ulogic;
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dummy : out std_ulogic;
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inst : in std_logic_vector(31 downto 0);
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pc : in std_logic_vector(31 downto 2);
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result: in std_logic_vector(31 downto 0);
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index : in std_logic_vector(3 downto 0);
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wreg : in std_ulogic;
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annul : in std_ulogic;
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holdn : in std_ulogic;
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pv : in std_ulogic;
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trap : in std_ulogic);
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end;
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architecture behav of gaisler_cpu_disas is
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begin
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dummy <= '1';
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-- pragma translate_off
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trc : process(clk)
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variable valid : boolean;
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variable op : std_logic_vector(1 downto 0);
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variable op3 : std_logic_vector(5 downto 0);
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variable fpins, fpld : boolean;
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begin
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op := inst(31 downto 30); op3 := inst(24 downto 19);
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fpins := (op = FMT3) and ((op3 = FPOP1) or (op3 = FPOP2));
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fpld := (op = LDST) and ((op3 = LDF) or (op3 = LDDF) or (op3 = LDFSR));
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valid := (((not annul) and pv) = '1') and (not ((fpins or fpld) and (trap = '0')));
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valid := valid and (holdn = '1');
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if rising_edge(clk) and (rstn = '1') then
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print_insn (conv_integer(index), pc(31 downto 2) & "00", inst,
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result, valid, trap = '1', wreg = '1', false);
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end if;
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end process;
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-- pragma translate_on
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end;
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