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1 25 mikel262
-------------------------------------------------------------------------------
2
-- File Name : HostBFM.vhd
3
--
4
-- Project   : JPEG_ENC
5
--
6
-- Module    : HostBFM
7
--
8
-- Content   : Host BFM (Xilinx OPB v2.1)
9
--
10
-- Description : 
11
--
12
-- Spec.     : 
13
--
14
-- Author    : Michal Krepa
15
--
16
-------------------------------------------------------------------------------
17
-- History :
18
-- 20090301: (MK): Initial Creation.
19
-------------------------------------------------------------------------------
20
 
21
library ieee;
22
  use ieee.std_logic_1164.all;
23
  use ieee.numeric_std.all;
24
  use IEEE.STD_LOGIC_TEXTIO.ALL;
25
 
26
library STD;
27
  use STD.TEXTIO.ALL;
28
 
29
library work;
30
  use work.GPL_V2_Image_Pkg.ALL;
31
  use WORK.MDCT_PKG.all;
32
  use WORK.MDCTTB_PKG.all;
33 35 mikel262
  use work.JPEG_PKG.all;
34 25 mikel262
 
35
entity HostBFM is
36
  port
37
  (
38
        CLK                : in  std_logic;
39
        RST                : in  std_logic;
40
        -- OPB
41
        OPB_ABus           : out std_logic_vector(31 downto 0);
42
        OPB_BE             : out std_logic_vector(3 downto 0);
43
        OPB_DBus_in        : out std_logic_vector(31 downto 0);
44
        OPB_RNW            : out std_logic;
45
        OPB_select         : out std_logic;
46
        OPB_DBus_out       : in  std_logic_vector(31 downto 0);
47
        OPB_XferAck        : in  std_logic;
48
        OPB_retry          : in  std_logic;
49
        OPB_toutSup        : in  std_logic;
50
        OPB_errAck         : in  std_logic;
51
 
52
        -- HOST DATA
53
       iram_wdata          : out std_logic_vector(23 downto 0);
54
       iram_wren           : out std_logic;
55
       fifo_almost_full    : in  std_logic;
56
 
57
        sim_done           : out std_logic
58
    );
59
end entity HostBFM;
60
 
61
-------------------------------------------------------------------------------
62
-------------------------------------------------------------------------------
63
----------------------------------- ARCHITECTURE ------------------------------
64
-------------------------------------------------------------------------------
65
-------------------------------------------------------------------------------
66
architecture RTL of HostBFM is
67
 
68
  signal num_comps   : integer;
69
  signal addr_inc    : integer := 0;
70
-------------------------------------------------------------------------------
71
-- Architecture: begin
72
-------------------------------------------------------------------------------
73
begin
74
 
75
 
76
 
77
  -------------------------------------------------------------------
78
  -- code
79
  -------------------------------------------------------------------
80
  p_code : process
81
 
82
    -----------------------------------------------------------------
83
    -- HOST WRITE
84
    -----------------------------------------------------------------
85
    procedure host_write
86
      (
87
        signal clk         : in    std_logic;
88
        constant C_ADDR    : in    unsigned(31 downto 0);
89
        constant C_WDATA   : in    unsigned(31 downto 0);
90
 
91
        signal OPB_ABus    : out   std_logic_vector(31 downto 0);
92
        signal OPB_BE      : out   std_logic_vector(3 downto 0);
93
        signal OPB_DBus_in : out   std_logic_vector(31 downto 0);
94
        signal OPB_RNW     : out   std_logic;
95
        signal OPB_select  : out   std_logic;
96
        signal OPB_XferAck : in  std_logic
97
      ) is
98
    begin
99
      OPB_ABus    <= (others => '0');
100
      OPB_BE      <= (others => '0');
101
      OPB_DBus_in <= (others => '0');
102
      OPB_RNW     <= '0';
103
      OPB_select  <= '0';
104
 
105
      wait until rising_edge(clk);
106
 
107
      OPB_select  <= '1';
108
      OPB_ABus    <= std_logic_vector(C_ADDR);
109
      OPB_RNW     <= '0';
110
      OPB_BE      <= X"F";
111
      OPB_DBus_in <= std_logic_vector(C_WDATA);
112
 
113
      wait until rising_edge(clk);
114
 
115
      while OPB_XferAck /= '1' loop
116
        wait until rising_edge(clk);
117
      end loop;
118
 
119
      OPB_ABus    <= (others => '0');
120
      OPB_BE      <= (others => '0');
121
      OPB_DBus_in <= (others => '0');
122
      OPB_RNW     <= '0';
123
      OPB_select  <= '0';
124
 
125
      assert false
126
      report CR&"Host write access, address = " & HexImage(C_ADDR) & ",data written = " & HexImage(C_WDATA) &CR
127
      severity note;
128
 
129
      wait until rising_edge(clk);
130
 
131
    end procedure host_write;
132
 
133
    -----------------------------------------------------------------
134
    -- HOST READ
135
    -----------------------------------------------------------------
136
    procedure host_read
137
      (
138
        signal clk          : in    std_logic;
139
        constant C_ADDR     : in    unsigned(31 downto 0);
140
        variable RDATA      : out   unsigned(31 downto 0);
141
 
142
        signal OPB_ABus     : out   std_logic_vector(31 downto 0);
143
        signal OPB_BE       : out   std_logic_vector(3 downto 0);
144
        signal OPB_DBus_out : in    std_logic_vector(31 downto 0);
145
        signal OPB_RNW      : out   std_logic;
146
        signal OPB_select   : out   std_logic;
147
        signal OPB_XferAck  : in  std_logic
148
      )
149
    is
150
      variable data_r : std_logic_vector(31 downto 0);
151
    begin
152
      OPB_ABus    <= (others => '0');
153
      OPB_BE      <= (others => '0');
154
      OPB_DBus_in <= (others => '0');
155
      OPB_RNW     <= '0';
156
      OPB_select  <= '0';
157
 
158
      wait until rising_edge(clk);
159
 
160
      OPB_select  <= '1';
161
      OPB_ABus    <= std_logic_vector(C_ADDR);
162
      OPB_RNW     <= '1';
163
      OPB_BE      <= X"F";
164
 
165
      wait until rising_edge(clk);
166
 
167
      while OPB_XferAck /= '1' loop
168
        wait until rising_edge(clk);
169
      end loop;
170
 
171
      RDATA := unsigned(OPB_DBus_out);
172
      data_r := OPB_DBus_out;
173
 
174
      OPB_ABus    <= (others => '0');
175
      OPB_BE      <= (others => '0');
176
      OPB_DBus_in <= (others => '0');
177
      OPB_RNW     <= '0';
178
      OPB_select  <= '0';
179
 
180
      assert false
181
      report CR&"Host read access, address = " & HexImage(C_ADDR) & ",data read = " & HexImage(data_r) &CR
182
      severity note;
183
 
184
 
185
      wait until rising_edge(clk);
186
 
187
    end procedure host_read;
188
 
189
 
190
    --------------------------------------
191
    -- read text image data
192
    --------------------------------------
193
    procedure read_image is
194
      file infile          : TEXT open read_mode is "test.txt";
195
      constant N           : integer := 8;
196
      constant MAX_COMPS   : integer := 3;
197
      variable inline      : LINE;
198
      variable tmp_int     : INTEGER := 0;
199
      variable y_size      : INTEGER := 0;
200
      variable x_size      : INTEGER := 0;
201
      variable matrix      : I_MATRIX_TYPE;
202
      variable x_blk_cnt   : INTEGER := 0;
203
      variable y_blk_cnt   : INTEGER := 0;
204
      variable n_lines_arr : N_LINES_TYPE;
205
      variable line_n      : INTEGER := 0;
206
      variable pix_n       : INTEGER := 0;
207
      variable x_n         : INTEGER := 0;
208
      variable y_n         : INTEGER := 0;
209
      variable data_word   : unsigned(31 downto 0);
210
      variable image_line  : STD_LOGIC_VECTOR(0 to MAX_COMPS*MAX_IMAGE_SIZE_X*IP_W-1);
211
 
212
      constant C_IMAGE_RAM_BASE : unsigned(31 downto 0) := X"0010_0000";
213
 
214
      variable x_cnt       : integer;
215
      variable data_word2  : unsigned(31 downto 0);
216
      variable num_comps_v : integer;
217
    begin
218
      READLINE(infile,inline);
219
      READ(inline,num_comps_v);
220
      READLINE(infile,inline);
221
      READ(inline,y_size);
222
      READLINE(infile,inline);
223
      READ(inline,x_size);
224
 
225
      num_comps <= num_comps_v;
226
 
227
      if y_size rem N > 0 then
228
        assert false
229 35 mikel262
          report "ERROR: Image height dimension is not multiply of 8!"
230 25 mikel262
          severity Failure;
231
      end if;
232
      if x_size rem N > 0 then
233
        assert false
234 35 mikel262
          report "ERROR: Image width dimension is not multiply of 8!"
235 25 mikel262
          severity Failure;
236
      end if;
237
 
238 35 mikel262
      if x_size > C_MAX_LINE_WIDTH then
239
        assert false
240
          report "ERROR: Image width bigger than C_MAX_LINE_WIDTH in JPEG_PKG.VHD! " &
241
                 "Increase C_MAX_LINE_WIDTH accordingly"
242
          severity Failure;
243
      end if;
244
 
245 25 mikel262
      addr_inc <= 0;
246
 
247
      -- image size
248
      host_write(CLK, X"0000_0004", to_unsigned(x_size,16) & to_unsigned(y_size,16),
249
               OPB_ABus, OPB_BE, OPB_DBus_in, OPB_RNW, OPB_select, OPB_XferAck);
250
 
251
      iram_wren <= '0';
252
      for y_n in 0 to y_size-1 loop
253
        READLINE(infile,inline);
254
        HREAD(inline,image_line(0 to num_comps*x_size*IP_W-1));
255
        x_cnt := 0;
256
        for x_n in 0 to x_size-1 loop
257
          data_word := X"00" & UNSIGNED(image_line(x_cnt to x_cnt+num_comps*IP_W-1));
258
          data_word2(7 downto 0)   := data_word(23 downto 16);
259
          data_word2(15 downto 8)  := data_word(15 downto 8);
260
          data_word2(23 downto 16) := data_word(7 downto 0);
261
 
262
          iram_wren  <= '0';
263
          iram_wdata <= (others => 'X');
264
          while(fifo_almost_full = '1') loop
265
            wait until rising_edge(clk);
266
          end loop;
267
 
268 28 mikel262
          --for i in 0 to 10 loop
269 25 mikel262
          --  wait until rising_edge(clk);
270
          --end loop;
271
 
272
          iram_wren <= '1';
273
          iram_wdata <= std_logic_vector(data_word2(23 downto 0));
274
          wait until rising_edge(clk);
275
 
276
          x_cnt := x_cnt + num_comps*IP_W;
277
 
278
          addr_inc <= addr_inc + 1;
279
        end loop;
280
      end loop;
281
      iram_wren <= '0';
282
 
283
    end read_image;
284
 
285
    ------------------
286
    type ROMQ_TYPE is array (0 to 64-1)
287
            of unsigned(7 downto 0);
288
 
289 32 mikel262
  constant qrom_lum : ROMQ_TYPE :=
290 25 mikel262
  (
291
  -- 100%
292
  --others => X"01"
293
 
294
  -- 85%
295 41 mikel262
  --X"05", X"03", X"04", X"04", 
296
  --X"04", X"03", X"05", X"04", 
297
  --X"04", X"04", X"05", X"05", 
298
  --X"05", X"06", X"07", X"0C",
299
  --X"08", X"07", X"07", X"07", 
300
  --X"07", X"0F", X"0B", X"0B", 
301
  --X"09", X"0C", X"11", X"0F", 
302
  --X"12", X"12", X"11", X"0F",
303
  --X"11", X"11", X"13", X"16", 
304
  --X"1C", X"17", X"13", X"14", 
305
  --X"1A", X"15", X"11", X"11", 
306
  --X"18", X"21", X"18", X"1A",
307
  --X"1D", X"1D", X"1F", X"1F", 
308
  --X"1F", X"13", X"17", X"22", 
309
  --X"24", X"22", X"1E", X"24", 
310
  --X"1C", X"1E", X"1F", X"1E"
311
 -- others => X"01"
312 25 mikel262
 
313
  -- 75%
314 41 mikel262
   X"08", X"06", X"06", X"07", X"06", X"05", X"08", X"07", X"07", X"07", X"09", X"09", X"08", X"0A", X"0C", X"14",
315
   X"0D", X"0C", X"0B", X"0B", X"0C", X"19", X"12", X"13", X"0F", X"14", X"1D", X"1A", X"1F", X"1E", X"1D", X"1A",
316
   X"1C", X"1C", X"20", X"24", X"2E", X"27", X"20", X"22", X"2C", X"23", X"1C", X"1C", X"28", X"37", X"29", X"2C",
317
   X"30", X"31", X"34", X"34", X"34", X"1F", X"27", X"39", X"3D", X"38", X"32", X"3C", X"2E", X"33", X"34", X"32"
318 25 mikel262
 
319
   -- 15 %
320
   --X"35", X"25", X"28", X"2F", 
321
   --X"28", X"21", X"35", X"2F", 
322
   --X"2B", X"2F", X"3C", X"39", 
323
   --X"35", X"3F", X"50", X"85", 
324
   --X"57", X"50", X"49", X"49", 
325
   --X"50", X"A3", X"75", X"7B", 
326
   --X"61", X"85", X"C1", X"AA", 
327
   --X"CB", X"C8", X"BE", X"AA", 
328
   --X"BA", X"B7", X"D5", X"F0", 
329
   --X"FF", X"FF", X"D5", X"E2", 
330
   --X"FF", X"E6", X"B7", X"BA", 
331
   --X"FF", X"FF", X"FF", X"FF", 
332
   --X"FF", X"FF", X"FF", X"FF", 
333
   --X"FF", X"CE", X"FF", X"FF", 
334
   --X"FF", X"FF", X"FF", X"FF", 
335 32 mikel262
   --X"FF", X"FF", X"FF", X"FF"      
336 25 mikel262
 
337
   -- 50%
338 38 mikel262
   --X"10", X"0B", X"0C", X"0E", X"0C", X"0A", X"10", X"0E", 
339
   --X"0D", X"0E", X"12", X"11", X"10", X"13", X"18", X"28",
340
   --X"1A", X"18", X"16", X"16", X"18", X"31", X"23", X"25", 
341
   --X"1D", X"28", X"3A", X"33", X"3D", X"3C", X"39", X"33",
342
   --X"38", X"37", X"40", X"48", X"5C", X"4E", X"40", X"44", 
343
   --X"57", X"45", X"37", X"38", X"50", X"6D", X"51", X"57",
344
   --X"5F", X"62", X"67", X"68", X"67", X"3E", X"4D", X"71", 
345
   --X"79", X"70", X"64", X"78", X"5C", X"65", X"67", X"63"
346 32 mikel262
  );
347
 
348
  constant qrom_chr : ROMQ_TYPE :=
349
  (
350 36 mikel262
   -- 50% for chrominance
351 38 mikel262
  --X"11", X"12", X"12", X"18", X"15", X"18", X"2F", X"1A", 
352
  --X"1A", X"2F", X"63", X"42", X"38", X"42", X"63", X"63",
353
  --X"63", X"63", X"63", X"63", X"63", X"63", X"63", X"63", 
354
  --X"63", X"63", X"63", X"63", X"63", X"63", X"63", X"63",
355
  --X"63", X"63", X"63", X"63", X"63", X"63", X"63", X"63", 
356
  --X"63", X"63", X"63", X"63", X"63", X"63", X"63", X"63",
357
  --X"63", X"63", X"63", X"63", X"63", X"63", X"63", X"63", 
358
  --X"63", X"63", X"63", X"63", X"63", X"63", X"63", X"63"
359
 
360 41 mikel262
  -- 75% chrominance
361
  X"09", X"09", X"09", X"0C", X"0B", X"0C", X"18", X"0D",
362
  X"0D", X"18", X"32", X"21", X"1C", X"21", X"32", X"32",
363
  X"32", X"32", X"32", X"32", X"32", X"32", X"32", X"32",
364
  X"32", X"32", X"32", X"32", X"32", X"32", X"32", X"32",
365
  X"32", X"32", X"32", X"32", X"32", X"32", X"32", X"32",
366
  X"32", X"32", X"32", X"32", X"32", X"32", X"32", X"32",
367
  X"32", X"32", X"32", X"32", X"32", X"32", X"32", X"32",
368
  X"32", X"32", X"32", X"32", X"32", X"32", X"32", X"32"
369
 
370
  --X"08", X"06", X"06", X"07", X"06", X"05", X"08", X"07", X"07", X"07", X"09", X"09", X"08", X"0A", X"0C", X"14",
371
  --X"0D", X"0C", X"0B", X"0B", X"0C", X"19", X"12", X"13", X"0F", X"14", X"1D", X"1A", X"1F", X"1E", X"1D", X"1A",
372
  --X"1C", X"1C", X"20", X"24", X"2E", X"27", X"20", X"22", X"2C", X"23", X"1C", X"1C", X"28", X"37", X"29", X"2C",
373
  --X"30", X"31", X"34", X"34", X"34", X"1F", X"27", X"39", X"3D", X"38", X"32", X"3C", X"2E", X"33", X"34", X"32"
374
  -- others => X"01"
375 25 mikel262
  );
376
 
377
    variable data_read  : unsigned(31 downto 0);
378
    variable data_write : unsigned(31 downto 0);
379
    variable addr       : unsigned(31 downto 0);
380
 
381
 
382
  ------------------------------------------------------------------------------
383
  -- BEGIN
384
  ------------------------------------------------------------------------------
385
  begin
386
    sim_done <= '0';
387
    iram_wren <= '0';
388
 
389
    while RST /= '0' loop
390
      wait until rising_edge(clk);
391
    end loop;
392
 
393
    for i in 0 to 100 loop
394
      wait until rising_edge(clk);
395
    end loop;
396
 
397
 
398
 
399
    host_read(CLK, X"0000_0000", data_read,
400
               OPB_ABus, OPB_BE, OPB_DBus_out, OPB_RNW, OPB_select, OPB_XferAck);
401
 
402
 
403
    host_read(CLK, X"0000_0004", data_read,
404
               OPB_ABus, OPB_BE, OPB_DBus_out, OPB_RNW, OPB_select, OPB_XferAck);
405
 
406 32 mikel262
    -- write luminance quantization table 
407 25 mikel262
    for i in 0 to 64-1 loop
408 32 mikel262
      data_write := X"0000_00" & qrom_lum(i);
409 25 mikel262
      addr := X"0000_0100" + to_unsigned(4*i,32);
410
      host_write(CLK, addr, data_write,
411
               OPB_ABus, OPB_BE, OPB_DBus_in, OPB_RNW, OPB_select, OPB_XferAck);
412
 
413
    end loop;
414
 
415 32 mikel262
    -- write chrominance quantization table 
416
    for i in 0 to 64-1 loop
417
      data_write := X"0000_00" & qrom_chr(i);
418
      addr := X"0000_0200" + to_unsigned(4*i,32);
419
      host_write(CLK, addr, data_write,
420
               OPB_ABus, OPB_BE, OPB_DBus_in, OPB_RNW, OPB_select, OPB_XferAck);
421
 
422
    end loop;
423
 
424
 
425 25 mikel262
 
426
    data_write := to_unsigned(1,32) + shift_left(to_unsigned(3,32),1);
427
 
428
    -- SOF & num_comps
429
    host_write(CLK, X"0000_0000", data_write,
430
               OPB_ABus, OPB_BE, OPB_DBus_in, OPB_RNW, OPB_select, OPB_XferAck);
431
 
432
    -- write BUF_FIFO with bitmap
433
    read_image;
434
 
435
    -- wait until JPEG encoding is done
436
    host_read(CLK, X"0000_000C", data_read,
437
               OPB_ABus, OPB_BE, OPB_DBus_out, OPB_RNW, OPB_select, OPB_XferAck);
438
    while data_read /= 2 loop
439
     host_read(CLK, X"0000_000C", data_read,
440
               OPB_ABus, OPB_BE, OPB_DBus_out, OPB_RNW, OPB_select, OPB_XferAck);
441
    end loop;
442
 
443
    sim_done <= '1';
444
 
445
    wait;
446
 
447
  end process;
448
 
449
 
450
end architecture RTL;
451
-------------------------------------------------------------------------------
452
-- Architecture: end
453
-------------------------------------------------------------------------------

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