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[/] [mkjpeg/] [trunk/] [tb/] [vhdl/] [JPEG_TB.VHD] - Blame information for rev 42

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1 25 mikel262
--------------------------------------------------------------------------------
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--                                                                            --
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--                          V H D L    F I L E                                --
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--                          COPYRIGHT (C) 2006                                --
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--                                                                            --
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--------------------------------------------------------------------------------
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--
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-- Title       : JPEG_TB
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-- Design      : JPEG_ENC
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-- Author      : Michal Krepa
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--
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--------------------------------------------------------------------------------
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--
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-- File        : JPEG_TB.VHD
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-- Created     : Sun Mar 1 2009
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--
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--------------------------------------------------------------------------------
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--
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--  Description : Testbench top-level
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--
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--------------------------------------------------------------------------------
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library IEEE;
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  use IEEE.STD_LOGIC_1164.all;
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  use ieee.numeric_std.all;
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  use IEEE.STD_LOGIC_TEXTIO.ALL;
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library STD;
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  use STD.TEXTIO.ALL;
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library work;
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  use work.GPL_V2_Image_Pkg.ALL;
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  use WORK.MDCT_PKG.all;
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  use WORK.MDCTTB_PKG.all;
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entity JPEG_TB is
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end JPEG_TB;
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--**************************************************************************--
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architecture TB of JPEG_TB is
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  type char_file is file of character;
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  file f_capture           : text;
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  file f_capture_bin       : char_file;
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  constant CAPTURE_ORAM    : string := "OUT_RAM.txt";
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  constant CAPTURE_BIN     : string := "test_out.jpg";
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  signal CLK               : STD_LOGIC;
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  signal RST               : STD_LOGIC;
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  signal ram_rdaddr        : std_logic_vector(23 downto 0);
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  signal ram_q             : std_logic_vector(7 downto 0);
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  signal ram_byte          : std_logic_vector(7 downto 0);
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  signal ram_wren          : std_logic;
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  signal ram_wraddr        : std_logic_vector(23 downto 0);
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  signal OPB_ABus          : std_logic_vector(31 downto 0);
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  signal OPB_BE            : std_logic_vector(3 downto 0);
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  signal OPB_DBus_in       : std_logic_vector(31 downto 0);
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  signal OPB_RNW           : std_logic;
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  signal OPB_select        : std_logic;
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  signal OPB_DBus_out      : std_logic_vector(31 downto 0);
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  signal OPB_XferAck       : std_logic;
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  signal OPB_retry         : std_logic;
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  signal OPB_toutSup       : std_logic;
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  signal OPB_errAck        : std_logic;
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  signal iram_waddr        : std_logic_vector(19 downto 0);
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  signal iram_raddr        : std_logic_vector(19 downto 0);
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  signal iram_wdata        : std_logic_vector(23 downto 0);
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  signal iram_rdata        : std_logic_vector(23 downto 0);
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  signal iram_wren         : std_logic;
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  signal iram_rden         : std_logic;
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  signal sim_done          : std_logic;
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  signal iram_fifo_afull   : std_logic;
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  signal outif_almost_full : std_logic;
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  signal count1            : unsigned(15 downto 0);
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------------------------------
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-- architecture begin
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------------------------------
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begin
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  ------------------------------
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  -- CLKGEN map
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  ------------------------------
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  U_ClkGen : entity work.ClkGen
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        port map
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  (
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     CLK            => CLK,
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     RST            => RST
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        );
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  ------------------------------
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  -- HOST Bus Functional Model
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  ------------------------------
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  U_HostBFM : entity work.HostBFM
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  port map
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  (
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        CLK            => CLK,
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        RST            => RST,
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        -- OPB
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        OPB_ABus       => OPB_ABus,
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        OPB_BE         => OPB_BE,
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        OPB_DBus_in    => OPB_DBus_in,
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        OPB_RNW        => OPB_RNW,
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        OPB_select     => OPB_select,
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        OPB_DBus_out   => OPB_DBus_out,
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        OPB_XferAck    => OPB_XferAck,
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        OPB_retry      => OPB_retry,
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        OPB_toutSup    => OPB_toutSup,
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        OPB_errAck     => OPB_errAck,
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        -- IRAM
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        iram_wdata     => iram_wdata,
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        iram_wren      => iram_wren,
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        fifo_almost_full => iram_fifo_afull,
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        sim_done       => sim_done
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    );
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  ------------------------------
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  -- JPEG ENCODER
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  ------------------------------
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  U_JpegEnc : entity work.JpegEnc
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  port map
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  (
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        CLK                => CLK,
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        RST                => RST,
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        -- OPB
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        OPB_ABus           => OPB_ABus,
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        OPB_BE             => OPB_BE,
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        OPB_DBus_in        => OPB_DBus_in,
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        OPB_RNW            => OPB_RNW,
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        OPB_select         => OPB_select,
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        OPB_DBus_out       => OPB_DBus_out,
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        OPB_XferAck        => OPB_XferAck,
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        OPB_retry          => OPB_retry,
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        OPB_toutSup        => OPB_toutSup,
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        OPB_errAck         => OPB_errAck,
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        -- IMAGE RAM
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        iram_wdata         => iram_wdata,
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        iram_wren          => iram_wren,
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        iram_fifo_afull    => iram_fifo_afull,
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        -- OUT RAM
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        ram_byte           => ram_byte,
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        ram_wren           => ram_wren,
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        ram_wraddr         => ram_wraddr,
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        outif_almost_full  => outif_almost_full
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    );
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  -------------------------------------------------------------------
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  -- OUT RAM
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  -------------------------------------------------------------------
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  U_OUT_RAM : entity work.RAMSIM
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  generic map
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  (
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      RAMADDR_W     => 18,
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      RAMDATA_W     => 8
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  )
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  port map
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  (
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        d           => ram_byte,
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        waddr       => ram_wraddr(17 downto 0),
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        raddr       => ram_rdaddr(17 downto 0),
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        we          => ram_wren,
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        clk         => CLK,
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        q           => ram_q
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  );
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  p_capture : process
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    variable fLine           : line;
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    variable fLine_bin       : line;
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  begin
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    file_open(f_capture, CAPTURE_ORAM, write_mode);
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    file_open(f_capture_bin, CAPTURE_BIN, write_mode);
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    while sim_done /= '1' loop
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      wait until rising_edge(CLK);
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      if ram_wren = '1' then
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        hwrite(fLine, ram_byte);
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        write(fLine, string'(" "));
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        write(f_capture_bin, CHARACTER'VAL(to_integer(unsigned(ram_byte))));
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      end if;
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    end loop;
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    writeline(f_capture, fLine);
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    --writeline(f_capture_bin, fLine_bin);
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    file_close(f_capture);
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    file_close(f_capture_bin);
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    wait;
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  end process;
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  backpressure : process(CLK, RST)
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  begin
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    if RST = '1' then
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      outif_almost_full <= '0';
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      count1 <= (others => '0');
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    elsif CLK'event and CLK = '1' then
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      if count1 = 10000 then
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        count1 <= (others => '0');
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        outif_almost_full <= not outif_almost_full;
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      else
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        count1 <= count1 + 1;
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      end if;
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    end if;
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  end process;
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end TB;
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-----------------------------------
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--**************************************************************************--

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