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[/] [mod_mult_exp/] [trunk/] [bench/] [vhdl/] [mod_mult/] [ModularMultiplierIterative32bitTB.vhd] - Blame information for rev 4

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1 3 gajos
-----------------------------------------------------------------------
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----                                                               ----
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---- Montgomery modular multiplier and exponentiator               ----
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----                                                               ----
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---- This file is part of the Montgomery modular multiplier        ----
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---- and exponentiator project                                     ----
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---- http://opencores.org/project,mod_mult_exp                     ----
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----                                                               ----
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---- Description:                                                  ----
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----   This is TestBench for the Montgomery modular multiplier     ----
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----   with the 32 bit width.                                      ----
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----   it takes two nubers and modulus as the input and results    ----
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----   the Montgomery product A*B*(R^{-1}) mod M                   ----
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----   where R^{-1} is the modular multiplicative inverse.         ----
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----   R*R^{-1} == 1 mod M                                         ----
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----   R = 2^word_length mod M                                     ----
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----               and word_length is the binary width of the      ----
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----               operated word (in this case 32 bit)             ----
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---- To Do:                                                        ----
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----                                                               ----
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---- Author(s):                                                    ----
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---- - Krzysztof Gajewski, gajos@opencores.org                     ----
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----                       k.gajewski@gmail.com                    ----
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----                                                               ----
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-----------------------------------------------------------------------
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----                                                               ----
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---- Copyright (C) 2014 Authors and OPENCORES.ORG                  ----
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----                                                               ----
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---- This source file may be used and distributed without          ----
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---- restriction provided that this copyright statement is not     ----
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---- removed from the file and that any derivative work contains   ----
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---- the original copyright notice and the associated disclaimer.  ----
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----                                                               ----
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---- This source file is free software; you can redistribute it    ----
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---- and-or modify it under the terms of the GNU Lesser General    ----
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---- Public License as published by the Free Software Foundation;  ----
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---- either version 2.1 of the License, or (at your option) any    ----
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---- later version.                                                ----
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----                                                               ----
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---- This source is distributed in the hope that it will be        ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied    ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR       ----
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---- PURPOSE. See the GNU Lesser General Public License for more   ----
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---- details.                                                      ----
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----                                                               ----
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---- You should have received a copy of the GNU Lesser General     ----
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---- Public License along with this source; if not, download it    ----
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---- from http://www.opencores.org/lgpl.shtml                      ----
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----                                                               ----
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-----------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--USE ieee.numeric_std.ALL;
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ENTITY ModularMultiplierIterative32bitTB IS
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END ModularMultiplierIterative32bitTB;
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ARCHITECTURE behavior OF ModularMultiplierIterative32bitTB IS
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    -- Component Declaration for the Unit Under Test (UUT)
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    COMPONENT ModularMultiplierIterative
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    PORT(
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         A       : IN  STD_LOGIC_VECTOR(31 downto 0);
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         B       : IN  STD_LOGIC_VECTOR(31 downto 0);
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         M       : IN  STD_LOGIC_VECTOR(31 downto 0);
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         start   : IN  STD_LOGIC;
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         product : OUT STD_LOGIC_VECTOR(31 downto 0);
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         ready   : OUT STD_LOGIC;
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         clk     : IN  STD_LOGIC
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        );
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    END COMPONENT;
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   --Inputs
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   signal A     : STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
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   signal B     : STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
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   signal M     : STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
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   signal start : STD_LOGIC := '0';
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   signal clk   : STD_LOGIC := '0';
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        --Outputs
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   signal product : std_logic_vector(31 downto 0);
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   signal ready   : STD_LOGIC;
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   -- Clock period definitions
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   constant clk_period : time := 10 ns;
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BEGIN
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        -- Instantiate the Unit Under Test (UUT)
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   uut: ModularMultiplierIterative PORT MAP (
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          A => A,
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          B => B,
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          M => M,
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          start => start,
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          product => product,
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          ready => ready,
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          clk => clk
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        );
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   -- Clock process definitions
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   clk_process :process
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   begin
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                clk <= '0';
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                wait for clk_period/2;
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                clk <= '1';
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                wait for clk_period/2;
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   end process;
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   -- Stimulus process
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   stim_proc: process
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   begin
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      -- hold reset state for 100 ns.
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                start <= '0';
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      wait for 100 ns;
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---- Preparation for test case 1 -----------------
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--    A = 1073741827 in decimal
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--    B = 1876543287 in decimal
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--    M = 2147483659 in decimal
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--    expected_result = 1075674849379283795 in decimal,  in hex 66e4624e
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--    mod(1073741827*1876543287*1659419191, 2147483659) = 1726243406
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--    where 2703402148733296366 is the inverse modulus
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--------------------------------------------------
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                start <= '1';
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      -- A = 1073741827 in decimal
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      A <=  "01000000000000000000000000000011";
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      -- B = 1876543210987 in decimal
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           B <=  "01101111110110011100011100110111";
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           -- M = 2147483659 in decimal
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      M <=  "10000000000000000000000000001011";
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          --wait for 80*clk_period;
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          wait until ready = '1' and clk = '0';
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          if product /= x"66e4624e" then
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                report "RESULT MISMATCH! Test case 1 failed" severity ERROR;
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                assert false severity failure;
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          else
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                report "Test case 1 successful" severity note;
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          end if;
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     start <= '0';
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---- Preparation for test case 2 -----------------
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--    A = 1073741826 in decimal
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--    B = 1876543286 in decimal
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--    M = 2147483659 in decimal
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--    expected_result = 1075674849379283795 in decimal,  in hex 66e4624e
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--    mod(1073741826*1876543286*1659419191, 2147483659) = 1567508594
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--    where 1659419191 is the inverse modulus
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--------------------------------------------------
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      -- A = 1073741826 in decimal
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      A <=  "01000000000000000000000000000010";
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      -- B = 1876543210986 in decimal
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           B <=  "01101111110110011100011100110110";
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           -- M = 2147483659 in decimal
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      M <=  "10000000000000000000000000001011";
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                wait for clk_period;
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      start <= '1';
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          --wait for 80*clk_period;
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          wait until ready = '1' and clk = '0';
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          if product /= x"5d6e4872" then
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                report "RESULT MISMATCH! Test case 2 failed" severity ERROR;
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                assert false severity failure;
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          else
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                report "Test case 2 successful" severity note;
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          end if;
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                assert false severity failure;
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   end process;
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END;

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