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gajos |
-----------------------------------------------------------------------
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---- ----
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---- Montgomery modular multiplier and exponentiator ----
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---- ----
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---- This file is part of the Montgomery modular multiplier ----
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---- and exponentiator project ----
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---- http://opencores.org/project,mod_mult_exp ----
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---- ----
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---- Description: ----
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---- This module is state machine for the example implementation ----
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---- of the Montgomery modular exponentiatorcombined with the ----
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---- RS-232 communication with PC. ----
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---- ----
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---- To Do: ----
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---- ----
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---- Author(s): ----
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---- - Krzysztof Gajewski, gajos@opencores.org ----
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---- k.gajewski@gmail.com ----
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---- ----
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-----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2019 Authors and OPENCORES.ORG ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and-or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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-----------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use work.properties.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity ModExpDataCtrlSM is
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port(
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clk : in STD_LOGIC;
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reset : in STD_LOGIC;
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RDAsig : in STD_LOGIC;
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TBEsig : in STD_LOGIC;
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RDsig : out STD_LOGIC;
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WRsig : out STD_LOGIC;
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data_in_ready : out STD_LOGIC;
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readySig : in STD_LOGIC;
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modExpCtrlRegEn : out STD_LOGIC;
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dataToModExpEn : out STD_LOGIC;
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dataToModExpShift : out STD_LOGIC;
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dataFromModExpEn : out STD_LOGIC;
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dataFromModExpShift : out STD_LOGIC;
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muxCtrl : out STD_LOGIC;
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opcodes : in STD_LOGIC_VECTOR(2 downto 0);
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controlStateOut : out STD_LOGIC_VECTOR(2 downto 0)
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);
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end ModExpDataCtrlSM;
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architecture Behavioral of ModExpDataCtrlSM is
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-- Counters are used for both bit counting in byte
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-- and composing full length word in exponentiator
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component counter is
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generic(
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size : integer := 4
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);
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port (
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count : in STD_LOGIC;
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zero : in STD_LOGIC;
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output : out STD_LOGIC_VECTOR (size - 1 downto 0);
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clk : in STD_LOGIC;
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reset : in STD_LOGIC
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);
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end component counter;
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-- some constants for temp_state signal which is used in TEMPORARY_STATE.
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-- This state is used as something like "wait" command due to data
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-- propagation in the core
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constant rd_data : STD_LOGIC_VECTOR(2 downto 0) := "000";
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constant mk_fin : STD_LOGIC_VECTOR(2 downto 0) := "001";
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constant dat_out_prop : STD_LOGIC_VECTOR(2 downto 0) := "010";
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constant info_st : STD_LOGIC_VECTOR(2 downto 0) := "011";
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constant mv_dat : STD_LOGIC_VECTOR(2 downto 0) := "100";
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constant nothing : STD_LOGIC_VECTOR(2 downto 0) := "101";
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signal state : comm_ctrl_states := NOP;
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signal next_state : comm_ctrl_states := NOP;
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signal temp_state : STD_LOGIC_VECTOR (2 downto 0) := nothing;
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-- This signals are used for control the counters for data shifting
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-- in shift registers (by bytes). This length have to be modified
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-- with changing the used word size.
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-- Modify for variable key size
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-- In fact it is modified from the properties file
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signal serialDataCtrCt : STD_LOGIC;
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signal serialDataCtrZero : STD_LOGIC;
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signal serialDataCtrOut : STD_LOGIC_VECTOR(WORD_INT_LOG downto 0);
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-- This signals are used for control the counters for data shifting - bits in
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-- bytes.
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-- DO NOT MODIFY!!!
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signal shiftDataCtrCt : STD_LOGIC;
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signal shiftDataCtrZero : STD_LOGIC;
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signal shiftDataCtrOut : STD_LOGIC_VECTOR(3 downto 0);
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begin
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-- State machine process
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SM : process(state, RDAsig, TBEsig, shiftDataCtrOut,
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serialDataCtrOut, opcodes, readySig)
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begin
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case state is
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-- This state prepares whoole core before calculations
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-- 'No operation' state
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when NOP =>
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WRsig <= '0';
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modExpCtrlRegEn <= '0';
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dataToModExpEn <= '0';
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dataToModExpShift <= '0';
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dataFromModExpEn <= '0';
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dataFromModExpShift <= '0';
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serialDataCtrZero <= '1';
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serialDataCtrCt <= '0';
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shiftDataCtrZero <= '1';
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shiftDataCtrCt <= '0';
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RDsig <= '0';
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-- This is something like 'info' word
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if (readySig = '1') then
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controlStateOut <= "100";
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else
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controlStateOut <= "000";
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end if;
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muxCtrl <= '1';
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data_in_ready <= '0';
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temp_state <= nothing; -- not important
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-- RDAsig = '1' means that some data
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-- appeard in the RS-232 input
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if (RDAsig = '1') then
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next_state <= DECODE_IN;
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else
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next_state <= NOP;
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end if;
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when DECODE_IN =>
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WRsig <= '0';
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dataToModExpEn <= '0';
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dataToModExpShift <= '0';
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dataFromModExpEn <= '0';
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dataFromModExpShift <= '0';
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serialDataCtrZero <= '1';
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serialDataCtrCt <= '0';
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shiftDataCtrZero <= '1';
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shiftDataCtrCt <= '0';
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RDsig <= '1';
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controlStateOut <= "000";
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muxCtrl <= '1';
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data_in_ready <= '0';
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modExpCtrlRegEn <= '1';
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-- firstly from the RS-232 input comes OPCODE informing the core
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-- what to do. Data can appeard in any order. This opcode are saved
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-- in the suitable register at the input of the modular exponentiator
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if (opcodes = mn_read_base) or (opcodes = mn_read_modulus) or
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(opcodes = mn_read_exponent) or (opcodes = mn_read_residuum) then
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next_state <= TEMPORARY_STATE;
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temp_state <= rd_data;
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elsif (opcodes = mn_count_power) then
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next_state <= TEMPORARY_STATE;
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temp_state <= mk_fin;
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elsif (opcodes = mn_show_result) then
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if (readySig = '1') then
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next_state <= TEMPORARY_STATE;
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temp_state <= dat_out_prop;
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else
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next_state <= TEMPORARY_STATE;
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temp_state <= info_st;
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end if;
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elsif (opcodes = mn_prepare_for_data) then
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next_state <= TEMPORARY_STATE;
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temp_state <= nothing;
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else
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next_state <= NOP;
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temp_state <= nothing; -- not important
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end if;
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when READ_DATA =>
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-- For now need to 'restart' all the flow of reading data
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modExpCtrlRegEn <= '0';
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RDsig <= '0';
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WRsig <= '0';
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serialDataCtrCt <= '0';
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serialDataCtrZero <= '0';
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shiftDataCtrCt <= '0';
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shiftDataCtrZero <= '0';
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dataToModExpEn <= '1';
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dataToModExpShift <= '0';
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dataFromModExpEn <= '0';
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dataFromModExpShift <= '0';
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controlStateOut <= "000";
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muxCtrl <= '1';
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data_in_ready <= '0';
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temp_state <= nothing; -- not important
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if (RDAsig = '0') then
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next_state <= READ_DATA;
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else
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next_state <= DECODE_READ;
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end if;
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-- This state is for the control of number of the 8-bit 'packets'
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-- of the input data for the modular exponentiator
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when DECODE_READ =>
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modExpCtrlRegEn <= '0';
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WRsig <= '0';
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serialDataCtrCt <= '1';
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serialDataCtrZero <= '0';
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shiftDataCtrCt <= '0';
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shiftDataCtrZero <= '0';
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dataToModExpShift <= '0';
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dataFromModExpEn <= '0';
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dataFromModExpShift <= '0';
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RDsig <= '1';
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dataToModExpEn <= '1';
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controlStateOut <= "000";
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muxCtrl <= '1';
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data_in_ready <= '0';
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-- Data reading X times 8 bit -> modify for variable key length
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-- In fact it is modified from the properties file
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if (serialDataCtrOut(WORD_INT_LOG - 1 downto 0) = WORD_INT_LOG_STR) then
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next_state <= DECODE_READ_PROP;
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temp_state <= nothing; -- not important
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else
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next_state <= TEMPORARY_STATE;
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temp_state <= mv_dat;
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end if;
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-- Some info state for the modular exponentiator core,
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-- that some data are at the input - after the end of the
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-- reading data
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when DECODE_READ_PROP =>
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modExpCtrlRegEn <= '0';
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WRsig <= '0';
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serialDataCtrCt <= '0';
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serialDataCtrZero <= '0';
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shiftDataCtrCt <= '0';
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shiftDataCtrZero <= '0';
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dataToModExpShift <= '0';
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dataFromModExpEn <= '0';
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dataFromModExpShift <= '0';
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RDsig <= '0';
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dataToModExpEn <= '0';
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serialDataCtrCt <= '0';
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muxCtrl <= '1';
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data_in_ready <= '1';
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temp_state <= nothing; -- not important
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controlStateOut <= "000";
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next_state <= INFO_STATE;
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-- This state is for moving bits in data word for the
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-- modular exponentiator counter counts to 8 while data
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-- are shifted
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when MOVE_DATA =>
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modExpCtrlRegEn <= '0';
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RDsig <= '0';
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WRsig <= '0';
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serialDataCtrCt <= '0';
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dataToModExpEn <= '0';
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dataToModExpShift <= '1';
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dataFromModExpEn <= '0';
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dataFromModExpShift <= '0';
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serialDataCtrZero <= '0';
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temp_state <= nothing;
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controlStateOut <= "000";
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muxCtrl <= '1';
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data_in_ready <= '0';
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--- shifting data in register -> DO NOT MODIFY!!!
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293 |
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if (shiftDataCtrOut(2 downto 0) = "111") then
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shiftDataCtrZero <= '1';
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shiftDataCtrCt <= '0';
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next_state <= READ_DATA;
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else
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shiftDataCtrZero <= '0';
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shiftDataCtrCt <= '1';
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next_state <= MOVE_DATA;
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end if;
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302 |
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-- If all the needed data appeared at the input
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303 |
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-- and 'mn_count_power' command appeared modular exponentiation
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304 |
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-- is performed. This state is present until modular exponentiation
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305 |
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-- is calculated
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306 |
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when MAKE_MOD_EXP =>
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307 |
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modExpCtrlRegEn <= '0';
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308 |
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RDsig <= '0';
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309 |
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WRsig <= '0';
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310 |
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dataToModExpEn <= '0';
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311 |
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dataToModExpShift <= '0';
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312 |
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dataFromModExpEn <= '0';
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313 |
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dataFromModExpShift <= '0';
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314 |
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serialDataCtrCt <= '0';
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315 |
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serialDataCtrZero <= '0';
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316 |
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shiftDataCtrCt <= '0';
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shiftDataCtrZero <= '0';
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318 |
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muxCtrl <= '1';
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data_in_ready <= '1';
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320 |
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-- Here
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322 |
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if (readySig = '1') then
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controlStateOut <= "100";
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324 |
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next_state <= TEMPORARY_STATE;
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325 |
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temp_state <= info_st;
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326 |
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else
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controlStateOut <= "001";
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328 |
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next_state <= MAKE_MOD_EXP;
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329 |
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temp_state <= nothing;
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330 |
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end if;
|
331 |
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-- When 'mn_show_result' command appears in the core input,
|
332 |
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-- the result from the modular exponentiation feeds the output
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333 |
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-- Here and below state are also for 'data propagation'
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334 |
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when DATA_TO_OUT_PROPAGATE =>
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335 |
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modExpCtrlRegEn <= '0';
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336 |
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RDsig <= '0';
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337 |
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WRsig <= '0';
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338 |
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dataToModExpEn <= '0';
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339 |
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dataToModExpShift <= '0';
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340 |
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shiftDataCtrCt <= '0';
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341 |
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shiftDataCtrZero <= '0';
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342 |
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serialDataCtrCt <= '0';
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343 |
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serialDataCtrZero <= '0';
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344 |
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dataFromModExpEn <= '1';
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345 |
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dataFromModExpShift <= '0';
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346 |
|
|
next_state <= DATA_TO_OUT_PROPAGATE2;
|
347 |
|
|
temp_state <= nothing;
|
348 |
|
|
controlStateOut <= "000";
|
349 |
|
|
muxCtrl <= '0';
|
350 |
|
|
data_in_ready <= '0';
|
351 |
|
|
temp_state <= nothing; -- not important
|
352 |
|
|
when DATA_TO_OUT_PROPAGATE2 =>
|
353 |
|
|
modExpCtrlRegEn <= '0';
|
354 |
|
|
RDsig <= '0';
|
355 |
|
|
WRsig <= '1';
|
356 |
|
|
dataToModExpEn <= '0';
|
357 |
|
|
dataToModExpShift <= '0';
|
358 |
|
|
dataFromModExpEn <= '0';
|
359 |
|
|
dataFromModExpShift <= '0';
|
360 |
|
|
serialDataCtrCt <= '0';
|
361 |
|
|
serialDataCtrZero <= '0';
|
362 |
|
|
shiftDataCtrCt <= '0';
|
363 |
|
|
shiftDataCtrZero <= '0';
|
364 |
|
|
next_state <= OUTPUT_DATA;
|
365 |
|
|
temp_state <= nothing;
|
366 |
|
|
controlStateOut <= "000";
|
367 |
|
|
muxCtrl <= '0';
|
368 |
|
|
data_in_ready <= '0';
|
369 |
|
|
temp_state <= nothing; -- not important
|
370 |
|
|
-- Here data from parallel form are transformed to serial form.
|
371 |
|
|
-- This state is for the control of number of the 8-bit 'packets'
|
372 |
|
|
-- of the input data for the modular exponentiator
|
373 |
|
|
when OUTPUT_DATA =>
|
374 |
|
|
modExpCtrlRegEn <= '0';
|
375 |
|
|
dataToModExpEn <= '0';
|
376 |
|
|
dataToModExpShift <= '0';
|
377 |
|
|
dataFromModExpEn <= '0';
|
378 |
|
|
dataFromModExpShift <= '0';
|
379 |
|
|
shiftDataCtrCt <= '0';
|
380 |
|
|
shiftDataCtrZero <= '0';
|
381 |
|
|
serialDataCtrZero <= '0';
|
382 |
|
|
RDsig <= '0';
|
383 |
|
|
WRsig <= '1';
|
384 |
|
|
serialDataCtrCt <= '1';
|
385 |
|
|
temp_state <= nothing;
|
386 |
|
|
controlStateOut <= "000";
|
387 |
|
|
muxCtrl <= '0';
|
388 |
|
|
data_in_ready <= '0';
|
389 |
|
|
if (serialDataCtrOut(WORD_INT_LOG) = '1') then
|
390 |
|
|
next_state <= NOP;
|
391 |
|
|
else
|
392 |
|
|
next_state <= MOVE_OUTPUT_DATA;
|
393 |
|
|
end if;
|
394 |
|
|
-- This state is for moving bits in data word for the
|
395 |
|
|
-- modular exponentiator counter counts to 8 while data
|
396 |
|
|
-- are shifted
|
397 |
|
|
when MOVE_OUTPUT_DATA =>
|
398 |
|
|
if (TBEsig = '0') then
|
399 |
|
|
-- Here we have to wait for the sending the previous serial data
|
400 |
|
|
modExpCtrlRegEn <= '0';
|
401 |
|
|
RDsig <= '0';
|
402 |
|
|
WRsig <= '0';
|
403 |
|
|
serialDataCtrCt <= '0';
|
404 |
|
|
dataToModExpEn <= '0';
|
405 |
|
|
dataToModExpShift <= '0';
|
406 |
|
|
dataFromModExpEn <= '0';
|
407 |
|
|
dataFromModExpShift <= '0';
|
408 |
|
|
serialDataCtrZero <= '0';
|
409 |
|
|
shiftDataCtrCt <= '0';
|
410 |
|
|
shiftDataCtrZero <= '0';
|
411 |
|
|
next_state <= MOVE_OUTPUT_DATA;
|
412 |
|
|
controlStateOut <= "000";
|
413 |
|
|
muxCtrl <= '0';
|
414 |
|
|
data_in_ready <= '0';
|
415 |
|
|
temp_state <= nothing; -- not important
|
416 |
|
|
else
|
417 |
|
|
-- Here data are shifted in the output data word
|
418 |
|
|
modExpCtrlRegEn <= '0';
|
419 |
|
|
RDsig <= '0';
|
420 |
|
|
WRsig <= '0';
|
421 |
|
|
serialDataCtrCt <= '0';
|
422 |
|
|
dataToModExpEn <= '0';
|
423 |
|
|
dataToModExpShift <= '0';
|
424 |
|
|
dataFromModExpEn <= '0';
|
425 |
|
|
dataFromModExpShift <= '1';
|
426 |
|
|
shiftDataCtrCt <= '1';
|
427 |
|
|
serialDataCtrZero <= '0';
|
428 |
|
|
controlStateOut <= "000";
|
429 |
|
|
muxCtrl <= '0';
|
430 |
|
|
data_in_ready <= '0';
|
431 |
|
|
temp_state <= nothing; -- not important
|
432 |
|
|
-- Output register shifting DO NOT MODIFY!!!
|
433 |
|
|
if (shiftDataCtrOut(3) = '1') then
|
434 |
|
|
shiftDataCtrCt <= '0';
|
435 |
|
|
shiftDataCtrZero <= '1';
|
436 |
|
|
dataFromModExpShift <= '0';
|
437 |
|
|
next_state <= DATA_TO_OUT_PROPAGATE2;
|
438 |
|
|
else
|
439 |
|
|
shiftDataCtrZero <= '0';
|
440 |
|
|
next_state <= MOVE_OUTPUT_DATA;
|
441 |
|
|
end if;
|
442 |
|
|
end if;
|
443 |
|
|
-- State for informing 'the world' about the end of
|
444 |
|
|
-- the modular exponentiation
|
445 |
|
|
when INFO_STATE =>
|
446 |
|
|
modExpCtrlRegEn <= '0';
|
447 |
|
|
dataToModExpEn <= '0';
|
448 |
|
|
dataToModExpShift <= '0';
|
449 |
|
|
dataFromModExpEn <= '0';
|
450 |
|
|
dataFromModExpShift <= '0';
|
451 |
|
|
serialDataCtrCt <= '0';
|
452 |
|
|
serialDataCtrZero <= '0';
|
453 |
|
|
shiftDataCtrCt <= '0';
|
454 |
|
|
shiftDataCtrZero <= '0';
|
455 |
|
|
if (readySig = '1') then
|
456 |
|
|
controlStateOut <= "100";
|
457 |
|
|
else
|
458 |
|
|
controlStateOut <= "000";
|
459 |
|
|
end if;
|
460 |
|
|
muxCtrl <= '1';
|
461 |
|
|
data_in_ready <= '0';
|
462 |
|
|
temp_state <= nothing; -- not important
|
463 |
|
|
RDsig <= '0';
|
464 |
|
|
WRsig <= '1';
|
465 |
|
|
next_state <= NOP;
|
466 |
|
|
-- This state is mostly used for 'data propagation'
|
467 |
|
|
-- and control of work of the modular exponentiator
|
468 |
|
|
-- its work/state depends on the 'temp_state' signal.
|
469 |
|
|
-- temp_state = nothing means that this state is not used
|
470 |
|
|
when TEMPORARY_STATE =>
|
471 |
|
|
modExpCtrlRegEn <= '0';
|
472 |
|
|
RDsig <= '0';
|
473 |
|
|
WRsig <= '0';
|
474 |
|
|
dataToModExpEn <= '0';
|
475 |
|
|
dataToModExpShift <= '0';
|
476 |
|
|
dataFromModExpEn <= '0';
|
477 |
|
|
dataFromModExpShift <= '0';
|
478 |
|
|
serialDataCtrCt <= '0';
|
479 |
|
|
serialDataCtrZero <= '0';
|
480 |
|
|
shiftDataCtrCt <= '0';
|
481 |
|
|
shiftDataCtrZero <= '0';
|
482 |
|
|
if (readySig = '1') then
|
483 |
|
|
controlStateOut <= "100";
|
484 |
|
|
next_state <= TEMPORARY_STATE;
|
485 |
|
|
temp_state <= info_st;
|
486 |
|
|
else
|
487 |
|
|
controlStateOut <= "001";
|
488 |
|
|
next_state <= MAKE_MOD_EXP;
|
489 |
|
|
temp_state <= nothing;
|
490 |
|
|
end if;
|
491 |
|
|
|
492 |
|
|
if (temp_state = rd_data) then
|
493 |
|
|
muxCtrl <= '0';
|
494 |
|
|
data_in_ready <= '0';
|
495 |
|
|
next_state <= READ_DATA;
|
496 |
|
|
temp_state <= rd_data;
|
497 |
|
|
elsif (temp_state = mk_fin) then
|
498 |
|
|
muxCtrl <= '0';
|
499 |
|
|
data_in_ready <= '1';
|
500 |
|
|
next_state <= MAKE_MOD_EXP;
|
501 |
|
|
temp_state <= mk_fin;
|
502 |
|
|
elsif (temp_state = dat_out_prop) then
|
503 |
|
|
muxCtrl <= '1';
|
504 |
|
|
data_in_ready <= '0';
|
505 |
|
|
next_state <= DATA_TO_OUT_PROPAGATE;
|
506 |
|
|
temp_state <= dat_out_prop;
|
507 |
|
|
elsif (temp_state = info_st) then
|
508 |
|
|
muxCtrl <= '0';
|
509 |
|
|
data_in_ready <= '0';
|
510 |
|
|
next_state <= INFO_STATE;
|
511 |
|
|
temp_state <= info_st;
|
512 |
|
|
elsif (temp_state = mv_dat) then
|
513 |
|
|
muxCtrl <= '0';
|
514 |
|
|
data_in_ready <= '0';
|
515 |
|
|
next_state <= MOVE_DATA;
|
516 |
|
|
temp_state <= mv_dat;
|
517 |
|
|
else
|
518 |
|
|
muxCtrl <= '0';
|
519 |
|
|
data_in_ready <= '0';
|
520 |
|
|
next_state <= NOP;
|
521 |
|
|
temp_state <= nothing;
|
522 |
|
|
end if;
|
523 |
|
|
end case;
|
524 |
|
|
end process SM;
|
525 |
|
|
|
526 |
|
|
state_modifier : process (clk, reset)
|
527 |
|
|
begin
|
528 |
|
|
if (clk = '1' and clk'Event) then
|
529 |
|
|
if (reset = '1') then
|
530 |
|
|
state <= NOP;
|
531 |
|
|
else
|
532 |
|
|
state <= next_state;
|
533 |
|
|
end if;
|
534 |
|
|
end if;
|
535 |
|
|
end process state_modifier;
|
536 |
|
|
|
537 |
|
|
-- modify for changing width of the hey
|
538 |
|
|
-- in fact it is modified from the properties file
|
539 |
|
|
dataCounter : counter
|
540 |
|
|
generic map(
|
541 |
|
|
size => WORD_INT_LOG + 1
|
542 |
|
|
)
|
543 |
|
|
port map (
|
544 |
|
|
count => serialDataCtrCt,
|
545 |
|
|
zero => serialDataCtrZero,
|
546 |
|
|
output => serialDataCtrOut,
|
547 |
|
|
clk => clk,
|
548 |
|
|
reset => reset
|
549 |
|
|
);
|
550 |
|
|
|
551 |
|
|
shiftCounter : counter
|
552 |
|
|
generic map(
|
553 |
|
|
size => 4
|
554 |
|
|
)
|
555 |
|
|
port map (
|
556 |
|
|
count => shiftDataCtrCt,
|
557 |
|
|
zero => shiftDataCtrZero,
|
558 |
|
|
output => shiftDataCtrOut,
|
559 |
|
|
clk => clk,
|
560 |
|
|
reset => reset
|
561 |
|
|
);
|
562 |
|
|
|
563 |
|
|
end Behavioral;
|