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1 5 gajos
-----------------------------------------------------------------------
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----                                                               ----
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---- Montgomery modular multiplier and exponentiator               ----
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----                                                               ----
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---- This file is part of the Montgomery modular multiplier        ----
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---- and exponentiator project                                     ----
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---- http://opencores.org/project,mod_mult_exp                     ----
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----                                                               ----
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---- Description:                                                  ----
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----   Montgomery modular exponentiator main module. It combines   ----
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----   all subomponents. It takes four numbers as the input:       ----
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----   base, power, modulus and Montgomery residuum                ----
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----   (2^(2*word_length) mod N) and results the modular           ----
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----   exponentiation A^B mod M.                                   ----
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----   In fact input data are read through one input controlled by ----
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----   the ctrl input.                                             ----
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---- To Do:                                                        ----
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----                                                               ----
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---- Author(s):                                                    ----
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---- - Krzysztof Gajewski, gajos@opencores.org                     ----
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----                       k.gajewski@gmail.com                    ----
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----                                                               ----
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-----------------------------------------------------------------------
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----                                                               ----
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---- Copyright (C) 2014 Authors and OPENCORES.ORG                  ----
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----                                                               ----
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---- This source file may be used and distributed without          ----
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---- restriction provided that this copyright statement is not     ----
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---- removed from the file and that any derivative work contains   ----
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---- the original copyright notice and the associated disclaimer.  ----
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----                                                               ----
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---- This source file is free software; you can redistribute it    ----
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---- and-or modify it under the terms of the GNU Lesser General    ----
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---- Public License as published by the Free Software Foundation;  ----
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---- either version 2.1 of the License, or (at your option) any    ----
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---- later version.                                                ----
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----                                                               ----
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---- This source is distributed in the hope that it will be        ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied    ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR       ----
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---- PURPOSE. See the GNU Lesser General Public License for more   ----
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---- details.                                                      ----
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----                                                               ----
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---- You should have received a copy of the GNU Lesser General     ----
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---- Public License along with this source; if not, download it    ----
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---- from http://www.opencores.org/lgpl.shtml                      ----
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----                                                               ----
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-----------------------------------------------------------------------
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library IEEE;
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use work.properties.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity ModExp is
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    generic (
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        word_size   : integer := WORD_LENGTH;
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        word_binary : integer := WORD_INTEGER
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    );
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    Port (
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        input         : in  STD_LOGIC_VECTOR(word_size - 1 downto 0);
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        ctrl          : in  STD_LOGIC_VECTOR(2 downto 0);
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        clk           : in  STD_LOGIC;
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        reset         : in  STD_LOGIC;
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        data_in_ready : in  STD_LOGIC;
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        ready         : out STD_LOGIC;
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        output        : out STD_LOGIC_VECTOR(word_size - 1 downto 0)
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    );
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end ModExp;
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architecture Behavioral of ModExp is
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-- Montgomery modular multiplier component
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component ModularMultiplierIterative is
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    generic (
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        word_size : integer := WORD_LENGTH
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    );
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    port (
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        A       : in  STD_LOGIC_VECTOR(word_size - 1 downto 0);     -- multiplicand
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        B       : in  STD_LOGIC_VECTOR(word_size - 1 downto 0);     -- multiplier
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        M       : in  STD_LOGIC_VECTOR(word_size - 1 downto 0);     -- modulus
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        start   : in  STD_LOGIC;
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        product : out STD_LOGIC_VECTOR(word_size - 1 downto 0); -- product
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        ready   : out STD_LOGIC;
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        clk     : in  STD_LOGIC
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    );
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end component ModularMultiplierIterative;
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-- Block memory component generated through ISE
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-- It is used like multiple cell register
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COMPONENT blockMemory
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    PORT (
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        clka  : in  STD_LOGIC;
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        rsta  : in  STD_LOGIC;
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        wea   : in  STD_LOGIC_VECTOR(0 DOWNTO 0);
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        addra : in  STD_LOGIC_VECTOR(3 DOWNTO 0);
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        dina  : in  STD_LOGIC_VECTOR(word_size - 1 DOWNTO 0);
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        douta : out STD_LOGIC_VECTOR(word_size - 1 DOWNTO 0)
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    );
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END COMPONENT;
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109
-- Register
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component Reg is
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    generic(
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        word_size : integer := WORD_LENGTH
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    );
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    port(
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        input  : in  STD_LOGIC_VECTOR(word_size - 1 downto 0);
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        output : out STD_LOGIC_VECTOR(word_size - 1 downto 0);
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        enable : in  STD_LOGIC;
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        clk    : in  STD_LOGIC;
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        reset  : in  STD_LOGIC
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    );
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end component Reg;
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-- Multiplexer
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component MontMult4inMux is
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    generic (
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        word_size : integer := WORD_LENGTH - 1
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    );
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    port (
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        ctrl   : in  STD_LOGIC_VECTOR(1 downto 0);
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        zero   : in  STD_LOGIC_VECTOR(word_size downto 0);
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        M      : in  STD_LOGIC_VECTOR(word_size downto 0);
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        Y      : in  STD_LOGIC_VECTOR(word_size downto 0);
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        YplusM : in  STD_LOGIC_VECTOR(word_size downto 0);
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        output : out STD_LOGIC_VECTOR(word_size downto 0)
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    );
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end component MontMult4inMux;
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-- State machine
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component ModExpSM is
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    generic(
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        word_size : integer := WORD_LENGTH;
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        word_binary : integer := WORD_INTEGER
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    );
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    port (
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        data_in_ready  : in  STD_LOGIC;
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        clk            : in  STD_LOGIC;
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        exp_ctrl       : in  STD_LOGIC_VECTOR(2 downto 0);
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        reset          : in  STD_LOGIC;
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        in_mux_control : out STD_LOGIC_VECTOR(1 downto 0);
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        -- finalizer end status
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        ready          : out STD_LOGIC;
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        -- control for multiplier
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        modMultStart   : out STD_LOGIC;
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        modMultReady   : in  STD_LOGIC;
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        -- control for memory and registers
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        addr_dataA     : out STD_LOGIC_VECTOR(3 downto 0);
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        addr_dataB     : out STD_LOGIC_VECTOR(3 downto 0);
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        regData_EnA    : out STD_LOGIC_VECTOR(0 downto 0);
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        regData_EnB    : out STD_LOGIC_VECTOR(0 downto 0);
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        regData_EnC    : out STD_LOGIC;
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        regData_EnExponent   : out STD_LOGIC;
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        ExponentData         : in  STD_LOGIC_VECTOR(word_size - 1 downto 0);
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        memory_reset   : out STD_LOGIC
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    );
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end component ModExpSM;
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-- data registers signals
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signal addr_dataA : STD_LOGIC_VECTOR(3 downto 0);
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signal addr_dataB : STD_LOGIC_VECTOR(3 downto 0);
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signal memDataLoadA  : STD_LOGIC_VECTOR(0 downto 0);
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signal memDataLoadB  : STD_LOGIC_VECTOR(0 downto 0);
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signal memDataLoadC  : STD_LOGIC;
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signal memDataLoadExponent : STD_LOGIC;
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signal memDataA  : STD_LOGIC_VECTOR(word_size - 1 downto 0);
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signal memDataB  : STD_LOGIC_VECTOR(word_size - 1 downto 0);
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signal memDataC  : STD_LOGIC_VECTOR(word_size - 1 downto 0);
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signal memDataExponent : STD_LOGIC_VECTOR(word_size - 1 downto 0);
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signal memoryIn  : STD_LOGIC_VECTOR(word_size - 1 downto 0);
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signal in_mux_control : STD_LOGIC_VECTOR(1 downto 0);
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-- signal for multiplier
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signal multStart       : STD_LOGIC;
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signal multReady       : STD_LOGIC;
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signal modMultToBuffer : STD_LOGIC_VECTOR(word_size - 1 downto 0);
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signal zero : STD_LOGIC_VECTOR(word_size - 1 downto 0) := (others => '0');
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signal one  : STD_LOGIC_VECTOR(word_size - 1 downto 0) := (0 => '1', others => '0');
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signal memory_reset : STD_LOGIC;
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begin
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    -- connections between components
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    zero <= (others => '0');
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    one <=  (0 => '1', others => '0');
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    -- Montgomery modular multiplier component
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    modMult : ModularMultiplierIterative
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    port map (
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        A       => memDataA,
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        B       => memDataB,
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        M       => memDataC,
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        start   => multStart,
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        product => modMultToBuffer,
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        ready   => multReady,
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        clk     => clk
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    );
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    -- Multiplexer
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    mux : MontMult4inMux
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    port map (
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        ctrl   => in_mux_control,
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        zero   => zero,
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        M      => one,
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        Y      => modMultToBuffer,
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        YplusM => input,
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        output => memoryIn
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    );
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    -- Block memory for the first input of the multiplier
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    memoryA : blockMemory
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    port map (
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        clka  => clk,
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        rsta  => memory_reset,
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        wea   => memDataLoadA,
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        addra => addr_dataA,
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        dina  => memoryIn,
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        douta => memDataA
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    );
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    -- Block memory for the second input of the multiplier
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    memoryB : blockMemory
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    port map (
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        clka  => clk,
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        rsta  => memory_reset,
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        wea   => memDataLoadB,
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        addra => addr_dataB,
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        dina  => memoryIn,
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        douta => memDataB
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    );
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    -- Register for the modulus for the multiplier
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    memoryModulus : Reg
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    port map (
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        input  => memoryIn,
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        output => memDataC,
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        enable => memDataLoadC,
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        clk    => clk,
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        reset  => memory_reset
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    );
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    -- Register for the exponent - it feeds also the state machine for the control of the exponentiation process
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    memoryExponent : Reg
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    port map (
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        input  => memoryIn,
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        output => memDataExponent,
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        enable => memDataLoadExponent,
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        clk    => clk,
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        reset  => memory_reset
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    );
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    -- State machine of the Montgomery modular exponentiator
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    stateMachine : ModExpSM
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    port map(
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        data_in_ready  => data_in_ready,
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        clk            => clk,
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        exp_ctrl       => ctrl,
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        reset          => reset,
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        in_mux_control => in_mux_control,
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        ready          => ready,
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        modMultStart   => multStart,
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        modMultReady   => multReady,
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        addr_dataA     => addr_dataA,
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        addr_dataB     => addr_dataB,
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        regData_EnA    => memDataLoadA,
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        regData_EnB    => memDataLoadB,
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        regData_EnC    => memDataLoadC,
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        regData_EnExponent   => memDataLoadExponent,
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        ExponentData         => memDataExponent,
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        memory_reset   => memory_reset
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    );
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    output <= memDataA;
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end Behavioral;

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