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[/] [mod_mult_exp/] [trunk/] [rtl/] [vhdl/] [mod_exp/] [blockMemory32/] [blockMemory/] [implement/] [planAhead_rdn.tcl] - Blame information for rev 5

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# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
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# 
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# This file contains confidential and proprietary information
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# of Xilinx, Inc. and is protected under U.S. and
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# international copyright and other intellectual property
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# laws.
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# 
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# DISCLAIMER
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# This disclaimer is not a license and does not grant any
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# rights to the materials distributed herewith. Except as
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# otherwise provided in a valid license issued to you by
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# Xilinx, and to the maximum extent permitted by applicable
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# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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# (2) Xilinx shall not be liable (whether in contract or tort,
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# CRITICAL APPLICATIONS
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# Applications"). Customer assumes the sole risk and
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# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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set device xc3s500efg320-5
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set projName blockMemory
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set design blockMemory
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set projDir [file dirname [info script]]
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create_project $projName $projDir/results/$projName -part $device -force
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set_property design_mode RTL [current_fileset -srcset]
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set top_module blockMemory_exdes
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add_files -norecurse {../../example_design/blockMemory_exdes.vhd}
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add_files -norecurse {./blockMemory.ngc}
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import_files -fileset [get_filesets constrs_1] -force -norecurse {../../example_design/blockMemory_exdes.xdc}
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set_property top blockMemory_exdes [get_property srcset [current_run]]
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synth_design
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opt_design
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place_design
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route_design
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write_sdf -rename_top_module blockMemory_exdes -file routed.sdf
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write_vhdl -mode sim routed.vhd
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report_timing -nworst 30 -path_type full -file routed.twr
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report_drc -file report.drc
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write_bitstream -bitgen_options {-g UnconstrainedPins:Allow}

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