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[/] [mod_mult_exp/] [trunk/] [rtl/] [vhdl/] [mod_exp/] [blockMemory32/] [blockMemory/] [simulation/] [blockMemory_tb.vhd] - Blame information for rev 5

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1 5 gajos
--------------------------------------------------------------------------------
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--
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-- BLK MEM GEN v7_1 Core - Top File for the Example Testbench
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--
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--------------------------------------------------------------------------------
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--
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-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
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--
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-- This file contains confidential and proprietary information
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-- of Xilinx, Inc. and is protected under U.S. and
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-- international copyright and other intellectual property
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-- laws.
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--
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-- DISCLAIMER
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-- This disclaimer is not a license and does not grant any
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-- rights to the materials distributed herewith. Except as
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-- otherwise provided in a valid license issued to you by
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-- Xilinx, and to the maximum extent permitted by applicable
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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-- (2) Xilinx shall not be liable (whether in contract or tort,
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-- including negligence, or under any other theory of
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-- liability) for any loss or damage of any kind or nature
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-- related to, arising under or in connection with these
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-- materials, including for any direct, or any indirect,
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-- special, incidental, or consequential loss or damage
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-- (including loss of data, profits, goodwill, or any type of
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-- loss or damage suffered as a result of any action brought
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-- by a third party) even if such damage or loss was
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-- reasonably foreseeable or Xilinx had been advised of the
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-- possibility of the same.
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--
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-- CRITICAL APPLICATIONS
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-- Xilinx products are not designed or intended to be fail-
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-- safe, or for use in any application requiring fail-safe
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-- performance, such as life-support or safety devices or
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-- systems, Class III medical devices, nuclear facilities,
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-- applications related to the deployment of airbags, or any
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-- other applications that could lead to death, personal
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-- injury, or severe property or environmental damage
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-- (individually and collectively, "Critical
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-- Applications"). Customer assumes the sole risk and
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-- liability of any use of Xilinx products in Critical
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-- Applications, subject only to applicable laws and
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-- regulations governing limitations on product liability.
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--
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-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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-- PART OF THIS FILE AT ALL TIMES.
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--------------------------------------------------------------------------------
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-- Filename: blockMemory_tb.vhd
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-- Description:
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--  Testbench Top
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--------------------------------------------------------------------------------
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-- Author: IP Solutions Division
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--
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-- History: Sep 12, 2011 - First Release
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--------------------------------------------------------------------------------
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--
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--------------------------------------------------------------------------------
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-- Library Declarations
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--------------------------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.STD_LOGIC_ARITH.ALL;
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USE IEEE.STD_LOGIC_UNSIGNED.ALL;
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LIBRARY work;
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USE work.ALL;
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ENTITY blockMemory_tb IS
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END ENTITY;
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ARCHITECTURE blockMemory_tb_ARCH OF blockMemory_tb IS
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 SIGNAL  STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
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 SIGNAL  CLK :  STD_LOGIC := '1';
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 SIGNAL  RESET : STD_LOGIC;
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 BEGIN
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 CLK_GEN: PROCESS BEGIN
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     CLK <= NOT CLK;
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     WAIT FOR 100 NS;
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     CLK <= NOT CLK;
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     WAIT FOR 100 NS;
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  END PROCESS;
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  RST_GEN: PROCESS BEGIN
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    RESET <= '1';
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    WAIT FOR 1000 NS;
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    RESET <= '0';
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    WAIT;
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  END PROCESS;
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--STOP_SIM: PROCESS BEGIN
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-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
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--   ASSERT FALSE
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--     REPORT "END SIMULATION TIME REACHED"
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--     SEVERITY FAILURE;
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--END PROCESS;
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--
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PROCESS BEGIN
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  WAIT UNTIL STATUS(8)='1';
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  IF( STATUS(7 downto 0)/="0") THEN
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    ASSERT false
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     REPORT "Simulation Failed"
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         SEVERITY FAILURE;
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  ELSE
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   ASSERT false
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     REPORT "Simulation Complete"
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         SEVERITY FAILURE;
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  END IF;
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END PROCESS;
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  blockMemory_synth_inst:ENTITY work.blockMemory_synth
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  PORT MAP(
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           CLK_IN   => CLK,
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           RESET_IN => RESET,
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           STATUS   => STATUS
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          );
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END ARCHITECTURE;

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