OpenCores
URL https://opencores.org/ocsvn/mod_mult_exp/mod_mult_exp/trunk

Subversion Repositories mod_mult_exp

[/] [mod_mult_exp/] [trunk/] [rtl/] [vhdl/] [mod_exp/] [blockMemory32/] [coregen.cgp] - Blame information for rev 5

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 5 gajos
SET busformat = BusFormatAngleBracketNotRipped
2
SET designentry = VHDL
3
SET device = xc3s500e
4
SET devicefamily = spartan3e
5
SET flowvendor = Other
6
SET package = fg320
7
SET speedgrade = -5
8
SET verilogsim = false
9
SET vhdlsim = true

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.