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gajos |
INFO:sim:172 - Generating IP...
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Applying current project options...
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Finished applying current project options.
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WARNING:sim - A core named 'blockMemory' already exists in the project. Output
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products for this core may be overwritten.
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Resolving generics for 'blockMemory'...
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WARNING:sim - A core named 'blockMemory' already exists in the project. Output
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products for this core may be overwritten.
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Applying external generics to 'blockMemory'...
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Delivering associated files for 'blockMemory'...
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WARNING:sim - Component blk_mem_gen_v7_1 does not have a valid model name for
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VHDL synthesis
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Delivering EJava files for 'blockMemory'...
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Generating implementation netlist for 'blockMemory'...
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INFO:sim - Pre-processing HDL files for 'blockMemory'...
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Running synthesis for 'blockMemory'
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Running ngcbuild...
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Writing VHO instantiation template for 'blockMemory'...
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Writing VHDL behavioral simulation model for 'blockMemory'...
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Generating ASY schematic symbol...
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INFO:sim:949 - Finished generation of ASY schematic symbol.
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Generating SYM schematic symbol for 'blockMemory'...
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Generating metadata file...
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Generating ISE project...
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XCO file found: blockMemory.xco
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XMDF file found: blockMemory_xmdf.tcl
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Adding E:/spent i
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praca/OpenCores/ModMultExp_opencores_edition/rtl/vhdl/mod_exp/blockMemory/tmp/_c
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g/blockMemory.asy -view all -origin_type imported
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Adding E:/spent i
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praca/OpenCores/ModMultExp_opencores_edition/rtl/vhdl/mod_exp/blockMemory/tmp/_c
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g/blockMemory.ngc -view all -origin_type created
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Checking file "E:/spent i
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praca/OpenCores/ModMultExp_opencores_edition/rtl/vhdl/mod_exp/blockMemory/tmp/_c
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g/blockMemory.ngc" for project device match ...
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File "E:/spent i
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praca/OpenCores/ModMultExp_opencores_edition/rtl/vhdl/mod_exp/blockMemory/tmp/_c
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g/blockMemory.ngc" device information matches project device.
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Adding E:/spent i
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praca/OpenCores/ModMultExp_opencores_edition/rtl/vhdl/mod_exp/blockMemory/tmp/_c
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g/blockMemory.sym -view all -origin_type imported
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Adding E:/spent i
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praca/OpenCores/ModMultExp_opencores_edition/rtl/vhdl/mod_exp/blockMemory/tmp/_c
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g/blockMemory.vhd -view all -origin_type created
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INFO:HDLCompiler:1061 - Parsing VHDL file "E:/spent i
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praca/OpenCores/ModMultExp_opencores_edition/rtl/vhdl/mod_exp/blockMemory/tmp
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/_cg/blockMemory.vhd" into library work
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INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
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Adding E:/spent i
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praca/OpenCores/ModMultExp_opencores_edition/rtl/vhdl/mod_exp/blockMemory/tmp/_c
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g/blockMemory.vho -view all -origin_type imported
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INFO:TclTasksC:2116 - The automatic calculation of top has been turned-off.
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Please set the new top explicitly by running the "project set top" command.
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To re-calculate the new top automatically, set the "Auto Implementation Top"
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property to true.
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Top level has been set to "/blockMemory"
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Generating README file...
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Generating FLIST file...
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INFO:sim:948 - Finished FLIST file generation.
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Launching README viewer...
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Moving files to output directory...
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Finished moving files to output directory
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Wrote CGP file for project 'blockMemory'.
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