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[/] [mod_mult_exp/] [trunk/] [rtl/] [vhdl/] [mod_exp/] [blockMemory512/] [blockMemory/] [simulation/] [blockMemory_synth.vhd] - Blame information for rev 5

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--------------------------------------------------------------------------------
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--
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-- BLK MEM GEN v7_1 Core - Synthesizable Testbench
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--
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--------------------------------------------------------------------------------
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--
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-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
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--
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-- This file contains confidential and proprietary information
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-- of Xilinx, Inc. and is protected under U.S. and
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-- international copyright and other intellectual property
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-- laws.
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--
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-- DISCLAIMER
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-- This disclaimer is not a license and does not grant any
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-- rights to the materials distributed herewith. Except as
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-- otherwise provided in a valid license issued to you by
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-- Xilinx, and to the maximum extent permitted by applicable
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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-- (2) Xilinx shall not be liable (whether in contract or tort,
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-- including negligence, or under any other theory of
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-- liability) for any loss or damage of any kind or nature
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-- related to, arising under or in connection with these
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-- materials, including for any direct, or any indirect,
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-- special, incidental, or consequential loss or damage
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-- (including loss of data, profits, goodwill, or any type of
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-- loss or damage suffered as a result of any action brought
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-- by a third party) even if such damage or loss was
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-- reasonably foreseeable or Xilinx had been advised of the
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-- possibility of the same.
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--
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-- CRITICAL APPLICATIONS
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-- Xilinx products are not designed or intended to be fail-
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-- safe, or for use in any application requiring fail-safe
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-- performance, such as life-support or safety devices or
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-- systems, Class III medical devices, nuclear facilities,
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-- applications related to the deployment of airbags, or any
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-- other applications that could lead to death, personal
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-- injury, or severe property or environmental damage
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-- (individually and collectively, "Critical
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-- Applications"). Customer assumes the sole risk and
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-- liability of any use of Xilinx products in Critical
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-- Applications, subject only to applicable laws and
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-- regulations governing limitations on product liability.
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--
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-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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-- PART OF THIS FILE AT ALL TIMES.
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--------------------------------------------------------------------------------
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--
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-- Filename: blockMemory_synth.vhd
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--
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-- Description:
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--  Synthesizable Testbench
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--------------------------------------------------------------------------------
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-- Author: IP Solutions Division
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--
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-- History: Sep 12, 2011 - First Release
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--------------------------------------------------------------------------------
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--
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--------------------------------------------------------------------------------
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-- Library Declarations
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--------------------------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.STD_LOGIC_UNSIGNED.ALL;
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USE IEEE.STD_LOGIC_ARITH.ALL;
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USE IEEE.NUMERIC_STD.ALL;
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USE IEEE.STD_LOGIC_MISC.ALL;
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LIBRARY STD;
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USE STD.TEXTIO.ALL;
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--LIBRARY unisim;
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--USE unisim.vcomponents.ALL;
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LIBRARY work;
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USE work.ALL;
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USE work.BMG_TB_PKG.ALL;
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ENTITY blockMemory_synth IS
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PORT(
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        CLK_IN     : IN  STD_LOGIC;
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    RESET_IN   : IN  STD_LOGIC;
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    STATUS     : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0')   --ERROR STATUS OUT OF FPGA
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    );
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END ENTITY;
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ARCHITECTURE blockMemory_synth_ARCH OF blockMemory_synth IS
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COMPONENT blockMemory_exdes
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  PORT (
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      --Inputs - Port A
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    RSTA           : IN STD_LOGIC;  --opt port
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    WEA            : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
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    ADDRA          : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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    DINA           : IN STD_LOGIC_VECTOR(511 DOWNTO 0);
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    DOUTA          : OUT STD_LOGIC_VECTOR(511 DOWNTO 0);
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    CLKA       : IN STD_LOGIC
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  );
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END COMPONENT;
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  SIGNAL CLKA: STD_LOGIC := '0';
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  SIGNAL RSTA: STD_LOGIC := '0';
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  SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
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  SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
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  SIGNAL ADDRA: STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
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  SIGNAL ADDRA_R: STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
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  SIGNAL DINA: STD_LOGIC_VECTOR(511 DOWNTO 0) := (OTHERS => '0');
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  SIGNAL DINA_R: STD_LOGIC_VECTOR(511 DOWNTO 0) := (OTHERS => '0');
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  SIGNAL DOUTA: STD_LOGIC_VECTOR(511 DOWNTO 0);
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  SIGNAL CHECKER_EN : STD_LOGIC:='0';
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  SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
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  SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
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  SIGNAL clk_in_i: STD_LOGIC;
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  SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
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  SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
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  SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
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  SIGNAL ITER_R0 : STD_LOGIC := '0';
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  SIGNAL ITER_R1 : STD_LOGIC := '0';
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  SIGNAL ITER_R2 : STD_LOGIC := '0';
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  SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
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  SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
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  BEGIN
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--  clk_buf: bufg
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--    PORT map(
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--      i => CLK_IN,
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--      o => clk_in_i
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--    );
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   clk_in_i <= CLK_IN;
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   CLKA <= clk_in_i;
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   RSTA <= RESET_SYNC_R3 AFTER 50 ns;
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   PROCESS(clk_in_i)
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   BEGIN
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      IF(RISING_EDGE(clk_in_i)) THEN
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                 RESET_SYNC_R1 <= RESET_IN;
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                 RESET_SYNC_R2 <= RESET_SYNC_R1;
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                 RESET_SYNC_R3 <= RESET_SYNC_R2;
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          END IF;
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   END PROCESS;
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PROCESS(CLKA)
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BEGIN
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  IF(RISING_EDGE(CLKA)) THEN
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    IF(RESET_SYNC_R3='1') THEN
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        ISSUE_FLAG_STATUS<= (OTHERS => '0');
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          ELSE
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        ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
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   END IF;
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  END IF;
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END PROCESS;
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STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
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   BMG_DATA_CHECKER_INST: ENTITY work.CHECKER
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      GENERIC MAP (
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         WRITE_WIDTH => 512,
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                 READ_WIDTH  => 512      )
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      PORT MAP (
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         CLK     => CLKA,
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         RST     => RSTA,
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         EN      => CHECKER_EN_R,
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         DATA_IN => DOUTA,
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         STATUS  => ISSUE_FLAG(0)
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           );
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   PROCESS(CLKA)
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   BEGIN
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      IF(RISING_EDGE(CLKA)) THEN
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         IF(RSTA='1') THEN
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                    CHECKER_EN_R <= '0';
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             ELSE
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                    CHECKER_EN_R <= CHECKER_EN AFTER 50 ns;
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         END IF;
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      END IF;
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   END PROCESS;
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    BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
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     PORT MAP(
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                CLK => clk_in_i,
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                RST => RSTA,
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                ADDRA  => ADDRA,
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                DINA => DINA,
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                WEA => WEA,
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                    CHECK_DATA => CHECKER_EN
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             );
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      PROCESS(CLKA)
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      BEGIN
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        IF(RISING_EDGE(CLKA)) THEN
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                  IF(RESET_SYNC_R3='1') THEN
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                        STATUS(8) <= '0';
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                        iter_r2 <= '0';
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                        iter_r1 <= '0';
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                        iter_r0 <= '0';
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                  ELSE
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                        STATUS(8) <= iter_r2;
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                        iter_r2 <= iter_r1;
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                        iter_r1 <= iter_r0;
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                        iter_r0 <= STIMULUS_FLOW(8);
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              END IF;
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            END IF;
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      END PROCESS;
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      PROCESS(CLKA)
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      BEGIN
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        IF(RISING_EDGE(CLKA)) THEN
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                  IF(RESET_SYNC_R3='1') THEN
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                      STIMULUS_FLOW <= (OTHERS => '0');
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           ELSIF(WEA(0)='1') THEN
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                      STIMULUS_FLOW <= STIMULUS_FLOW+1;
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         END IF;
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            END IF;
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      END PROCESS;
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      PROCESS(CLKA)
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      BEGIN
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        IF(RISING_EDGE(CLKA)) THEN
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                  IF(RESET_SYNC_R3='1') THEN
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            WEA_R  <= (OTHERS=>'0') AFTER 50 ns;
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            DINA_R <= (OTHERS=>'0') AFTER 50 ns;
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           ELSE
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            WEA_R  <= WEA AFTER 50 ns;
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            DINA_R <= DINA AFTER 50 ns;
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         END IF;
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            END IF;
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      END PROCESS;
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      PROCESS(CLKA)
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      BEGIN
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        IF(RISING_EDGE(CLKA)) THEN
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                  IF(RESET_SYNC_R3='1') THEN
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            ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
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          ELSE
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            ADDRA_R <= ADDRA AFTER 50 ns;
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          END IF;
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            END IF;
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      END PROCESS;
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    BMG_PORT: blockMemory_exdes PORT MAP (
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      --Port A
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      RSTA       => RSTA,
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      WEA        => WEA_R,
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      ADDRA      => ADDRA_R,
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      DINA       => DINA_R,
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      DOUTA      => DOUTA,
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      CLKA       => CLKA
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    );
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END ARCHITECTURE;

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